13 Commits

Author	SHA1	Message	Date
tychovrahe	4ed70cc9bc	chore(core): remove useless MPU_MODE_KERNEL_SRAM ... [no changelog]	2024-11-14 09:30:07 +01:00
cepetr	7b6f444751	refactor(core): introduce global trezor_rtl/bsp/model headers ... [no changelog]	2024-11-05 10:00:31 +01:00
cepetr	76891323f6	feat(core): added access control for framebuffer ... [no changelog]	2024-10-22 09:40:13 +02:00
tychovrahe	57f72d5aa7	fix(core): use secure-unprivileged SAES XOR key for storage encryption ... [no changelog]	2024-09-24 12:21:53 +02:00
tychovrahe	28f420189a	refactor(core): combined build of coreapp + kernel, linker scripts refactoring ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	1c991339ce	refactor(core/embed): split firmware into kernel & coreapp ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	7f3cff04f1	refactor(core/embed): introduce new mpu driver ... [no changelog]	2024-09-24 12:21:53 +02:00
tychovrahe	5106ac7aa3	feat(core): support optiga handling on U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	cec0191360	fix(core): fix bootloader update on STM32U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	8150636a81	feat(core): add basic support for STM32U5	2024-02-29 23:05:56 +01:00
tychovrahe	5470304515	feat(core): Implement OPTIGA provisioning in prodtest. ... [no changelog]	2023-08-29 10:59:34 +02:00
Pavol Rusnak	54d348228f	all: rename TREZOR to Trezor where possible	2019-06-17 20:28:29 +02:00
matejcik	e5670856a2	MONOREPO CREATE FROM trezor-core	2019-04-15 19:14:40 +02:00