8 Commits

Author	SHA1	Message	Date
tychovrahe	354dad617d	fix(core): fix vector table alignment on STM32U5 ... [no changelog]	2024-07-16 16:38:48 +02:00
tychovrahe	b3d1ba25d9	perf(core): optimize boot speed by checking empty image area by words ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	c3f84e2949	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]	2024-02-29 23:05:56 +01:00
grdddj	b8ea21d24a	feat(all): implement translations into Trezor ... Co-authored-by matejcik <ja@matejcik.cz>	2024-02-12 14:49:32 +01:00
cepetr	02f34a2748	feat(core/bootloader): check firmware padding	2023-10-27 16:41:56 +02:00
cepetr	ba83a7e644	feat(core): introduce interaction-less upgrade	2023-10-27 16:15:15 +02:00
tychovrahe	8a4f376f20	refactor(core): prepare fw for differently sized fw chunks ... [no changelog]	2023-10-20 16:33:53 +02:00
tychovrahe	238e3fd7c1	refactor(core): add abstraction over flash memory layout ... [no changelog]	2023-07-25 10:25:20 +02:00