From be598582f5cc2de808c70e74526a98667566ca4c Mon Sep 17 00:00:00 2001 From: Pavol Rusnak Date: Thu, 7 Sep 2017 20:45:43 +0200 Subject: [PATCH] trezorhal: remove trezorhal/hal directory --- SConscript.boardloader | 1 - SConscript.bootloader | 3 +- SConscript.firmware | 1 - embed/trezorhal/hal/stm32f4xx_hal_sram.c | 693 ----------- embed/trezorhal/hal/stm32f4xx_hal_sram.h | 207 ---- embed/trezorhal/hal/stm32f4xx_ll_fsmc.c | 1026 ---------------- embed/trezorhal/hal/stm32f4xx_ll_fsmc.h | 1049 ----------------- .../trezorhal/{hal => }/stm32f4xx_hal_conf.h | 0 8 files changed, 1 insertion(+), 2979 deletions(-) delete mode 100644 embed/trezorhal/hal/stm32f4xx_hal_sram.c delete mode 100644 embed/trezorhal/hal/stm32f4xx_hal_sram.h delete mode 100644 embed/trezorhal/hal/stm32f4xx_ll_fsmc.c delete mode 100644 embed/trezorhal/hal/stm32f4xx_ll_fsmc.h rename embed/trezorhal/{hal => }/stm32f4xx_hal_conf.h (100%) diff --git a/SConscript.boardloader b/SConscript.boardloader index c69235d8ce..1bbfa84126 100644 --- a/SConscript.boardloader +++ b/SConscript.boardloader @@ -108,7 +108,6 @@ env.Replace( CPPPATH=[ 'embed/boardloader', 'embed/trezorhal', - 'embed/trezorhal/hal', 'embed/extmod/modtrezorui', 'vendor/micropython/stmhal', 'vendor/micropython/ports/stm32', diff --git a/SConscript.bootloader b/SConscript.bootloader index 19f6338a17..c78545f0f4 100644 --- a/SConscript.bootloader +++ b/SConscript.bootloader @@ -128,7 +128,6 @@ env.Replace( 'embed/bootloader/nanopb', 'embed/bootloader/protob', 'embed/trezorhal', - 'embed/trezorhal/hal', 'embed/extmod/modtrezorui', 'vendor/micropython/ports/stm32', 'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Inc', @@ -171,4 +170,4 @@ program_bin = env.Command( action=[ '$OBJCOPY -O binary -j .header -j .flash -j .data $SOURCE $TARGET', '$BINCTL $TARGET -s 1 4141414141414141414141414141414141414141414141414141414141414141', - ], ) \ No newline at end of file + ], ) diff --git a/SConscript.firmware b/SConscript.firmware index 68ef26a03f..52df3a4cb9 100644 --- a/SConscript.firmware +++ b/SConscript.firmware @@ -329,7 +329,6 @@ env.Replace( '.', 'embed/firmware', 'embed/trezorhal', - 'embed/trezorhal/hal', 'embed/extmod/modtrezorui', 'vendor/micropython', 'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Inc', diff --git a/embed/trezorhal/hal/stm32f4xx_hal_sram.c b/embed/trezorhal/hal/stm32f4xx_hal_sram.c deleted file mode 100644 index 10ace0c28a..0000000000 --- a/embed/trezorhal/hal/stm32f4xx_hal_sram.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_sram.c - * @author MCD Application Team - * @version V1.5.2 - * @date 22-September-2016 - * @brief SRAM HAL module driver. - * This file provides a generic firmware to drive SRAM memories - * mounted as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SRAM memories. It uses the FMC layer functions to interface - with SRAM devices. - The following sequence should be followed to configure the FMC/FSMC to interface - with SRAM/PSRAM memories: - - (#) Declare a SRAM_HandleTypeDef handle structure, for example: - SRAM_HandleTypeDef hsram; and: - - (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SRAM device - - (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined - base register instance for NOR or SRAM extended mode - - (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended - mode timings; for example: - FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() - (##) Control register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Init() - (##) Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Timing_Init() - (##) Extended mode Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Extended_Timing_Init() - (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access - (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ - HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation - - (#) You can continuously monitor the SRAM device HAL state by calling the function - HAL_SRAM_GetState() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup SRAM SRAM - * @brief SRAM driver modules - * @{ - */ -#ifdef HAL_SRAM_MODULE_ENABLED - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SRAM_Exported_Functions SRAM Exported Functions - * @{ - */ -/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### SRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize/de-initialize - the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the SRAM handle parameter */ - if(hsram == NULL) - { - return HAL_ERROR; - } - - if(hsram->State == HAL_SRAM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsram->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ - HAL_SRAM_MspInit(hsram); - } - - /* Initialize SRAM control Interface */ - FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); - - /* Initialize SRAM timing Interface */ - FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); - - /* Initialize SRAM extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); - - return HAL_OK; -} - -/** - * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) -{ - /* De-Initialize the low level hardware (MSP) */ - HAL_SRAM_MspDeInit(hsram); - - /* Configure the SRAM registers with their reset values */ - FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); - - hsram->State = HAL_SRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief SRAM MSP Init. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SRAM MSP DeInit. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) - { - *pDstBuffer = *(__IO uint8_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) - { - *(__IO uint8_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) - { - *pDstBuffer = *(__IO uint16_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) - { - *(__IO uint16_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) - { - *pDstBuffer = *(__IO uint32_t *)pAddress; - pDstBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) - { - *(__IO uint32_t *)pAddress = *pSrcBuffer; - pSrcBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### SRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SRAM controller state - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL state - */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) -{ - return hsram->State; -} -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx */ -#endif /* HAL_SRAM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/embed/trezorhal/hal/stm32f4xx_hal_sram.h b/embed/trezorhal/hal/stm32f4xx_hal_sram.h deleted file mode 100644 index 2fa7368e67..0000000000 --- a/embed/trezorhal/hal/stm32f4xx_hal_sram.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_sram.h - * @author MCD Application Team - * @version V1.5.2 - * @date 22-September-2016 - * @brief Header file of SRAM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_SRAM_H -#define __STM32F4xx_HAL_SRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx*/ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) - -/** @addtogroup SRAM - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Types SRAM Exported Types - * @{ - */ -/** - * @brief HAL SRAM State structures definition - */ -typedef enum -{ - HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ - -}HAL_SRAM_StateTypeDef; - -/** - * @brief SRAM handle Structure definition - */ -typedef struct -{ - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - - FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - - FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - - __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - - DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -}SRAM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ -/** @brief Reset SRAM handle state - * @param __HANDLE__: SRAM handle - * @retval None - */ -#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup SRAM_Exported_Functions - * @{ - */ - -/** @addtogroup SRAM_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); - -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group3 - * @{ - */ -/* SRAM Control functions ******************************************************/ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group4 - * @{ - */ -/* SRAM State functions *********************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx */ -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_SRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/embed/trezorhal/hal/stm32f4xx_ll_fsmc.c b/embed/trezorhal/hal/stm32f4xx_ll_fsmc.c deleted file mode 100644 index 952be8ee52..0000000000 --- a/embed/trezorhal/hal/stm32f4xx_ll_fsmc.c +++ /dev/null @@ -1,1026 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_fsmc.c - * @author MCD Application Team - * @version V1.5.2 - * @date 22-September-2016 - * @brief FSMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FSMC peripheral features ##### - ============================================================================== - [..] The Flexible static memory controller (FSMC) includes two memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND/PC Card memory controller - - [..] The FSMC functional block makes the interface with synchronous and asynchronous static - memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FSMC performs - only one access at a time to an external device. - The main features of the FSMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) Read-only memory (ROM). - (++) NOR Flash memory/OneNAND Flash memory. - (++) PSRAM (4 memory banks). - (++) 16-bit PC Card compatible devices. - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data. - (+) Independent Chip Select control for each memory bank. - (+) Independent configuration for each memory bank. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup FSMC_LL FSMC Low Layer - * @brief FSMC driver modules - * @{ - */ - -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FSMC_LL_Private_Functions - * @{ - */ - -/** @addtogroup FSMC_LL_NORSRAM - * @brief NORSRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use NORSRAM device driver ##### - ============================================================================== - - [..] - This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() - (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() - (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() - (+) FSMC NORSRAM bank extended timing configuration using the function - FSMC_NORSRAM_Extended_Timing_Init() - (+) FSMC NORSRAM bank enable/disable write operation using the functions - FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() - -@endverbatim - * @{ - */ - -/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FSMC NORSRAM interface - (+) De-initialize the FSMC NORSRAM interface - (+) Configure the FSMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FSMC_NORSRAM device according to the specified - * control parameters in the FSMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FSMC_MUX(Init->DataAddressMux)); - assert_param(IS_FSMC_MEMORY(Init->MemoryType)); - assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) - assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); - assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock)); -#endif /* STM32F412Zx || TM32F412Vx */ - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ - FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ - FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW)); - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->PageSize |\ - Init->WriteBurst - ); -#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \ - FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \ - FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \ - FSMC_BCR1_WFDIS)); - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - - if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) - { - tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - - Device->BTCR[Init->NSBank] = tmpr; - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) - /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) - { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); - } - - if(Init->NSBank != FSMC_NORSRAM_BANK1) - { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); - } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ - - return HAL_OK; -} - -/** - * @brief DeInitialize the FSMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Disable the FSMC_NORSRAM device */ - __FSMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FSMC_NORSRAM device */ - /* FSMC_NORSRAM_BANK1 */ - if(Bank == FSMC_NORSRAM_BANK1) - { - Device->BTCR[Bank] = 0x000030DBU; - } - /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ - else - { - Device->BTCR[Bank] = 0x000030D2U; - } - - Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; - - return HAL_OK; -} - - -/** - * @brief Initialize the FSMC_NORSRAM Timing according to the specified - * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1U]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ - FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ - FSMC_BTR1_ACCMOD)); - - /* Set FSMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (((Timing->CLKDivision)-1U) << 20U) |\ - (((Timing->DataLatency)-2U) << 24U) |\ - (Timing->AccessMode)); - - Device->BTCR[Bank + 1] = tmpr; - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) - /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) - { - tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U)); - tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U); - Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr; - } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ - - return HAL_OK; -} - -/** - * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ - FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFFU; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FSMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FSMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Enable write operation */ - Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Disable write operation */ - Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @addtogroup FSMC_LL_NAND - * @brief NAND Controller functions - * - @verbatim - ============================================================================== - ##### How to use NAND device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FSMC NAND banks in order - to run the NAND external devices. - - (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() - (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() - (+) FSMC NAND bank common space timing configuration using the function - FSMC_NAND_CommonSpace_Timing_Init() - (+) FSMC NAND bank attribute space timing configuration using the function - FSMC_NAND_AttributeSpace_Timing_Init() - (+) FSMC NAND bank enable/disable ECC correction feature using the functions - FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() - (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() - -@endverbatim - * @{ - */ - -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FSMC NAND interface - (+) De-initialize the FSMC NAND interface - (+) Configure the FSMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FSMC_NAND device according to the specified - * control parameters in the FSMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - - if(Init->NandBank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ - FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ - FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); - - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - if(Init->NandBank == FSMC_NAND_BANK2) - { - /* NAND bank 2 registers configuration */ - Device->PCR2 = tmpr; - } - else - { - /* NAND bank 3 registers configuration */ - Device->PCR3 = tmpr; - } - - return HAL_OK; -} - -/** - * @brief Initializes the FSMC_NAND Common space Timing according to the specified - * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ - FSMC_PMEM2_MEMHIZ2)); - - /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) - { - /* NAND bank 2 registers configuration */ - Device->PMEM2 = tmpr; - } - else - { - /* NAND bank 3 registers configuration */ - Device->PMEM3 = tmpr; - } - - return HAL_OK; -} - -/** - * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified - * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ - FSMC_PATT2_ATTHIZ2)); - - /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) - { - /* NAND bank 2 registers configuration */ - Device->PATT2 = tmpr; - } - else - { - /* NAND bank 3 registers configuration */ - Device->PATT3 = tmpr; - } - - return HAL_OK; -} - -/** - * @brief DeInitializes the FSMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Disable the NAND Bank */ - __FSMC_NAND_DISABLE(Device, Bank); - - /* De-initialize the NAND Bank */ - if(Bank == FSMC_NAND_BANK2) - { - /* Set the FSMC_NAND_BANK2 registers to their reset values */ - Device->PCR2 = 0x00000018U; - Device->SR2 = 0x00000040U; - Device->PMEM2 = 0xFCFCFCFCU; - Device->PATT2 = 0xFCFCFCFCU; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_NAND_BANK3 registers to their reset values */ - Device->PCR3 = 0x00000018U; - Device->SR3 = 0x00000040U; - Device->PMEM3 = 0xFCFCFCFCU; - Device->PATT3 = 0xFCFCFCFCU; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FSMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FSMC NAND interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Enable ECC feature */ - if(Bank == FSMC_NAND_BANK2) - { - Device->PCR2 |= FSMC_PCR2_ECCEN; - } - else - { - Device->PCR3 |= FSMC_PCR3_ECCEN; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Disable ECC feature */ - if(Bank == FSMC_NAND_BANK2) - { - Device->PCR2 &= ~FSMC_PCR2_ECCEN; - } - else - { - Device->PCR3 &= ~FSMC_PCR3_ECCEN; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_NAND_DEVICE(Device)); - assert_param(IS_FSMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the ECCR2 register value */ - *ECCval = (uint32_t)Device->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - *ECCval = (uint32_t)Device->ECCR3; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FSMC_LL_PCCARD - * @brief PCCARD Controller functions - * - @verbatim - ============================================================================== - ##### How to use PCCARD device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FSMC PCCARD bank in order - to run the PCCARD/compact flash external devices. - - (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() - (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() - (+) FSMC PCCARD bank common space timing configuration using the function - FSMC_PCCARD_CommonSpace_Timing_Init() - (+) FSMC PCCARD bank attribute space timing configuration using the function - FSMC_PCCARD_AttributeSpace_Timing_Init() - (+) FSMC PCCARD bank IO space timing configuration using the function - FSMC_PCCARD_IOSpace_Timing_Init() - -@endverbatim - * @{ - */ - -/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FSMC PCCARD interface - (+) De-initialize the FSMC PCCARD interface - (+) Configure the FSMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FSMC_PCCARD device according to the specified - * control parameters in the FSMC_PCCARD_HandleTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Init: Pointer to PCCARD Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - - /* Get PCCARD control register value */ - tmpr = Device->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID)); - - /* Set FSMC_PCCARD device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ - (Init->TCLRSetupTime << 9U) |\ - (Init->TARSetupTime << 13U)); - - Device->PCR4 = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified - * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get PCCARD common space timing register value */ - tmpr = Device->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ - FSMC_PMEM4_MEMHIZ4)); - /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)((Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - (Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PMEM4 = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified - * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get PCCARD timing parameters */ - tmpr = Device->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ - FSMC_PATT4_ATTHIZ4)); - - /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - Device->PATT4 = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified - * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get FSMC_PCCARD device timing parameters */ - tmpr = Device->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ - FSMC_PIO4_IOHIZ4)); - - /* Set FSMC_PCCARD device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PIO4 = tmpr; - - return HAL_OK; -} - -/** - * @brief DeInitializes the FSMC_PCCARD device - * @param Device: Pointer to PCCARD device instance - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) -{ - /* Disable the FSMC_PCCARD device */ - __FSMC_PCCARD_DISABLE(Device); - - /* De-initialize the FSMC_PCCARD device */ - Device->PCR4 = 0x00000018U; - Device->SR4 = 0x00000000U; - Device->PMEM4 = 0xFCFCFCFCU; - Device->PATT4 = 0xFCFCFCFCU; - Device->PIO4 = 0xFCFCFCFCU; - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/embed/trezorhal/hal/stm32f4xx_ll_fsmc.h b/embed/trezorhal/hal/stm32f4xx_ll_fsmc.h deleted file mode 100644 index 72f1678801..0000000000 --- a/embed/trezorhal/hal/stm32f4xx_ll_fsmc.h +++ /dev/null @@ -1,1049 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_fsmc.h - * @author MCD Application Team - * @version V1.5.2 - * @date 22-September-2016 - * @brief Header file of FSMC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_FSMC_H -#define __STM32F4xx_LL_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FSMC_LL - * @{ - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) -/* Private types -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Types FSMC Private Types - * @{ - */ - -/** - * @brief FSMC NORSRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory device. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ - - uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode - This mode is available only for the STM32F405/407/4015/417xx devices */ - - uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock - This mode is available only for the STM32F412Vx/Zx/Rx devices */ - - uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F412Vx/Vx devices */ - - uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FSMC_NORSRAM_InitTypeDef; - -/** - * @brief FSMC NORSRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ - - uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ - - uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ - -}FSMC_NORSRAM_TimingTypeDef; - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief FSMC NAND Configuration Structure definition - */ -typedef struct -{ - uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_NAND_Data_Width */ - - uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - - uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_NAND_InitTypeDef; - -/** - * @brief FSMC NAND/PCCARD Timing parameters structure definition - */ -typedef struct -{ - uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - - uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - - uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - - uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - data bus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_NAND_PCC_TimingTypeDef; - -/** - * @brief FSMC NAND Configuration Structure definition - */ -typedef struct -{ - uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - - uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_PCCARD_InitTypeDef; -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants - * @{ - */ - -/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller - * @{ - */ -/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank - * @{ - */ -#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) -#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) -#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) -#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) -/** - * @} - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing - * @{ - */ -#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) -#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type FSMC Memory Type - * @{ - */ -#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) -#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) -#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width - * @{ - */ -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access - * @{ - */ -#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode - * @{ - */ -#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity - * @{ - */ -#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) -#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode - * @note These values are available only for the STM32F405/415/407/417xx devices. - * @{ - */ -#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing FSMC Wait Timing - * @{ - */ -#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) -#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation FSMC Write Operation - * @{ - */ -#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal FSMC Wait Signal - * @{ - */ -#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode FSMC Extended Mode - * @{ - */ -#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait - * @{ - */ -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) -#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) -/** - * @} - */ - -/** @defgroup FSMC_Page_Size FSMC Page Size - * @{ - */ -#define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) -#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) -#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) -#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) -#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) -/** - * @} - */ - -/** @defgroup FSMC_Write_FIFO FSMC Write FIFO - * @note These values are available only for the STM32F412Vx/Zx/Rx devices. - * @{ - */ -#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) -#define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst FSMC Write Burst - * @{ - */ -#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) -/** - * @} - */ - -/** @defgroup FSMC_Continous_Clock FSMC Continous Clock - * @note These values are available only for the STM32F412Vx/Zx/Rx devices. - * @{ - */ -#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) -#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode FSMC Access Mode - * @{ - */ -#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U) -#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U) -#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U) -#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U) -/** - * @} - */ -/** - * @} - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller - * @{ - */ -/** @defgroup FSMC_NAND_Bank FSMC NAND Bank - * @{ - */ -#define FSMC_NAND_BANK2 ((uint32_t)0x00000010U) -#define FSMC_NAND_BANK3 ((uint32_t)0x00000100U) -/** - * @} - */ - -/** @defgroup FSMC_Wait_feature FSMC Wait feature - * @{ - */ -#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type - * @{ - */ -#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U) -#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width - * @{ - */ -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -/** - * @} - */ - -/** @defgroup FSMC_ECC FSMC ECC - * @{ - */ -#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) -#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size - * @{ - */ -#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) -#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) -#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) -#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) -#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) -#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) -/** - * @} - */ -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition - * @{ - */ -#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U) -#define FSMC_IT_LEVEL ((uint32_t)0x00000010U) -#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) -#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) -/** - * @} - */ - -/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition - * @{ - */ -#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) -#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U) -#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U) -/** - * @} - */ - -/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition - * @{ - */ -#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef -#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_DEVICE FSMC_Bank2_3 -#define FSMC_PCCARD_DEVICE FSMC_Bank4 -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32 - -#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef -#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef -#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef - -#define FMC_NORSRAM_Init FSMC_NORSRAM_Init -#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init -#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init -#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit -#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable -#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable - -#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE -#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef -#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef -#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef - -#define FMC_NAND_Init FSMC_NAND_Init -#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init -#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init -#define FMC_NAND_DeInit FSMC_NAND_DeInit -#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable -#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable -#define FMC_NAND_GetECC FSMC_NAND_GetECC -#define FMC_PCCARD_Init FSMC_PCCARD_Init -#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init -#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init -#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init -#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit - -#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE -#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE -#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE -#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE -#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT -#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT -#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG -#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG -#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT -#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT -#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG -#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FMC_NAND_TypeDef FSMC_NAND_TypeDef -#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE -#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FMC_NAND_DEVICE FSMC_NAND_DEVICE -#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE - -#define FMC_NAND_BANK2 FSMC_NAND_BANK2 -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 -#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 -#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 - -#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE -#define FMC_IT_LEVEL FSMC_IT_LEVEL -#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE -#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR - -#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE -#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL -#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE -#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros - * @{ - */ - -/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ -/** - * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) - -/** - * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) -/** - * @} - */ - -/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief Enable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @retval none - */ -#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) - -/** - * @brief Disable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @retval none - */ -#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) -/** - * @} - */ - -/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros - * @brief macros to handle SRAM read/write operations - * @{ - */ -/** - * @brief Enable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @retval none - */ -#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) - -/** - * @brief Disable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @retval none - */ -#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) -/** - * @} - */ - -/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros - * @brief macros to handle FSMC flags and interrupts - * @{ - */ -/** - * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) - -/** - * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) - -/** - * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__ : FSMC_NAND Bank - * @param __FLAG__ : FSMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) - -/** - * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __FLAG__: FSMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) - -/** - * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) - -/** - * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) - -/** - * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros - * @{ - */ -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ - ((__BANK__) == FSMC_NORSRAM_BANK2) || \ - ((__BANK__) == FSMC_NORSRAM_BANK3) || \ - ((__BANK__) == FSMC_NORSRAM_BANK4)) - -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) - -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ - ((BANK) == FSMC_NAND_BANK3)) - -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ - ((STATE) == FSMC_NAND_ECC_ENABLE)) - -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) - -#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) - -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) - -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) - -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) - -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) - -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) - -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) - -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) - -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) - -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - -#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) - -#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ - ((SIZE) == FSMC_PAGE_SIZE_128) || \ - ((SIZE) == FSMC_PAGE_SIZE_256) || \ - ((SIZE) == FSMC_PAGE_SIZE_1024)) - -#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ - ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) - -/** - * @} - */ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions - * @{ - */ - -/** @defgroup FSMC_LL_NORSRAM NOR SRAM - * @{ - */ - -/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions - * @{ - */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ -/** - * @} - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @defgroup FSMC_LL_NAND NAND - * @{ - */ -/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions - * @{ - */ -HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); -/** - * @} - */ -/** - * @} - */ - -/** @defgroup FSMC_LL_PCCARD PCCARD - * @{ - */ -/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); -/** - * @} - */ -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_FSMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/embed/trezorhal/hal/stm32f4xx_hal_conf.h b/embed/trezorhal/stm32f4xx_hal_conf.h similarity index 100% rename from embed/trezorhal/hal/stm32f4xx_hal_conf.h rename to embed/trezorhal/stm32f4xx_hal_conf.h