diff --git a/setup.c b/setup.c
index 5e986e53f..8329b4236 100644
--- a/setup.c
+++ b/setup.c
@@ -27,22 +27,8 @@
 
 #include "rng.h"
 #include "layout.h"
-#include "memory.h"
 #include "util.h"
 
-#define MPU_RASR_SIZE_32B   (0x04UL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_32KB  (0x0EUL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_64KB  (0x0FUL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_128KB (0x10UL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_256KB (0x11UL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_512KB (0x12UL << MPU_RASR_SIZE_LSB)
-#define MPU_RASR_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_LSB)
-
-// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABDJJGF.html
-#define MPU_RASR_ATTR_FLASH  (MPU_RASR_ATTR_C)
-#define MPU_RASR_ATTR_SRAM   (MPU_RASR_ATTR_S | MPU_RASR_ATTR_C)
-#define MPU_RASR_ATTR_PERIPH (MPU_RASR_ATTR_S | MPU_RASR_ATTR_B)
-
 uint32_t __stack_chk_guard;
 
 static inline void __attribute__((noreturn)) fault_handler(const char *line1) {
@@ -155,42 +141,56 @@ void setupApp(void)
 	gpio_set_af(GPIOA, GPIO_AF10, GPIO10);
 }
 
+#define MPU_RASR_SIZE_32KB  (0x0EUL << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_SIZE_64KB  (0x0FUL << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_SIZE_128KB (0x10UL << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_SIZE_256KB (0x11UL << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_LSB)
+
+// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABDJJGF.html
+#define MPU_RASR_ATTR_FLASH  (MPU_RASR_ATTR_C)
+#define MPU_RASR_ATTR_SRAM   (MPU_RASR_ATTR_C | MPU_RASR_ATTR_S)
+#define MPU_RASR_ATTR_PERIPH (MPU_RASR_ATTR_B | MPU_RASR_ATTR_S)
+
+#define FLASH_BASE	(0x08000000U)
+#define SRAM_BASE	(0x20000000U)
+
 // Never use in bootloader! Disables access to PPB (including MPU, NVIC, SCB)
 void mpu_config(void)
 {
-	// Enable memory fault handler
-	SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA;
-
 	// Disable MPU
 	MPU_CTRL = 0;
 
-	// Bootloader (read-only, execute never)
-	MPU_RBAR = 0x08000000  | MPU_RBAR_VALID | (0 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH  | MPU_RASR_SIZE_32KB  | MPU_RASR_ATTR_AP_PRO_URO | MPU_RASR_ATTR_XN;
+	// Bootloader (0x08000000 - 0x08007FFF, 32 KiB, read-only, execute never)
+	MPU_RBAR = FLASH_BASE | MPU_RBAR_VALID | (0 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32KB | MPU_RASR_ATTR_AP_PRO_URO | MPU_RASR_ATTR_XN;
 
-	// Metadata (read-write, execute never)
-	MPU_RBAR = 0x08008000  | MPU_RBAR_VALID | (1 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH  | MPU_RASR_SIZE_32KB  | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
+	// Metadata (0x08008000 - 0x0800FFFF, 32 KiB, read-write, execute never)
+	MPU_RBAR = FLASH_BASE | 0x8000 | MPU_RBAR_VALID | (1 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32KB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
 
-	// Firmware (read-only)
-	MPU_RBAR = 0x08010000  | MPU_RBAR_VALID | (2 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH  | MPU_RASR_SIZE_64KB  | MPU_RASR_ATTR_AP_PRO_URO;
-	MPU_RBAR = 0x08020000  | MPU_RBAR_VALID | (3 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH  | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRO_URO;
-	MPU_RBAR = 0x08040000  | MPU_RBAR_VALID | (4 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH  | MPU_RASR_SIZE_256KB | MPU_RASR_ATTR_AP_PRO_URO;
+	// Firmware (0x08010000 - 0x0807FFFF, 64 + 3 * 128 KiB = 64 + 128 + 256 KiB = 448 KiB, read-only)
+	MPU_RBAR = FLASH_BASE | 0x10000 | MPU_RBAR_VALID | (2 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_64KB | MPU_RASR_ATTR_AP_PRO_URO;
+	MPU_RBAR = FLASH_BASE | 0x20000 | MPU_RBAR_VALID | (3 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRO_URO;
+	MPU_RBAR = FLASH_BASE | 0x40000 | MPU_RBAR_VALID | (4 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_256KB | MPU_RASR_ATTR_AP_PRO_URO;
 
-	// SRAM (read-write, execute never)
-	MPU_RBAR = 0x20000000  | MPU_RBAR_VALID | (5 << MPU_RBAR_REGION_LSB);
-	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_SRAM   | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
+	// SRAM (0x20000000 - 0x2001FFFF, read-write, execute never)
+	MPU_RBAR = SRAM_BASE | MPU_RBAR_VALID | (5 << MPU_RBAR_REGION_LSB);
+	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_SRAM | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
 
-	// Peripherals (read-write, execute never)
+	// Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
 	MPU_RBAR = PERIPH_BASE | MPU_RBAR_VALID | (6 << MPU_RBAR_REGION_LSB);
 	MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_512MB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
 
 	// Enable MPU
 	MPU_CTRL = MPU_CTRL_ENABLE;
 
+	// Enable memory fault handler
+	SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA;
+
 	__asm__ volatile("dsb");
 	__asm__ volatile("isb");
 }