diff --git a/SConscript.boardloader b/SConscript.boardloader
index ce0a2a9c5f..78c9440655 100644
--- a/SConscript.boardloader
+++ b/SConscript.boardloader
@@ -80,8 +80,7 @@ SOURCE_TREZORHAL = [
'embed/trezorhal/flash.c',
'embed/trezorhal/mini_printf.c',
'embed/trezorhal/sdcard.c',
- 'embed/trezorhal/stm32_it.c',
- 'embed/trezorhal/stm32_system.c',
+ 'embed/trezorhal/stm32.c',
'embed/trezorhal/rng.c',
'embed/trezorhal/util.s',
'embed/trezorhal/vectortable.s',
diff --git a/SConscript.bootloader b/SConscript.bootloader
index 75fb7c967f..90a07e3931 100644
--- a/SConscript.bootloader
+++ b/SConscript.bootloader
@@ -92,8 +92,7 @@ SOURCE_TREZORHAL = [
'embed/trezorhal/image.c',
'embed/trezorhal/flash.c',
'embed/trezorhal/mini_printf.c',
- 'embed/trezorhal/stm32_it.c',
- 'embed/trezorhal/stm32_system.c',
+ 'embed/trezorhal/stm32.c',
'embed/trezorhal/touch.c',
'embed/trezorhal/usb.c',
'embed/trezorhal/usbd_conf.c',
diff --git a/SConscript.firmware b/SConscript.firmware
index 00c9524c6e..6c1232552e 100644
--- a/SConscript.firmware
+++ b/SConscript.firmware
@@ -280,8 +280,7 @@ SOURCE_TREZORHAL = [
'embed/trezorhal/rng.c',
'embed/trezorhal/sbu.c',
'embed/trezorhal/sdcard.c',
- 'embed/trezorhal/stm32_it.c',
- 'embed/trezorhal/stm32_system.c',
+ 'embed/trezorhal/stm32.c',
'embed/trezorhal/touch.c',
'embed/trezorhal/usb.c',
'embed/trezorhal/usbd_conf.c',
diff --git a/embed/trezorhal/common.c b/embed/trezorhal/common.c
index d111d70cb6..32baa46155 100644
--- a/embed/trezorhal/common.c
+++ b/embed/trezorhal/common.c
@@ -27,7 +27,7 @@ void __assert_func(const char *file, int line, const char *func, const char *exp
#endif
void __attribute__((noreturn)) nlr_jump_fail(void *val) {
- __fatal_error("uncaught exception", __FILE__, __LINE__, __FUNCTION__);
+ __fatal_error("uncaught exception", NULL, 0, NULL);
}
void periph_init(void) {
diff --git a/embed/trezorhal/stm32.c b/embed/trezorhal/stm32.c
new file mode 100644
index 0000000000..3eedd5bb28
--- /dev/null
+++ b/embed/trezorhal/stm32.c
@@ -0,0 +1,72 @@
+#include STM32_HAL_H
+
+#include "pendsv.h"
+#include "rng.h"
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+uint32_t SystemCoreClock = 168000000;
+
+void SystemInit(void)
+{
+ // set flash wait states for an increasing HCLK frequency -- reference RM0090 section 3.5.1
+ FLASH->ACR = FLASH_ACR_LATENCY_5WS;
+ // configure main PLL; assumes HSE is 8 MHz; this should evaluate to 0x27402a04 -- reference RM0090 section 7.3.2
+ RCC->PLLCFGR = (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC & ~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM)
+ | (7 << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
+ | RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
+ | (0 << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
+ | (168 << RCC_PLLCFGR_PLLN_Pos) // N = 168
+ | (4 << RCC_PLLCFGR_PLLM_Pos); // M = 4
+ // enable clock security system, HSE clock, and main PLL
+ RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_PLLON;
+ // wait until PLL and HSE ready
+ while((RCC->CR & (RCC_CR_PLLRDY | RCC_CR_HSERDY)) != (RCC_CR_PLLRDY | RCC_CR_HSERDY));
+ // APB2=2, APB1=4, AHB=1, system clock = main PLL
+ RCC->CFGR = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
+ // wait until PLL is system clock
+ while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
+ // turn off the HSI as it is now unused (it will be turned on again automatically if a clock security failure occurs)
+ RCC->CR &= ~RCC_CR_HSION;
+ // init the TRNG peripheral
+ rng_init();
+ // enable full access to the fpu coprocessor
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+}
+
+void PendSV_Handler(void) {
+ pendsv_isr_handler();
+}
+
+void SysTick_Handler(void) {
+ // Instead of calling HAL_IncTick we do the increment here of the counter.
+ // This is purely for efficiency, since SysTick is called 1000 times per
+ // second at the highest interrupt priority.
+ // Note: we don't need uwTick to be declared volatile here because this is
+ // the only place where it can be modified, and the code is more efficient
+ // without the volatile specifier.
+ extern uint32_t uwTick;
+ uwTick += 1;
+
+ // Read the systick control regster. This has the side effect of clearing
+ // the COUNTFLAG bit, which makes the logic in sys_tick_get_microseconds
+ // work properly.
+ SysTick->CTRL;
+
+ // Right now we have the storage and DMA controllers to process during
+ // this interrupt and we use custom dispatch handlers. If this needs to
+ // be generalised in the future then a dispatch table can be used as
+ // follows: ((void(*)(void))(systick_dispatch[uwTick & 0xf]))();
+
+ // if (STORAGE_IDLE_TICK(uwTick)) {
+ // NVIC->STIR = FLASH_IRQn;
+ // }
+
+ // if (DMA_IDLE_ENABLED() && DMA_IDLE_TICK(uwTick)) {
+ // dma_idle_handler(uwTick);
+ // }
+}
+
diff --git a/embed/trezorhal/stm32_it.c b/embed/trezorhal/stm32_it.c
deleted file mode 100644
index 08dd0435a0..0000000000
--- a/embed/trezorhal/stm32_it.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the Micro Python project, http://micropython.org/
- *
- * Original template from ST Cube library. See below for header.
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2013, 2014 Damien P. George
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/**
- ******************************************************************************
- * @file Templates/Src/stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 26-February-2014
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2014 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-#include STM32_HAL_H
-
-#include "pendsv.h"
-#include "gccollect.h"
-
-#include "display.h"
-#include "common.h"
-
-#define IRQ_ENTER(irq)
-#define IRQ_EXIT(irq)
-
-/******************************************************************************/
-/* Cortex-M4 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void) {
- pendsv_isr_handler();
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void) {
- // Instead of calling HAL_IncTick we do the increment here of the counter.
- // This is purely for efficiency, since SysTick is called 1000 times per
- // second at the highest interrupt priority.
- // Note: we don't need uwTick to be declared volatile here because this is
- // the only place where it can be modified, and the code is more efficient
- // without the volatile specifier.
- extern uint32_t uwTick;
- uwTick += 1;
-
- // Read the systick control regster. This has the side effect of clearing
- // the COUNTFLAG bit, which makes the logic in sys_tick_get_microseconds
- // work properly.
- SysTick->CTRL;
-
- // Right now we have the storage and DMA controllers to process during
- // this interrupt and we use custom dispatch handlers. If this needs to
- // be generalised in the future then a dispatch table can be used as
- // follows: ((void(*)(void))(systick_dispatch[uwTick & 0xf]))();
-
- // if (STORAGE_IDLE_TICK(uwTick)) {
- // NVIC->STIR = FLASH_IRQn;
- // }
-
- // if (DMA_IDLE_ENABLED() && DMA_IDLE_TICK(uwTick)) {
- // dma_idle_handler(uwTick);
- // }
-}
diff --git a/embed/trezorhal/stm32_system.c b/embed/trezorhal/stm32_system.c
deleted file mode 100644
index ac2a38c684..0000000000
--- a/embed/trezorhal/stm32_system.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- * This file is part of the Micro Python project, http://micropython.org/
- *
- * Taken from ST Cube library and modified. See below for original header.
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2013, 2014 Damien P. George
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/**
- ******************************************************************************
- * @file system_stm32.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 26-February-2014
- * @brief CMSIS Cortex-M4/M7 Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32fxxx_system
- * @{
- */
-
-/** @addtogroup STM32Fxxx_System_Private_Includes
- * @{
- */
-
-#include STM32_HAL_H
-
-#define MICROPY_HW_CLK_PLLM (4)
-#define MICROPY_HW_CLK_PLLN (168)
-#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
-#define MICROPY_HW_CLK_PLLQ (7)
-#define MICROPY_HW_CLK_LAST_FREQ (1)
-
-#include "common.h"
-#include "rng.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_Defines
- * @{
- */
-
-#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
-
-#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
-#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_PLLON)
-#define CONFIG_RCC_PLLCFGR (0x24003010)
-
-#if defined(MCU_SERIES_F4)
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-#elif defined(MCU_SERIES_F7)
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-#endif
-
-#elif defined(MCU_SERIES_L4)
-
-#define CONFIG_RCC_CR_1ST (RCC_CR_MSION)
-#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_HSION || RCC_CR_PLLON)
-#define CONFIG_RCC_PLLCFGR (0x00001000)
-/*
- * FIXME Do not know why I have to define these arrays here! they should be defined in the
- * hal_rcc-file!!
- *
- */
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
- 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-#else
-#error Unknown processor
-#endif
-
-/************************* Miscellaneous Configuration ************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
- uint32_t SystemCoreClock = 168000000;
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32Fxxx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and External memory
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- // set flash wait states for an increasing HCLK frequency -- reference RM0090 section 3.5.1
- FLASH->ACR = FLASH_ACR_LATENCY_5WS;
- // configure main PLL; assumes HSE is 8 MHz; this should evaluate to 0x27402a04 -- reference RM0090 section 7.3.2
- RCC->PLLCFGR = (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC & ~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM)
- | (7 << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
- | RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
- | (0 << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
- | (168 << RCC_PLLCFGR_PLLN_Pos) // N = 168
- | (4 << RCC_PLLCFGR_PLLM_Pos); // M = 4
- // enable clock security system, HSE clock, and main PLL
- RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_PLLON;
- // wait until PLL and HSE ready
- while((RCC->CR & (RCC_CR_PLLRDY | RCC_CR_HSERDY)) != (RCC_CR_PLLRDY | RCC_CR_HSERDY));
- // APB2=2, APB1=4, AHB=1, system clock = main PLL
- RCC->CFGR = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
- // wait until PLL is system clock
- while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
- // turn off the HSI as it is now unused (it will be turned on again automatically if a clock security failure occurs)
- RCC->CR &= ~RCC_CR_HSION;
- // init the TRNG peripheral
- rng_init();
- // enable full access to the fpu coprocessor
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
-}
-
-
-/**
- * @brief System Clock Configuration
- *
- * The system Clock is configured for F4/F7 as follows:
- * System Clock source = PLL (HSE)
- * SYSCLK(Hz) = 168000000
- * HCLK(Hz) = 168000000
- * AHB Prescaler = 1
- * APB1 Prescaler = 4
- * APB2 Prescaler = 2
- * HSE Frequency(Hz) = HSE_VALUE
- * PLL_M = HSE_VALUE/1000000
- * PLL_N = 336
- * PLL_P = 2
- * PLL_Q = 7
- * VDD(V) = 3.3
- * Main regulator output voltage = Scale1 mode
- * Flash Latency(WS) = 5
- *
- * The system Clock is configured for L4 as follows:
- * System Clock source = PLL (MSI)
- * SYSCLK(Hz) = 80000000
- * HCLK(Hz) = 80000000
- * AHB Prescaler = 1
- * APB1 Prescaler = 1
- * APB2 Prescaler = 1
- * MSI Frequency(Hz) = MSI_VALUE (4000000)
- * LSE Frequency(Hz) = 32768
- * PLL_M = 1
- * PLL_N = 40
- * PLL_P = 7
- * PLL_Q = 2
- * PLL_R = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
- * Flash Latency(WS) = 4
- * @param None
- * @retval None
- *
- * PLL is configured as follows:
- *
- * VCO_IN
- * F4/F7 = HSE / M
- * L4 = MSI / M
- * VCO_OUT
- * F4/F7 = HSE / M * N
- * L4 = MSI / M * N
- * PLLCLK
- * F4/F7 = HSE / M * N / P
- * L4 = MSI / M * N / R
- * PLL48CK
- * F4/F7 = HSE / M * N / Q
- * L4 = MSI / M * N / Q USB Clock is obtained over PLLSAI1
- *
- * SYSCLK = PLLCLK
- * HCLK = SYSCLK / AHB_PRESC
- * PCLKx = HCLK / APBx_PRESC
- *
- * Constraints on parameters:
- *
- * VCO_IN between 1MHz and 2MHz (2MHz recommended)
- * VCO_OUT between 192MHz and 432MHz
- * HSE = 8MHz
- * M = 2 .. 63 (inclusive)
- * N = 192 ... 432 (inclusive)
- * P = 2, 4, 6, 8
- * Q = 2 .. 15 (inclusive)
- *
- * AHB_PRESC=1,2,4,8,16,64,128,256,512
- * APBx_PRESC=1,2,4,8,16
- *
- * Output clocks:
- *
- * CPU SYSCLK max 168MHz
- * USB,RNG,SDIO PLL48CK must be 48MHz for USB
- * AHB HCLK max 168MHz
- * APB1 PCLK1 max 42MHz
- * APB2 PCLK2 max 84MHz
- *
- * Timers run from APBx if APBx_PRESC=1, else 2x APBx
- */
-void SystemClock_Config(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
- /* Enable Power Control clock */
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
- regarding system frequency refer to product datasheet. */
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- #elif defined(MCU_SERIES_L4)
- /* Enable the LSE Oscillator */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- __fatal_error("HAL_RCC_OscConfig", __FILE__, __LINE__, __FUNCTION__);
- }
- #endif
-
- /* Enable HSE Oscillator and activate PLL with HSE as source */
- #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- #elif defined(MCU_SERIES_L4)
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
- RCC_OscInitStruct.MSIState = RCC_MSI_ON;
- RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
- #endif
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
- clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-
-#if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
- #if defined(MCU_SERIES_F7)
- #define FREQ_BKP BKP31R
- #elif defined(MCU_SERIES_L4)
- #error Unsupported Processor
- #else
- #define FREQ_BKP BKP19R
- #endif
- uint32_t m = RTC->FREQ_BKP;
- uint32_t n;
- uint32_t p;
- uint32_t q;
-
- // 222111HH HHQQQQPP nNNNNNNN NNMMMMMM
- uint32_t h = (m >> 22) & 0xf;
- uint32_t b1 = (m >> 26) & 0x7;
- uint32_t b2 = (m >> 29) & 0x7;
- q = (m >> 18) & 0xf;
- p = (((m >> 16) & 0x03)+1)*2;
- n = (m >> 6) & 0x3ff;
- m &= 0x3f;
- if ((q < 2) || (q > 15) || (p > 8) || (p < 2) || (n < 192) || (n >= 433) || (m < 2)) {
- m = MICROPY_HW_CLK_PLLM;
- n = MICROPY_HW_CLK_PLLN;
- p = MICROPY_HW_CLK_PLLP;
- q = MICROPY_HW_CLK_PLLQ;
- h = RCC_SYSCLK_DIV1;
- b1 = RCC_HCLK_DIV4;
- b2 = RCC_HCLK_DIV2;
- } else {
- h <<= 4;
- b1 <<= 10;
- b2 <<= 10;
- }
- RCC_OscInitStruct.PLL.PLLM = m; //MICROPY_HW_CLK_PLLM;
- RCC_OscInitStruct.PLL.PLLN = n; //MICROPY_HW_CLK_PLLN;
- RCC_OscInitStruct.PLL.PLLP = p; //MICROPY_HW_CLK_PLLP;
- RCC_OscInitStruct.PLL.PLLQ = q; //MICROPY_HW_CLK_PLLQ;
-
- RCC_ClkInitStruct.AHBCLKDivider = h; //RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = b1; //RCC_HCLK_DIV4;
- RCC_ClkInitStruct.APB2CLKDivider = b2; //RCC_HCLK_DIV2;
-#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
- RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
- RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
- RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
- RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
- #if defined(MCU_SERIES_L4)
- RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
- #endif
-
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
- #elif defined(MCU_SERIES_L4)
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- #endif
-#endif
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- __fatal_error("HAL_RCC_OscConfig", __FILE__, __LINE__, __FUNCTION__);
- }
-
-#if defined(MCU_SERIES_F7)
- /* Activate the OverDrive to reach the 200 MHz Frequency */
- if (HAL_PWREx_EnableOverDrive() != HAL_OK)
- {
- __fatal_error("HAL_PWREx_EnableOverDrive", __FILE__, __LINE__, __FUNCTION__);
- }
-#endif
-
-#if !defined(MICROPY_HW_FLASH_LATENCY)
-#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5
-#endif
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, MICROPY_HW_FLASH_LATENCY) != HAL_OK)
- {
- __fatal_error("HAL_RCC_ClockConfig", __FILE__, __LINE__, __FUNCTION__);
- }
-
-#if defined(MCU_SERIES_F7)
- // The DFU bootloader changes the clocksource register from its default power
- // on reset value, so we set it back here, so the clocksources are the same
- // whether we were started from DFU or from a power on reset.
-
- RCC->DCKCFGR2 = 0;
-#endif
-#if defined(MCU_SERIES_L4)
- // Enable MSI-Hardware auto calibration mode with LSE
- HAL_RCCEx_EnableMSIPLLMode();
-
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_I2C1
- |RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC
- |RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_RTC;
- PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
- /* PLLSAI is used to clock USB, ADC, I2C1 and RNG. The frequency is
- HSE(8MHz)/PLLM(2)*PLLSAI1N(24)/PLLSAIQ(2) = 48MHz. See the STM32CubeMx
- application or the reference manual. */
- PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
- PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
- PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
- PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
- PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
- PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
- PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
- PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
- PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
- |RCC_PLLSAI1_48M2CLK
- |RCC_PLLSAI1_ADC1CLK;
-
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- {
- __fatal_error("HAL_RCCEx_PeriphCLKConfig");
- }
-
- __HAL_RCC_PWR_CLK_ENABLE();
-
- HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
-
- HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
-
- HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-#endif
-}
-
-void HAL_MspInit(void) {
-#if defined(MCU_SERIES_F7)
- /* Enable I-Cache */
- SCB_EnableICache();
-
- /* Enable D-Cache */
- SCB_EnableDCache();
-#endif
-}