From 5fd1f0e4c640528d7d256a9423598e289fd4d36b Mon Sep 17 00:00:00 2001 From: cepetr Date: Fri, 4 Oct 2024 13:28:09 +0200 Subject: [PATCH] refactor(core): decompose lowlevel module [no changelog] --- core/embed/boardloader/main.c | 10 +-- core/embed/bootloader/main.c | 7 +- core/embed/kernel/main.c | 5 ++ .../models/D001/boards/stm32f429i-disc1.h | 1 + core/embed/models/T2B1/boards/trezor_r_v10.h | 1 + core/embed/models/T2B1/boards/trezor_r_v3.h | 1 + core/embed/models/T2B1/boards/trezor_r_v4.h | 1 + core/embed/models/T2B1/boards/trezor_r_v6.h | 1 + core/embed/models/T2T1/boards/trezor_t.h | 1 + .../models/T3B1/boards/trezor_t3b1_revB.h | 1 + .../models/T3T1/boards/trezor_t3t1_revE.h | 1 + .../embed/models/T3T1/boards/trezor_t3t1_v4.h | 1 + .../trezorhal/{lowlevel.h => option_bytes.h} | 9 +-- core/embed/trezorhal/pvd.h | 33 ++++++++++ core/embed/trezorhal/reset_flags.h | 35 ++++++++++ .../stm32f4/{lowlevel.c => option_bytes.c} | 52 +-------------- core/embed/trezorhal/stm32f4/pvd.c | 64 +++++++++++++++++++ core/embed/trezorhal/stm32f4/reset_flags.c | 44 +++++++++++++ core/embed/trezorhal/stm32f4/startup_init.c | 18 ++++++ core/embed/trezorhal/stm32f4/systask.c | 12 ---- .../stm32u5/{lowlevel.c => option_bytes.c} | 50 +-------------- core/embed/trezorhal/stm32u5/pvd.c | 1 + core/embed/trezorhal/stm32u5/reset_flags.c | 45 +++++++++++++ core/embed/trezorhal/stm32u5/startup_init.c | 18 ++++++ core/site_scons/models/stm32f4_common.py | 4 +- core/site_scons/models/stm32u5_common.py | 4 +- 26 files changed, 296 insertions(+), 124 deletions(-) rename core/embed/trezorhal/{lowlevel.h => option_bytes.h} (84%) create mode 100644 core/embed/trezorhal/pvd.h create mode 100644 core/embed/trezorhal/reset_flags.h rename core/embed/trezorhal/stm32f4/{lowlevel.c => option_bytes.c} (77%) create mode 100644 core/embed/trezorhal/stm32f4/pvd.c create mode 100644 core/embed/trezorhal/stm32f4/reset_flags.c rename core/embed/trezorhal/stm32u5/{lowlevel.c => option_bytes.c} (83%) create mode 120000 core/embed/trezorhal/stm32u5/pvd.c create mode 100644 core/embed/trezorhal/stm32u5/reset_flags.c diff --git a/core/embed/boardloader/main.c b/core/embed/boardloader/main.c index 18054329b0..6e021bd20f 100644 --- a/core/embed/boardloader/main.c +++ b/core/embed/boardloader/main.c @@ -33,6 +33,8 @@ #include "model.h" #include "mpu.h" #include "platform.h" +#include "pvd.h" +#include "reset_flags.h" #include "rng.h" #include "rsod.h" #include "secret.h" @@ -57,9 +59,9 @@ #endif #endif -#include "lowlevel.h" #include "model.h" #include "monoctr.h" +#include "option_bytes.h" #include "version.h" #include "memzero.h" @@ -240,9 +242,9 @@ int main(void) { reset_flags_reset(); - // need the systick timer running before many HAL operations. - // want the PVD enabled before flash operations too. - periph_init(); +#ifdef USE_PVD + pvd_init(); +#endif if (sectrue != flash_configure_option_bytes()) { // display is not initialized so don't call ensure diff --git a/core/embed/bootloader/main.c b/core/embed/bootloader/main.c index e19b29deb1..669c5eb281 100644 --- a/core/embed/bootloader/main.c +++ b/core/embed/bootloader/main.c @@ -29,8 +29,9 @@ #include "flash_otp.h" #include "flash_utils.h" #include "image.h" -#include "lowlevel.h" #include "messages.pb.h" +#include "option_bytes.h" +#include "pvd.h" #include "random_delays.h" #include "rsod.h" #include "secbool.h" @@ -364,6 +365,10 @@ int bootloader_main(void) { random_delays_init(); +#ifdef USE_PVD + pvd_init(); +#endif + #ifdef USE_HASH_PROCESSOR hash_processor_init(); #endif diff --git a/core/embed/kernel/main.c b/core/embed/kernel/main.c index 5f4b54f7ab..a8ca9fe593 100644 --- a/core/embed/kernel/main.c +++ b/core/embed/kernel/main.c @@ -38,6 +38,7 @@ #include "optiga_commands.h" #include "optiga_transport.h" #include "platform.h" +#include "pvd.h" #include "random_delays.h" #include "rsod.h" #include "sdcard.h" @@ -76,6 +77,10 @@ void drivers_init() { random_delays_init(); +#ifdef USE_PVD + pvd_init(); +#endif + #ifdef RDI random_delays_start_rdi(); #endif diff --git a/core/embed/models/D001/boards/stm32f429i-disc1.h b/core/embed/models/D001/boards/stm32f429i-disc1.h index 28198342d2..30620b3697 100644 --- a/core/embed/models/D001/boards/stm32f429i-disc1.h +++ b/core/embed/models/D001/boards/stm32f429i-disc1.h @@ -12,6 +12,7 @@ #define USE_TOUCH 1 #define USE_SDRAM 1 #define USE_RGB_COLORS 1 +#define USE_PVD 1 #define I2C_COUNT 1 #define I2C_INSTANCE_0 I2C3 diff --git a/core/embed/models/T2B1/boards/trezor_r_v10.h b/core/embed/models/T2B1/boards/trezor_r_v10.h index 24cda1e8cc..9dae64582d 100644 --- a/core/embed/models/T2B1/boards/trezor_r_v10.h +++ b/core/embed/models/T2B1/boards/trezor_r_v10.h @@ -7,6 +7,7 @@ #define USE_SBU 1 #define USE_I2C 1 #define USE_CONSUMPTION_MASK 1 +#define USE_PVD 1 #define DISPLAY_RESX 128 #define DISPLAY_RESY 64 diff --git a/core/embed/models/T2B1/boards/trezor_r_v3.h b/core/embed/models/T2B1/boards/trezor_r_v3.h index ffe8b69148..d8cfb1ee5a 100644 --- a/core/embed/models/T2B1/boards/trezor_r_v3.h +++ b/core/embed/models/T2B1/boards/trezor_r_v3.h @@ -5,6 +5,7 @@ #define USE_BUTTON 1 #define USE_SBU 1 +#define USE_PVD 1 #define DISPLAY_RESX 128 #define DISPLAY_RESY 128 diff --git a/core/embed/models/T2B1/boards/trezor_r_v4.h b/core/embed/models/T2B1/boards/trezor_r_v4.h index 9dbbb62671..ac7ba7ca95 100644 --- a/core/embed/models/T2B1/boards/trezor_r_v4.h +++ b/core/embed/models/T2B1/boards/trezor_r_v4.h @@ -5,6 +5,7 @@ #define USE_BUTTON 1 #define USE_SBU 1 +#define USE_PVD 1 #define DISPLAY_RESX 128 #define DISPLAY_RESY 64 diff --git a/core/embed/models/T2B1/boards/trezor_r_v6.h b/core/embed/models/T2B1/boards/trezor_r_v6.h index d177c3d726..561df4d297 100644 --- a/core/embed/models/T2B1/boards/trezor_r_v6.h +++ b/core/embed/models/T2B1/boards/trezor_r_v6.h @@ -5,6 +5,7 @@ #define USE_BUTTON 1 #define USE_SBU 1 +#define USE_PVD 1 #define DISPLAY_RESX 128 #define DISPLAY_RESY 64 diff --git a/core/embed/models/T2T1/boards/trezor_t.h b/core/embed/models/T2T1/boards/trezor_t.h index 60d569648b..42f5a91370 100644 --- a/core/embed/models/T2T1/boards/trezor_t.h +++ b/core/embed/models/T2T1/boards/trezor_t.h @@ -10,6 +10,7 @@ #define USE_RGB_COLORS 1 #define USE_BACKLIGHT 1 #define USE_DISP_I8080_8BIT_DW 1 +#define USE_PVD 1 #define DISPLAY_RESX 240 #define DISPLAY_RESY 240 diff --git a/core/embed/models/T3B1/boards/trezor_t3b1_revB.h b/core/embed/models/T3B1/boards/trezor_t3b1_revB.h index 7c57e7623d..6949dcb005 100644 --- a/core/embed/models/T3B1/boards/trezor_t3b1_revB.h +++ b/core/embed/models/T3B1/boards/trezor_t3b1_revB.h @@ -11,6 +11,7 @@ #define USE_SBU 1 #define USE_HASH_PROCESSOR 1 #define USE_CONSUMPTION_MASK 1 +#define USE_PVD 1 #define DISPLAY_LEGACY_HEADER "displays/vg-2864ksweg01.h" diff --git a/core/embed/models/T3T1/boards/trezor_t3t1_revE.h b/core/embed/models/T3T1/boards/trezor_t3t1_revE.h index 65984732ae..6bd33e03f1 100644 --- a/core/embed/models/T3T1/boards/trezor_t3t1_revE.h +++ b/core/embed/models/T3T1/boards/trezor_t3t1_revE.h @@ -12,6 +12,7 @@ #define USE_HAPTIC 1 #define USE_BACKLIGHT 1 #define USE_HASH_PROCESSOR 1 +#define USE_PVD 1 #define DISPLAY_RESX 240 #define DISPLAY_RESY 240 diff --git a/core/embed/models/T3T1/boards/trezor_t3t1_v4.h b/core/embed/models/T3T1/boards/trezor_t3t1_v4.h index bf97f8e046..b3a570d850 100644 --- a/core/embed/models/T3T1/boards/trezor_t3t1_v4.h +++ b/core/embed/models/T3T1/boards/trezor_t3t1_v4.h @@ -13,6 +13,7 @@ #define USE_HAPTIC 1 #define USE_BACKLIGHT 1 #define USE_HASH_PROCESSOR 1 +#define USE_PVD 1 #define DISPLAY_RESX 240 #define DISPLAY_RESY 240 diff --git a/core/embed/trezorhal/lowlevel.h b/core/embed/trezorhal/option_bytes.h similarity index 84% rename from core/embed/trezorhal/lowlevel.h rename to core/embed/trezorhal/option_bytes.h index 7d6cf78916..449f2c3b46 100644 --- a/core/embed/trezorhal/lowlevel.h +++ b/core/embed/trezorhal/option_bytes.h @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#ifndef __TREZORHAL_LOWLEVEL_H__ -#define __TREZORHAL_LOWLEVEL_H__ +#ifndef TREZORHAL_OPTION_BYTES_H +#define TREZORHAL_OPTION_BYTES_H #include "secbool.h" @@ -29,10 +29,7 @@ void flash_lock_option_bytes(void); void flash_unlock_option_bytes(void); uint32_t flash_set_option_bytes(void); secbool flash_configure_option_bytes(void); -void periph_init(void); -secbool reset_flags_check(void); -void reset_flags_reset(void); #endif // KERNEL_MODE -#endif // __TREZORHAL_LOWLEVEL_H__ +#endif // TREZORHAL_OPTION_BYTES_H diff --git a/core/embed/trezorhal/pvd.h b/core/embed/trezorhal/pvd.h new file mode 100644 index 0000000000..74e288702d --- /dev/null +++ b/core/embed/trezorhal/pvd.h @@ -0,0 +1,33 @@ +/* + * This file is part of the Trezor project, https://trezor.io/ + * + * Copyright (c) SatoshiLabs + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TREZORHAL_PVD_H +#define TREZORHAL_PVD_H + +#ifdef KERNEL_MODE + +// Initialize the Programmable Voltage Detector (PVD) peripheral. +// +// The PVD is used to detect a voltage drop below a certain threshold +// and trigger an interrupt. This is used to safely shutdown the device. +void pvd_init(void); + +#endif // KERNEL_MODE + +#endif // TREZORHAL_PVD_H diff --git a/core/embed/trezorhal/reset_flags.h b/core/embed/trezorhal/reset_flags.h new file mode 100644 index 0000000000..52ae40d557 --- /dev/null +++ b/core/embed/trezorhal/reset_flags.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Trezor project, https://trezor.io/ + * + * Copyright (c) SatoshiLabs + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TREZORHAL_RESET_FLAGS_H +#define TREZORHAL_RESET_FLAGS_H + +#include "secbool.h" + +#ifdef KERNEL_MODE + +// Checks if the CPU reset flags indicate an expected type of reset. +secbool reset_flags_check(void); + +// Clear the CPU register that holds the reset flags. +void reset_flags_reset(void); + +#endif // KERNEL_MODE + +#endif // TREZORHAL_RESET_FLAGS_H diff --git a/core/embed/trezorhal/stm32f4/lowlevel.c b/core/embed/trezorhal/stm32f4/option_bytes.c similarity index 77% rename from core/embed/trezorhal/stm32f4/lowlevel.c rename to core/embed/trezorhal/stm32f4/option_bytes.c index 1174991f19..be42e799ad 100644 --- a/core/embed/trezorhal/stm32f4/lowlevel.c +++ b/core/embed/trezorhal/stm32f4/option_bytes.c @@ -19,11 +19,9 @@ #include STM32_HAL_H -#include "lowlevel.h" - -#include - +#include "option_bytes.h" #include "flash_otp.h" +#include "mpu.h" #ifdef KERNEL_MODE @@ -154,50 +152,4 @@ secbool flash_configure_option_bytes(void) { return secfalse; // notify that we DID have to change the option bytes } -void periph_init(void) { - // STM32F4xx HAL library initialization: - // - configure the Flash prefetch, instruction and data caches - // - configure the Systick to generate an interrupt each 1 msec - // - set NVIC Group Priority to 4 - // - global MSP (MCU Support Package) initialization - HAL_Init(); - - // Enable GPIO clocks - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - // enable the PVD (programmable voltage detector). - // select the "2.7V" threshold (level 5). - // this detector will be active regardless of the - // flash option byte BOR setting. - __HAL_RCC_PWR_CLK_ENABLE(); - PWR_PVDTypeDef pvd_config = {0}; - pvd_config.PVDLevel = PWR_PVDLEVEL_5; - pvd_config.Mode = PWR_PVD_MODE_IT_RISING_FALLING; - HAL_PWR_ConfigPVD(&pvd_config); - HAL_PWR_EnablePVD(); - NVIC_EnableIRQ(PVD_IRQn); -} - -secbool reset_flags_check(void) { -#if PRODUCTION - // this is effective enough that it makes development painful, so only use it - // for production. check the reset flags to assure that we arrive here due to - // a regular full power-on event, and not as a result of a lesser reset. - if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | - RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | - RCC_CSR_BORRSTF)) != - (RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { - return secfalse; - } -#endif - return sectrue; -} - -void reset_flags_reset(void) { - RCC->CSR |= RCC_CSR_RMVF; // clear the reset flags -} - #endif // #ifdef KERNEL_MODE diff --git a/core/embed/trezorhal/stm32f4/pvd.c b/core/embed/trezorhal/stm32f4/pvd.c new file mode 100644 index 0000000000..0f74ff9536 --- /dev/null +++ b/core/embed/trezorhal/stm32f4/pvd.c @@ -0,0 +1,64 @@ +/* + * This file is part of the Trezor project, https://trezor.io/ + * + * Copyright (c) SatoshiLabs + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include TREZOR_BOARD +#include STM32_HAL_H + +#include "bootutils.h" +#include "irq.h" +#include "mpu.h" + +#if defined(KERNEL_MODE) && defined(USE_PVD) + +void pvd_init(void) { + // enable the PVD (programmable voltage detector). + // select the "2.8V" threshold (level 5). + // this detector will be active regardless of the + // flash option byte BOR setting. + __HAL_RCC_PWR_CLK_ENABLE(); + PWR_PVDTypeDef pvd_config = {0}; + pvd_config.PVDLevel = PWR_PVDLEVEL_5; + pvd_config.Mode = PWR_PVD_MODE_IT_RISING_FALLING; + HAL_PWR_ConfigPVD(&pvd_config); + HAL_PWR_EnablePVD(); +#ifdef STM32U5 + NVIC_SetPriority(PVD_PVM_IRQn, IRQ_PRI_HIGHEST); + NVIC_EnableIRQ(PVD_PVM_IRQn); +#else + NVIC_SetPriority(PVD_IRQn, IRQ_PRI_HIGHEST); + NVIC_EnableIRQ(PVD_IRQn); +#endif +} + +#ifdef STM32U5 +void PVD_PVM_IRQHandler(void) { +#else +void PVD_IRQHandler(void) { +#endif + mpu_reconfig(MPU_MODE_DEFAULT); +#ifdef BACKLIGHT_PWM_TIM + // Turn off display backlight + BACKLIGHT_PWM_TIM->BACKLIGHT_PWM_TIM_CCR = 0; +#endif + // from util.s + extern void shutdown_privileged(void); + shutdown_privileged(); +} + +#endif // defined(KERNEL_MODE) && defined(USE_PVD) diff --git a/core/embed/trezorhal/stm32f4/reset_flags.c b/core/embed/trezorhal/stm32f4/reset_flags.c new file mode 100644 index 0000000000..675dc2dc54 --- /dev/null +++ b/core/embed/trezorhal/stm32f4/reset_flags.c @@ -0,0 +1,44 @@ +/* + * This file is part of the Trezor project, https://trezor.io/ + * + * Copyright (c) SatoshiLabs + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include STM32_HAL_H + +#include "reset_flags.h" + +#ifdef KERNEL_MODE + +secbool reset_flags_check(void) { +#if PRODUCTION + // this is effective enough that it makes development painful, so only use it + // for production. check the reset flags to assure that we arrive here due to + // a regular full power-on event, and not as a result of a lesser reset. + if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | + RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF | + RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { + return secfalse; + } +#endif + return sectrue; +} + +void reset_flags_reset(void) { + RCC->CSR |= RCC_CSR_RMVF; // clear the reset flags +} + +#endif diff --git a/core/embed/trezorhal/stm32f4/startup_init.c b/core/embed/trezorhal/stm32f4/startup_init.c index a2f5d8bb73..823cbbdb4f 100644 --- a/core/embed/trezorhal/stm32f4/startup_init.c +++ b/core/embed/trezorhal/stm32f4/startup_init.c @@ -159,6 +159,24 @@ void SystemInit(void) { // set CP10 and CP11 to enable full access to the fpu coprocessor; ARMv7-M // Architecture Reference Manual section B3.2.20 SCB->CPACR |= ((3U << 22) | (3U << 20)); + + // Configure Flash prefetch, Instruction cache, Data cache +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); +#endif + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif + + // Set Interrupt Group Priority + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + // Enable GPIO clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); } #ifdef TREZOR_MODEL_T diff --git a/core/embed/trezorhal/stm32f4/systask.c b/core/embed/trezorhal/stm32f4/systask.c index ec73670c1d..d128fee454 100644 --- a/core/embed/trezorhal/stm32f4/systask.c +++ b/core/embed/trezorhal/stm32f4/systask.c @@ -634,16 +634,4 @@ void NMI_Handler(void) { mpu_restore(mpu_mode); } -// from util.s -extern void shutdown_privileged(void); - -void PVD_PVM_IRQHandler(void) { - mpu_reconfig(MPU_MODE_DEFAULT); -#ifdef BACKLIGHT_PWM_TIM - // Turn off display backlight - BACKLIGHT_PWM_TIM->BACKLIGHT_PWM_TIM_CCR = 0; -#endif - shutdown_privileged(); -} - #endif // KERNEL_MODE diff --git a/core/embed/trezorhal/stm32u5/lowlevel.c b/core/embed/trezorhal/stm32u5/option_bytes.c similarity index 83% rename from core/embed/trezorhal/stm32u5/lowlevel.c rename to core/embed/trezorhal/stm32u5/option_bytes.c index 7270180782..d3a95eb50a 100644 --- a/core/embed/trezorhal/stm32u5/lowlevel.c +++ b/core/embed/trezorhal/stm32u5/option_bytes.c @@ -21,7 +21,7 @@ #ifdef KERNEL_MODE -#include "lowlevel.h" +#include "option_bytes.h" #include "common.h" #include "flash.h" #include "model.h" @@ -41,7 +41,6 @@ #ifdef VDD_3V3 // BOR LEVEL 0: Reset level threshold is around 2.8 V #define WANT_BOR_LEVEL (OB_BOR_LEVEL_4) -#define USE_PVD 1 #elif VDD_1V8 // BOR LEVEL 0: Reset level threshold is around 1.7 V #define WANT_BOR_LEVEL (OB_BOR_LEVEL_0) @@ -266,51 +265,4 @@ secbool flash_configure_option_bytes(void) { return secfalse; // notify that we DID have to change the option bytes } -void periph_init(void) { - // STM32U5xx HAL library initialization: - // - configure the Flash prefetch, instruction and data caches - // - configure the Systick to generate an interrupt each 1 msec - // - set NVIC Group Priority to 4 - // - global MSP (MCU Support Package) initialization - HAL_Init(); - - // Enable GPIO clocks - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - -#ifdef USE_PVD - // enable the PVD (programmable voltage detector). - // select the "2.8V" threshold (level 5). - // this detector will be active regardless of the - // flash option byte BOR setting. - __HAL_RCC_PWR_CLK_ENABLE(); - PWR_PVDTypeDef pvd_config = {0}; - pvd_config.PVDLevel = PWR_PVDLEVEL_5; - pvd_config.Mode = PWR_PVD_MODE_IT_RISING_FALLING; - HAL_PWR_ConfigPVD(&pvd_config); - HAL_PWR_EnablePVD(); - NVIC_EnableIRQ(PVD_PVM_IRQn); -#endif -} - -secbool reset_flags_check(void) { -#if PRODUCTION - // this is effective enough that it makes development painful, so only use it - // for production. check the reset flags to assure that we arrive here due to - // a regular full power-on event, and not as a result of a lesser reset. - if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | - RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF | - RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { - return secfalse; - } -#endif - return sectrue; -} - -void reset_flags_reset(void) { - RCC->CSR |= RCC_CSR_RMVF; // clear the reset flags -} - #endif // #ifdef KERNEL_MODE diff --git a/core/embed/trezorhal/stm32u5/pvd.c b/core/embed/trezorhal/stm32u5/pvd.c new file mode 120000 index 0000000000..e94aab5b3e --- /dev/null +++ b/core/embed/trezorhal/stm32u5/pvd.c @@ -0,0 +1 @@ +../stm32f4/pvd.c \ No newline at end of file diff --git a/core/embed/trezorhal/stm32u5/reset_flags.c b/core/embed/trezorhal/stm32u5/reset_flags.c new file mode 100644 index 0000000000..ce4a664b93 --- /dev/null +++ b/core/embed/trezorhal/stm32u5/reset_flags.c @@ -0,0 +1,45 @@ +/* + * This file is part of the Trezor project, https://trezor.io/ + * + * Copyright (c) SatoshiLabs + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include STM32_HAL_H + +#include "reset_flags.h" + +#ifdef KERNEL_MODE + +secbool reset_flags_check(void) { +#if PRODUCTION + // this is effective enough that it makes development painful, so only use it + // for production. check the reset flags to assure that we arrive here due to + // a regular full power-on event, and not as a result of a lesser reset. + if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | + RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | + RCC_CSR_BORRSTF)) != + (RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { + return secfalse; + } +#endif + return sectrue; +} + +void reset_flags_reset(void) { + RCC->CSR |= RCC_CSR_RMVF; // clear the reset flags +} + +#endif diff --git a/core/embed/trezorhal/stm32u5/startup_init.c b/core/embed/trezorhal/stm32u5/startup_init.c index 393a43b530..a5f26742ac 100644 --- a/core/embed/trezorhal/stm32u5/startup_init.c +++ b/core/embed/trezorhal/stm32u5/startup_init.c @@ -214,6 +214,24 @@ void SystemInit(void) { // enable instruction cache in default 2-way mode ICACHE->CR = ICACHE_CR_EN; + + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ + /// SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & + /// RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + // Enable GPIO clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); } #endif // #ifdef KERNEL_MODE diff --git a/core/site_scons/models/stm32f4_common.py b/core/site_scons/models/stm32f4_common.py index 18add8554c..400595207f 100644 --- a/core/site_scons/models/stm32f4_common.py +++ b/core/site_scons/models/stm32f4_common.py @@ -48,10 +48,12 @@ def stm32f4_common_files(env, defines, sources, paths): "embed/trezorhal/stm32f4/flash_otp.c", "embed/trezorhal/stm32f4/fwutils.c", "embed/trezorhal/stm32f4/layout.c", - "embed/trezorhal/stm32f4/lowlevel.c", "embed/trezorhal/stm32f4/monoctr.c", "embed/trezorhal/stm32f4/mpu.c", + "embed/trezorhal/stm32f4/option_bytes.c", + "embed/trezorhal/stm32f4/pvd.c", "embed/trezorhal/stm32f4/random_delays.c", + "embed/trezorhal/stm32f4/reset_flags.c", "embed/trezorhal/stm32f4/rng.c", "embed/trezorhal/stm32f4/secret.c", "embed/trezorhal/stm32f4/startup_init.c", diff --git a/core/site_scons/models/stm32u5_common.py b/core/site_scons/models/stm32u5_common.py index 2ab4d6aa85..c9ac21e29b 100644 --- a/core/site_scons/models/stm32u5_common.py +++ b/core/site_scons/models/stm32u5_common.py @@ -57,11 +57,13 @@ def stm32u5_common_files(env, defines, sources, paths): "embed/trezorhal/stm32u5/flash_otp.c", "embed/trezorhal/stm32u5/fwutils.c", "embed/trezorhal/stm32u5/layout.c", - "embed/trezorhal/stm32u5/lowlevel.c", "embed/trezorhal/stm32u5/hash_processor.c", "embed/trezorhal/stm32u5/monoctr.c", "embed/trezorhal/stm32u5/mpu.c", + "embed/trezorhal/stm32u5/option_bytes.c", + "embed/trezorhal/stm32u5/pvd.c", "embed/trezorhal/stm32u5/random_delays.c", + "embed/trezorhal/stm32u5/reset_flags.c", "embed/trezorhal/stm32u5/rng.c", "embed/trezorhal/stm32u5/secret.c", "embed/trezorhal/stm32u5/secure_aes.c",