2017-10-24 16:16:36 +00:00
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/* TREZORv2 firmware linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x08040000, LENGTH = 768K
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CCMRAM (wal) : ORIGIN = 0x10000000, LENGTH = 64K
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SRAM (wal) : ORIGIN = 0x20000000, LENGTH = 192K
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}
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main_stack_base = ORIGIN(SRAM) + LENGTH(SRAM); /* 8-byte aligned full descending stack */
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to wipe memory */
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ccmram_start = ORIGIN(CCMRAM);
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ccmram_end = ORIGIN(CCMRAM) + LENGTH(CCMRAM);
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/* used by the startup code to wipe memory */
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sram_start = ORIGIN(SRAM);
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sram_end = ORIGIN(SRAM) + LENGTH(SRAM);
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_ram_start = sram_start;
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_ram_end = sram_end;
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_codelen = SIZEOF(.flash) + SIZEOF(.data);
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_flash_start = ORIGIN(FLASH);
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_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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_heap_start = ADDR(.heap);
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_heap_end = ADDR(.heap) + SIZEOF(.heap);
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SECTIONS {
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2017-10-26 22:41:22 +00:00
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.vendorheader : ALIGN(4) {
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2017-10-24 16:16:36 +00:00
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KEEP(*(.vendorheader))
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2017-10-26 22:41:22 +00:00
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} >FLASH AT>FLASH
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.header : ALIGN(4) {
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2017-10-24 16:16:36 +00:00
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM AT>FLASH
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM
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.heap : ALIGN(4) {
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. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
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. = ABSOLUTE(sram_end - 16K); /* this explicitly sets the end of the heap effectively giving the stack at most 16K */
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} >SRAM
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.stack : ALIGN(8) {
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. = 4K; /* this acts as a build time assertion that at least this much memory is available for stack use */
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} >SRAM
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}
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