From 16bb7744f39795fb25e0d494a9b9422cc3493e81 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Fri, 16 Mar 2018 10:42:44 +0800 Subject: [PATCH 1/2] Booting/linux-bootstrap-1.md: lowercase coreboot[1], http->https [1] in coreboot source code: util/lint/lint-stable-021-coreboot-lowercase --- Booting/linux-bootstrap-1.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Booting/linux-bootstrap-1.md b/Booting/linux-bootstrap-1.md index 66e0508..82d542a 100644 --- a/Booting/linux-bootstrap-1.md +++ b/Booting/linux-bootstrap-1.md @@ -38,7 +38,7 @@ CS base 0xffff0000 The processor starts working in [real mode](https://en.wikipedia.org/wiki/Real_mode). Let's back up a little and try to understand [memory segmentation](https://en.wikipedia.org/wiki/Memory_segmentation) in this mode. Real mode is supported on all x86-compatible processors, from the [8086](https://en.wikipedia.org/wiki/Intel_8086) CPU all the way to the modern Intel 64-bit CPUs. The `8086` processor has a 20-bit address bus, which means that it could work with a `0-0xFFFFF` or `1 megabyte` address space. But it only has `16-bit` registers, which have a maximum address of `2^16 - 1` or `0xffff` (64 kilobytes). -[Memory segmentation](http://en.wikipedia.org/wiki/Memory_segmentation) is used to make use of all the address space available. All memory is divided into small, fixed-size segments of `65536` bytes (64 KB). Since we cannot address memory above `64 KB` with 16-bit registers, an alternate method was devised. +[Memory segmentation](https://en.wikipedia.org/wiki/Memory_segmentation) is used to make use of all the address space available. All memory is divided into small, fixed-size segments of `65536` bytes (64 KB). Since we cannot address memory above `64 KB` with 16-bit registers, an alternate method was devised. An address consists of two parts: a segment selector, which has a base address, and an offset from this base address. In real mode, the associated base address of a segment selector is `Segment Selector * 16`. Thus, to get a physical address in memory, we need to multiply the segment selector part by `16` and add the offset to it: @@ -73,7 +73,7 @@ The starting address is formed by adding the base address to the value in the EI '0xfffffff0' ``` -We get `0xfffffff0`, which is 16 bytes below 4GB. This point is called the [Reset vector](http://en.wikipedia.org/wiki/Reset_vector). This is the memory location at which the CPU expects to find the first instruction to execute after reset. It contains a [jump](http://en.wikipedia.org/wiki/JMP_%28x86_instruction%29) (`jmp`) instruction that usually points to the BIOS entry point. For example, if we look in the [coreboot](http://www.coreboot.org/) source code (`src/cpu/x86/16bit/reset16.inc`), we will see: +We get `0xfffffff0`, which is 16 bytes below 4GB. This point is called the [Reset vector](https://en.wikipedia.org/wiki/Reset_vector). This is the memory location at which the CPU expects to find the first instruction to execute after reset. It contains a [jump](https://en.wikipedia.org/wiki/JMP_%28x86_instruction%29) (`jmp`) instruction that usually points to the BIOS entry point. For example, if we look in the [coreboot](https://www.coreboot.org/) source code (`src/cpu/x86/16bit/reset16.inc`), we will see: ```assembly .section ".reset" @@ -180,7 +180,7 @@ In general, real mode's memory map is as follows: 0x000F0000 - 0x000FFFFF - System BIOS ``` -In the beginning of this post, I wrote that the first instruction executed by the CPU is located at address `0xFFFFFFF0`, which is much larger than `0xFFFFF` (1MB). How can the CPU access this address in real mode? The answer is in the [coreboot](http://www.coreboot.org/Developer_Manual/Memory_map) documentation: +In the beginning of this post, I wrote that the first instruction executed by the CPU is located at address `0xFFFFFFF0`, which is much larger than `0xFFFFF` (1MB). How can the CPU access this address in real mode? The answer is in the [coreboot](https://www.coreboot.org/Developer_Manual/Memory_map) documentation: ``` 0xFFFE_0000 - 0xFFFF_FFFF: 128 kilobyte ROM mapped into address space @@ -491,12 +491,12 @@ Links * [Intel 80386 programmer's reference manual 1986](http://css.csail.mit.edu/6.858/2014/readings/i386.pdf) * [Minimal Boot Loader for Intel® Architecture](https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf) - * [8086](http://en.wikipedia.org/wiki/Intel_8086) - * [80386](http://en.wikipedia.org/wiki/Intel_80386) - * [Reset vector](http://en.wikipedia.org/wiki/Reset_vector) - * [Real mode](http://en.wikipedia.org/wiki/Real_mode) + * [8086](https://en.wikipedia.org/wiki/Intel_8086) + * [80386](https://en.wikipedia.org/wiki/Intel_80386) + * [Reset vector](https://en.wikipedia.org/wiki/Reset_vector) + * [Real mode](https://en.wikipedia.org/wiki/Real_mode) * [Linux kernel boot protocol](https://www.kernel.org/doc/Documentation/x86/boot.txt) - * [CoreBoot developer manual](http://www.coreboot.org/Developer_Manual) + * [coreboot developer manual](https://www.coreboot.org/Developer_Manual) * [Ralf Brown's Interrupt List](http://www.ctyme.com/intr/int.htm) - * [Power supply](http://en.wikipedia.org/wiki/Power_supply) - * [Power good signal](http://en.wikipedia.org/wiki/Power_good_signal) + * [Power supply](https://en.wikipedia.org/wiki/Power_supply) + * [Power good signal](https://en.wikipedia.org/wiki/Power_good_signal) From 2da09c87552b0e4f344e5bbc41b059e38cf7d98e Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Fri, 16 Mar 2018 10:46:01 +0800 Subject: [PATCH 2/2] Booting/linux-bootstrap-1.md: update to the latest coreboot code --- Booting/linux-bootstrap-1.md | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/Booting/linux-bootstrap-1.md b/Booting/linux-bootstrap-1.md index 82d542a..48e80d2 100644 --- a/Booting/linux-bootstrap-1.md +++ b/Booting/linux-bootstrap-1.md @@ -76,26 +76,28 @@ The starting address is formed by adding the base address to the value in the EI We get `0xfffffff0`, which is 16 bytes below 4GB. This point is called the [Reset vector](https://en.wikipedia.org/wiki/Reset_vector). This is the memory location at which the CPU expects to find the first instruction to execute after reset. It contains a [jump](https://en.wikipedia.org/wiki/JMP_%28x86_instruction%29) (`jmp`) instruction that usually points to the BIOS entry point. For example, if we look in the [coreboot](https://www.coreboot.org/) source code (`src/cpu/x86/16bit/reset16.inc`), we will see: ```assembly - .section ".reset" + .section ".reset", "ax", %progbits .code16 -.globl reset_vector -reset_vector: +.globl _start +_start: .byte 0xe9 - .int _start - ( . + 2 ) + .int _start16bit - ( . + 2 ) ... ``` -Here we can see the `jmp` instruction [opcode](http://ref.x86asm.net/coder32.html#xE9), which is `0xe9`, and its destination address at `_start - ( . + 2)`. +Here we can see the `jmp` instruction [opcode](http://ref.x86asm.net/coder32.html#xE9), which is `0xe9`, and its destination address at `_start16bit - ( . + 2)`. -We can also see that the `reset` section is `16` bytes and that is compiled to start from `0xfffffff0` address (`src/cpu/x86/16bit/reset16.lds`): +We can also see that the `reset` section is `16` bytes and that is compiled to start from `0xfffffff0` address (`src/cpu/x86/16bit/reset16.ld`): ``` SECTIONS { + /* Trigger an error if I have an unuseable start address */ + _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { - *(.reset) - . = 15 ; + *(.reset); + . = 15; BYTE(0x00); } }