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Fix typo at the description of IDT entries
s/special mechanism in the x86_64, will see it later;/ special mechanism in the x86_64, which is described below;/
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@ -214,7 +214,7 @@ As we can see, `IDT` entry on the diagram consists of the following fields:
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* `0-15` bits - offset from the segment selector which is used by the processor as the base address of the entry point of the interrupt handler;
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* `16-31` bits - base address of the segment select which contains the entry point of the interrupt handler;
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* `IST` - a new special mechanism in the `x86_64`, will see it later;
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* `IST` - a new special mechanism in the `x86_64`, which is described below;
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* `DPL` - Descriptor Privilege Level;
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* `P` - Segment Present flag;
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* `48-63` bits - the second part of the handler base address;
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