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Commit Graph

11 Commits

Author SHA1 Message Date
jsteube
dad03e394d Fixed two major problems
1) SIMD code for all attack-mode

Macro vector_accessible() was not refactored and missing completely.
Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way.

2) SIMD code for attack-mode 0

With new SIMD code, apply_rules_vect() has to return u32 not u32x.
This has massive impact on all *_a0 kernels.

I've rewritten most of them. Deep testing using test.sh is still required.

Some kernel need more fixes:

- Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c
- Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them

This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this.
This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
magnum
a5be8a75ed Allow and support vector-width 16, which is current maximum for
OpenCL. Closes #226.
2016-02-18 08:51:45 +01:00
jsteube
7c6b3af23b Fix issue in https://github.com/hashcat/oclHashcat/issues/170 2016-01-27 20:01:08 +01:00
Gabriele 'matrix' Gristina
7acfac87cf Fixed compiler warnings (no previous prototype for function) 2016-01-25 13:35:58 +01:00
Jens Steube
4c0e520fd8 Test convert for -m 1000 with -a 0 for SIMD, speed is now on par or faster than hashcat 2016-01-21 16:47:38 +01:00
Jens Steube
62f66a8784 Workaround AMD catalyst optimizer bug in rule-engine 2016-01-19 20:54:25 +01:00
jsteube
e0ea23bda9 Fix bug in rule-engine for NV, left shifts and right shifts were switched 2016-01-16 13:34:54 +01:00
jsteube
76612ac031 Fix more missing casts to uint in rule-engine 2016-01-14 20:54:41 +01:00
jsteube
e8229af09b Fix for -m 1500, -m 3000: Missing "defined" keyword
Fix for -m 1000: MD4_H1 copy/paste error
Fix for -m 8900, -m 9300: Invalid value for device_processor_cores for CPU devices
Fix for -m 9100: Variable salt2 initializer needed some clauses for clearness
Temporary limit gpu_accel for CPU devices to 1 for development phase
Mark pocl as too bleeding edge for production use, recommend native drivers
Remove workarounds for pocl
Rename VENDOR_ID_UNKNOWN to VENDOR_ID_GENERIC in host code
Rename IS_UNKNOWN to IS_GENERIC in kernel code
2016-01-07 20:14:34 +01:00
jsteube
bacc1049e3 More fixes for IS_UNKNOWN in kernels 2016-01-05 23:05:06 +01:00
jsteube
0bf4e3c34a - Dropped all vector code since new GPU's are all scalar, makes the code much easier
- Some performance on low-end GPU may drop because of that, but only for a few hash-modes
- Dropped scalar code (aka warp) since we do not have any vector datatypes anymore
- Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4
- Still need to fix kernels to new function names, needs to be done manually
- Temperature Management needs to be rewritten partially because of conflicting datatypes names
- Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id)
- Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD)
- First tests working for -m 0, for example
- Great performance increases in general for NV so far
- Tested amp_* and markov_* kernel
- Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00