- Remove inline keywords
- Remove volatile keywords where it causes ROCm to slow down
- Replace DES functions (looks like bitselect somehow is no longer mapped to BFI_INT)
1) SIMD code for all attack-mode
Macro vector_accessible() was not refactored and missing completely.
Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way.
2) SIMD code for attack-mode 0
With new SIMD code, apply_rules_vect() has to return u32 not u32x.
This has massive impact on all *_a0 kernels.
I've rewritten most of them. Deep testing using test.sh is still required.
Some kernel need more fixes:
- Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c
- Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them
This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this.
This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
- Replaced SBOX for DES:
replaced JtR's * Bitslice DES S-boxes making use of a vector conditional select operation (e.g., vsel on PowerPC with AltiVec).
with JtR's * Bitslice DES S-boxes for x86 with MMX/SSE2/AVX and for typical RISC architectures.
Performance increased for DEScrypt from 355MH/s to 405MH/s and for LM from 11100MH/s to 12000MH/s
BTW, the same effect can be seen with non-maxwell GPU's
- Remove some volatile keywords no longer needed thanks to fixed catalyst bugs
- Fix weak-hash-check parameter for use with tools/test.sh
Fix for -m 1000: MD4_H1 copy/paste error
Fix for -m 8900, -m 9300: Invalid value for device_processor_cores for CPU devices
Fix for -m 9100: Variable salt2 initializer needed some clauses for clearness
Temporary limit gpu_accel for CPU devices to 1 for development phase
Mark pocl as too bleeding edge for production use, recommend native drivers
Remove workarounds for pocl
Rename VENDOR_ID_UNKNOWN to VENDOR_ID_GENERIC in host code
Rename IS_UNKNOWN to IS_GENERIC in kernel code
- Some performance on low-end GPU may drop because of that, but only for a few hash-modes
- Dropped scalar code (aka warp) since we do not have any vector datatypes anymore
- Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4
- Still need to fix kernels to new function names, needs to be done manually
- Temperature Management needs to be rewritten partially because of conflicting datatypes names
- Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id)
- Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD)
- First tests working for -m 0, for example
- Great performance increases in general for NV so far
- Tested amp_* and markov_* kernel
- Migrated special NV optimizations for rule processor
