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Update HIP includes to work with Linux on HIP 5.1.20531+
This commit is contained in:
Jens Steube
parent
4b4f9b61b9
commit
cf352e4f8b
@ -10,7 +10,7 @@
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// Therefore, we need to take certain items, such as hipDeviceptr_t from driver specific paths like amd_driver_types.h
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// We just need to keep this in mind in case we need to update these constants from future SDK versions
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// start: amd_driver_types.h
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// start: driver_types.h
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typedef void* hipDeviceptr_t;
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@ -28,7 +28,7 @@ typedef enum hipFunction_attribute {
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HIP_FUNC_ATTRIBUTE_MAX
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} hipFunction_attribute;
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// stop: amd_driver_types.h
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// stop: driver_types.h
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// start: hip_runtime_api.h
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@ -101,6 +101,7 @@ typedef enum __HIP_NODISCARD hipError_t {
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hipErrorInvalidHandle = 400,
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// Deprecated
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hipErrorInvalidResourceHandle = 400, ///< Resource handle (hipEvent_t or hipStream_t) invalid.
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hipErrorIllegalState = 401, ///< Resource required is not in a valid state to perform operation.
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hipErrorNotFound = 500,
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hipErrorNotReady = 600, ///< Indicates that asynchronous operations enqueued earlier are not
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///< ready. This is not actually an error, but is used to distinguish
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@ -149,6 +150,10 @@ typedef enum __HIP_NODISCARD hipError_t {
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///< the hipStreamCaptureModeRelaxed argument to
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///< hipStreamBeginCapture was passed to
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///< hipStreamEndCapture in a different thread.
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hipErrorGraphExecUpdateFailure = 910, ///< This error indicates that the graph update
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///< not performed because it included changes which
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///< violated constraintsspecific to instantiated graph
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///< update.
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hipErrorUnknown = 999, //< Unknown error.
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// HSA Runtime Error Codes start here.
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hipErrorRuntimeMemory = 1052, ///< HSA runtime memory call returned error. Typically not seen
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@ -161,112 +166,170 @@ typedef enum __HIP_NODISCARD hipError_t {
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#undef __HIP_NODISCARD
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typedef enum hipDeviceAttribute_t {
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hipDeviceAttributeMaxThreadsPerBlock, ///< Maximum number of threads per block.
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hipDeviceAttributeMaxBlockDimX, ///< Maximum x-dimension of a block.
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hipDeviceAttributeMaxBlockDimY, ///< Maximum y-dimension of a block.
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hipDeviceAttributeMaxBlockDimZ, ///< Maximum z-dimension of a block.
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hipDeviceAttributeMaxGridDimX, ///< Maximum x-dimension of a grid.
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hipDeviceAttributeMaxGridDimY, ///< Maximum y-dimension of a grid.
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hipDeviceAttributeMaxGridDimZ, ///< Maximum z-dimension of a grid.
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hipDeviceAttributeMaxSharedMemoryPerBlock, ///< Maximum shared memory available per block in
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///< bytes.
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hipDeviceAttributeTotalConstantMemory, ///< Constant memory size in bytes.
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hipDeviceAttributeWarpSize, ///< Warp size in threads.
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hipDeviceAttributeMaxRegistersPerBlock, ///< Maximum number of 32-bit registers available to a
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///< thread block. This number is shared by all thread
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///< blocks simultaneously resident on a
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///< multiprocessor.
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hipDeviceAttributeCudaCompatibleBegin = 0,
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hipDeviceAttributeEccEnabled = hipDeviceAttributeCudaCompatibleBegin, ///< Whether ECC support is enabled.
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hipDeviceAttributeAccessPolicyMaxWindowSize, ///< Cuda only. The maximum size of the window policy in bytes.
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hipDeviceAttributeAsyncEngineCount, ///< Cuda only. Asynchronous engines number.
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hipDeviceAttributeCanMapHostMemory, ///< Whether host memory can be mapped into device address space
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hipDeviceAttributeCanUseHostPointerForRegisteredMem,///< Cuda only. Device can access host registered memory
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///< at the same virtual address as the CPU
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hipDeviceAttributeClockRate, ///< Peak clock frequency in kilohertz.
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hipDeviceAttributeMemoryClockRate, ///< Peak memory clock frequency in kilohertz.
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hipDeviceAttributeMemoryBusWidth, ///< Global memory bus width in bits.
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hipDeviceAttributeMultiprocessorCount, ///< Number of multiprocessors on the device.
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hipDeviceAttributeComputeMode, ///< Compute mode that device is currently in.
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hipDeviceAttributeL2CacheSize, ///< Size of L2 cache in bytes. 0 if the device doesn't have L2
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///< cache.
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hipDeviceAttributeMaxThreadsPerMultiProcessor, ///< Maximum resident threads per
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///< multiprocessor.
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hipDeviceAttributeComputeCapabilityMajor, ///< Major compute capability version number.
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hipDeviceAttributeComputeCapabilityMinor, ///< Minor compute capability version number.
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hipDeviceAttributeConcurrentKernels, ///< Device can possibly execute multiple kernels
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///< concurrently.
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hipDeviceAttributePciBusId, ///< PCI Bus ID.
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hipDeviceAttributePciDeviceId, ///< PCI Device ID.
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hipDeviceAttributeMaxSharedMemoryPerMultiprocessor, ///< Maximum Shared Memory Per
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///< Multiprocessor.
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hipDeviceAttributeIsMultiGpuBoard, ///< Multiple GPU devices.
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hipDeviceAttributeIntegrated, ///< iGPU
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hipDeviceAttributeComputePreemptionSupported, ///< Cuda only. Device supports Compute Preemption.
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hipDeviceAttributeConcurrentKernels, ///< Device can possibly execute multiple kernels concurrently.
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hipDeviceAttributeConcurrentManagedAccess, ///< Device can coherently access managed memory concurrently with the CPU
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hipDeviceAttributeCooperativeLaunch, ///< Support cooperative launch
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hipDeviceAttributeCooperativeMultiDeviceLaunch, ///< Support cooperative launch on multiple devices
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hipDeviceAttributeMaxTexture1DWidth, ///< Maximum number of elements in 1D images
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hipDeviceAttributeMaxTexture2DWidth, ///< Maximum dimension width of 2D images in image elements
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hipDeviceAttributeMaxTexture2DHeight, ///< Maximum dimension height of 2D images in image elements
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hipDeviceAttributeMaxTexture3DWidth, ///< Maximum dimension width of 3D images in image elements
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hipDeviceAttributeMaxTexture3DHeight, ///< Maximum dimensions height of 3D images in image elements
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hipDeviceAttributeMaxTexture3DDepth, ///< Maximum dimensions depth of 3D images in image elements
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hipDeviceAttributeHdpMemFlushCntl, ///< Address of the HDP_MEM_COHERENCY_FLUSH_CNTL register
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hipDeviceAttributeHdpRegFlushCntl, ///< Address of the HDP_REG_COHERENCY_FLUSH_CNTL register
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hipDeviceAttributeDeviceOverlap, ///< Cuda only. Device can concurrently copy memory and execute a kernel.
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///< Deprecated. Use instead asyncEngineCount.
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hipDeviceAttributeDirectManagedMemAccessFromHost, ///< Host can directly access managed memory on
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///< the device without migration
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hipDeviceAttributeGlobalL1CacheSupported, ///< Cuda only. Device supports caching globals in L1
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hipDeviceAttributeHostNativeAtomicSupported, ///< Cuda only. Link between the device and the host supports native atomic operations
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hipDeviceAttributeIntegrated, ///< Device is integrated GPU
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hipDeviceAttributeIsMultiGpuBoard, ///< Multiple GPU devices.
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hipDeviceAttributeKernelExecTimeout, ///< Run time limit for kernels executed on the device
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hipDeviceAttributeL2CacheSize, ///< Size of L2 cache in bytes. 0 if the device doesn't have L2 cache.
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hipDeviceAttributeLocalL1CacheSupported, ///< caching locals in L1 is supported
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hipDeviceAttributeLuid, ///< Cuda only. 8-byte locally unique identifier in 8 bytes. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeLuidDeviceNodeMask, ///< Cuda only. Luid device node mask. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeComputeCapabilityMajor, ///< Major compute capability version number.
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hipDeviceAttributeManagedMemory, ///< Device supports allocating managed memory on this system
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hipDeviceAttributeMaxBlocksPerMultiProcessor, ///< Cuda only. Max block size per multiprocessor
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hipDeviceAttributeMaxBlockDimX, ///< Max block size in width.
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hipDeviceAttributeMaxBlockDimY, ///< Max block size in height.
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hipDeviceAttributeMaxBlockDimZ, ///< Max block size in depth.
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hipDeviceAttributeMaxGridDimX, ///< Max grid size in width.
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hipDeviceAttributeMaxGridDimY, ///< Max grid size in height.
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hipDeviceAttributeMaxGridDimZ, ///< Max grid size in depth.
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hipDeviceAttributeMaxSurface1D, ///< Maximum size of 1D surface.
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hipDeviceAttributeMaxSurface1DLayered, ///< Cuda only. Maximum dimensions of 1D layered surface.
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hipDeviceAttributeMaxSurface2D, ///< Maximum dimension (width, height) of 2D surface.
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hipDeviceAttributeMaxSurface2DLayered, ///< Cuda only. Maximum dimensions of 2D layered surface.
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hipDeviceAttributeMaxSurface3D, ///< Maximum dimension (width, height, depth) of 3D surface.
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hipDeviceAttributeMaxSurfaceCubemap, ///< Cuda only. Maximum dimensions of Cubemap surface.
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hipDeviceAttributeMaxSurfaceCubemapLayered, ///< Cuda only. Maximum dimension of Cubemap layered surface.
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hipDeviceAttributeMaxTexture1DWidth, ///< Maximum size of 1D texture.
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hipDeviceAttributeMaxTexture1DLayered, ///< Cuda only. Maximum dimensions of 1D layered texture.
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hipDeviceAttributeMaxTexture1DLinear, ///< Maximum number of elements allocatable in a 1D linear texture.
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///< Use cudaDeviceGetTexture1DLinearMaxWidth() instead on Cuda.
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hipDeviceAttributeMaxTexture1DMipmap, ///< Cuda only. Maximum size of 1D mipmapped texture.
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hipDeviceAttributeMaxTexture2DWidth, ///< Maximum dimension width of 2D texture.
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hipDeviceAttributeMaxTexture2DHeight, ///< Maximum dimension hight of 2D texture.
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hipDeviceAttributeMaxTexture2DGather, ///< Cuda only. Maximum dimensions of 2D texture if gather operations performed.
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hipDeviceAttributeMaxTexture2DLayered, ///< Cuda only. Maximum dimensions of 2D layered texture.
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hipDeviceAttributeMaxTexture2DLinear, ///< Cuda only. Maximum dimensions (width, height, pitch) of 2D textures bound to pitched memory.
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hipDeviceAttributeMaxTexture2DMipmap, ///< Cuda only. Maximum dimensions of 2D mipmapped texture.
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hipDeviceAttributeMaxTexture3DWidth, ///< Maximum dimension width of 3D texture.
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hipDeviceAttributeMaxTexture3DHeight, ///< Maximum dimension height of 3D texture.
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hipDeviceAttributeMaxTexture3DDepth, ///< Maximum dimension depth of 3D texture.
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hipDeviceAttributeMaxTexture3DAlt, ///< Cuda only. Maximum dimensions of alternate 3D texture.
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hipDeviceAttributeMaxTextureCubemap, ///< Cuda only. Maximum dimensions of Cubemap texture
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hipDeviceAttributeMaxTextureCubemapLayered, ///< Cuda only. Maximum dimensions of Cubemap layered texture.
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hipDeviceAttributeMaxThreadsDim, ///< Maximum dimension of a block
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hipDeviceAttributeMaxThreadsPerBlock, ///< Maximum number of threads per block.
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hipDeviceAttributeMaxThreadsPerMultiProcessor, ///< Maximum resident threads per multiprocessor.
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hipDeviceAttributeMaxPitch, ///< Maximum pitch in bytes allowed by memory copies
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hipDeviceAttributeMemoryBusWidth, ///< Global memory bus width in bits.
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hipDeviceAttributeMemoryClockRate, ///< Peak memory clock frequency in kilohertz.
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hipDeviceAttributeComputeCapabilityMinor, ///< Minor compute capability version number.
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hipDeviceAttributeMultiGpuBoardGroupID, ///< Cuda only. Unique ID of device group on the same multi-GPU board
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hipDeviceAttributeMultiprocessorCount, ///< Number of multiprocessors on the device.
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hipDeviceAttributeName, ///< Device name.
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hipDeviceAttributePageableMemoryAccess, ///< Device supports coherently accessing pageable memory
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///< without calling hipHostRegister on it
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hipDeviceAttributePageableMemoryAccessUsesHostPageTables, ///< Device accesses pageable memory via the host's page tables
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hipDeviceAttributePciBusId, ///< PCI Bus ID.
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hipDeviceAttributePciDeviceId, ///< PCI Device ID.
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hipDeviceAttributePciDomainID, ///< PCI Domain ID.
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hipDeviceAttributePersistingL2CacheMaxSize, ///< Cuda11 only. Maximum l2 persisting lines capacity in bytes
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hipDeviceAttributeMaxRegistersPerBlock, ///< 32-bit registers available to a thread block. This number is shared
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///< by all thread blocks simultaneously resident on a multiprocessor.
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hipDeviceAttributeMaxRegistersPerMultiprocessor, ///< 32-bit registers available per block.
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hipDeviceAttributeReservedSharedMemPerBlock, ///< Cuda11 only. Shared memory reserved by CUDA driver per block.
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hipDeviceAttributeMaxSharedMemoryPerBlock, ///< Maximum shared memory available per block in bytes.
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hipDeviceAttributeSharedMemPerBlockOptin, ///< Cuda only. Maximum shared memory per block usable by special opt in.
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hipDeviceAttributeSharedMemPerMultiprocessor, ///< Cuda only. Shared memory available per multiprocessor.
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hipDeviceAttributeSingleToDoublePrecisionPerfRatio, ///< Cuda only. Performance ratio of single precision to double precision.
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hipDeviceAttributeStreamPrioritiesSupported, ///< Cuda only. Whether to support stream priorities.
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hipDeviceAttributeSurfaceAlignment, ///< Cuda only. Alignment requirement for surfaces
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hipDeviceAttributeTccDriver, ///< Cuda only. Whether device is a Tesla device using TCC driver
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hipDeviceAttributeTextureAlignment, ///< Alignment requirement for textures
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hipDeviceAttributeTexturePitchAlignment, ///< Pitch alignment requirement for 2D texture references bound to pitched memory;
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hipDeviceAttributeKernelExecTimeout, ///<Run time limit for kernels executed on the device
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hipDeviceAttributeCanMapHostMemory, ///<Device can map host memory into device address space
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hipDeviceAttributeEccEnabled, ///<Device has ECC support enabled
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hipDeviceAttributeTotalConstantMemory, ///< Constant memory size in bytes.
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hipDeviceAttributeTotalGlobalMem, ///< Global memory available on devicice.
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hipDeviceAttributeUnifiedAddressing, ///< Cuda only. An unified address space shared with the host.
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hipDeviceAttributeUuid, ///< Cuda only. Unique ID in 16 byte.
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hipDeviceAttributeWarpSize, ///< Warp size in threads.
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hipDeviceAttributeCudaCompatibleEnd = 9999,
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hipDeviceAttributeAmdSpecificBegin = 10000,
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hipDeviceAttributeClockInstructionRate = hipDeviceAttributeAmdSpecificBegin, ///< Frequency in khz of the timer used by the device-side "clock*"
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hipDeviceAttributeArch, ///< Device architecture
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hipDeviceAttributeMaxSharedMemoryPerMultiprocessor, ///< Maximum Shared Memory PerMultiprocessor.
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hipDeviceAttributeGcnArch, ///< Device gcn architecture
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hipDeviceAttributeGcnArchName, ///< Device gcnArch name in 256 bytes
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hipDeviceAttributeHdpMemFlushCntl, ///< Address of the HDP_MEM_COHERENCY_FLUSH_CNTL register
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hipDeviceAttributeHdpRegFlushCntl, ///< Address of the HDP_REG_COHERENCY_FLUSH_CNTL register
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hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc, ///< Supports cooperative launch on multiple
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///devices with unmatched functions
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///< devices with unmatched functions
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hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim, ///< Supports cooperative launch on multiple
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///devices with unmatched grid dimensions
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///< devices with unmatched grid dimensions
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hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim, ///< Supports cooperative launch on multiple
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///devices with unmatched block dimensions
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///< devices with unmatched block dimensions
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hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem, ///< Supports cooperative launch on multiple
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///devices with unmatched shared memories
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///< devices with unmatched shared memories
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hipDeviceAttributeIsLargeBar, ///< Whether it is LargeBar
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hipDeviceAttributeAsicRevision, ///< Revision of the GPU in this device
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hipDeviceAttributeManagedMemory, ///< Device supports allocating managed memory on this system
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hipDeviceAttributeDirectManagedMemAccessFromHost, ///< Host can directly access managed memory on
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/// the device without migration
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hipDeviceAttributeConcurrentManagedAccess, ///< Device can coherently access managed memory
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/// concurrently with the CPU
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hipDeviceAttributePageableMemoryAccess, ///< Device supports coherently accessing pageable memory
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/// without calling hipHostRegister on it
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hipDeviceAttributePageableMemoryAccessUsesHostPageTables, ///< Device accesses pageable memory via
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/// the host's page tables
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hipDeviceAttributeCanUseStreamWaitValue ///< '1' if Device supports hipStreamWaitValue32() and
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hipDeviceAttributeCanUseStreamWaitValue, ///< '1' if Device supports hipStreamWaitValue32() and
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///< hipStreamWaitValue64(), '0' otherwise.
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hipDeviceAttributeImageSupport, ///< '1' if Device supports image, '0' otherwise.
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hipDeviceAttributePhysicalMultiProcessorCount, ///< All available physical compute
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///< units for the device
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hipDeviceAttributeAmdSpecificEnd = 19999,
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hipDeviceAttributeVendorSpecificBegin = 20000,
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// Extended attributes for vendors
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} hipDeviceAttribute_t;
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//! Flags that can be used with hipStreamCreateWithFlags
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#define hipStreamDefault \
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0x00 ///< Default stream creation flags. These are used with hipStreamCreate().
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#define hipStreamNonBlocking 0x01 ///< Stream does not implicitly synchronize with null stream
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//Flags that can be used with hipStreamCreateWithFlags.
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/** Default stream creation flags. These are used with hipStreamCreate().*/
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#define hipStreamDefault 0x00
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/** Stream does not implicitly synchronize with null stream.*/
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#define hipStreamNonBlocking 0x01
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//! Flags that can be used with hipEventCreateWithFlags:
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#define hipEventDefault 0x0 ///< Default flags
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#define hipEventBlockingSync \
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0x1 ///< Waiting will yield CPU. Power-friendly and usage-friendly but may increase latency.
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#define hipEventDisableTiming \
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0x2 ///< Disable event's capability to record timing information. May improve performance.
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#define hipEventInterprocess 0x4 ///< Event can support IPC. @warning - not supported in HIP.
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#define hipEventReleaseToDevice \
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0x40000000 /// < Use a device-scope release when recording this event. This flag is useful to
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/// obtain more precise timings of commands between events. The flag is a no-op on
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/// CUDA platforms.
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#define hipEventReleaseToSystem \
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0x80000000 /// < Use a system-scope release when recording this event. This flag is
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/// useful to make non-coherent host memory visible to the host. The flag is a
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/// no-op on CUDA platforms.
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//Flags that can be used with hipEventCreateWithFlags.
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/** Default flags.*/
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#define hipEventDefault 0x0
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/** Waiting will yield CPU. Power-friendly and usage-friendly but may increase latency.*/
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#define hipEventBlockingSync 0x1
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#define hipDeviceScheduleAuto 0x0 ///< Automatically select between Spin and Yield
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#define hipDeviceScheduleSpin \
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0x1 ///< Dedicate a CPU core to spin-wait. Provides lowest latency, but burns a CPU core and
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///< may consume more power.
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#define hipDeviceScheduleYield \
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0x2 ///< Yield the CPU to the operating system when waiting. May increase latency, but lowers
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///< power and is friendlier to other threads in the system.
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/** Disable event's capability to record timing information. May improve performance.*/
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#define hipEventDisableTiming 0x2
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/** Event can support IPC. Warnig: It is not supported in HIP.*/
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#define hipEventInterprocess 0x4
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/** Use a device-scope release when recording this event. This flag is useful to obtain more
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* precise timings of commands between events. The flag is a no-op on CUDA platforms.*/
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#define hipEventReleaseToDevice 0x40000000
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/** Use a system-scope release when recording this event. This flag is useful to make
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* non-coherent host memory visible to the host. The flag is a no-op on CUDA platforms.*/
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#define hipEventReleaseToSystem 0x80000000
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#define hipDeviceScheduleAuto 0x0
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/** Dedicate a CPU core to spin-wait. Provides lowest latency, but burns a CPU core and may
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* consume more power.*/
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#define hipDeviceScheduleSpin 0x1
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/** Yield the CPU to the operating system when waiting. May increase latency, but lowers power
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* and is friendlier to other threads in the system.*/
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#define hipDeviceScheduleYield 0x2
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#define hipDeviceScheduleBlockingSync 0x4
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#define hipDeviceScheduleMask 0x7
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#define hipDeviceMapHost 0x8
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@ -6,7 +6,7 @@
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#ifndef _EXT_HIPRTC_H
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#define _EXT_HIPRTC_H
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// start: amd_detail/hiprtc.h
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// start: hiprtc.h
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typedef enum hiprtcResult {
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HIPRTC_SUCCESS = 0,
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@ -25,7 +25,7 @@ typedef enum hiprtcResult {
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typedef struct _hiprtcProgram* hiprtcProgram;
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// stop: amd_detail/hiprtc.h
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// stop: hiprtc.h
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#ifdef _WIN32
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#define HIPRTCAPI __stdcall
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