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Optimize update functions in inc_hash_* helper files by testing for pos == 0
This commit is contained in:
parent
ec63c2f017
commit
b626e7f61b
@ -1282,17 +1282,11 @@ DECLSPEC void append_0x80_1x16 (u32x w[16], const u32 offset)
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DECLSPEC void switch_buffer_by_offset_le (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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w0[0] = swap32 (w0[0]);
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@ -1991,17 +1985,11 @@ DECLSPEC void switch_buffer_by_offset_le (u32x w0[4], u32x w1[4], u32x w2[4], u3
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DECLSPEC void switch_buffer_by_offset_carry_le (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x c0[4], u32x c1[4], u32x c2[4], u32x c3[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if defined IS_AMD || defined IS_GENERIC
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w0[0] = swap32 (w0[0]);
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@ -3315,13 +3303,7 @@ DECLSPEC void switch_buffer_by_offset_carry_le (u32x w0[4], u32x w1[4], u32x w2[
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DECLSPEC void switch_buffer_by_offset_be (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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@ -3988,13 +3970,7 @@ DECLSPEC void switch_buffer_by_offset_be (u32x w0[4], u32x w1[4], u32x w2[4], u3
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DECLSPEC void switch_buffer_by_offset_carry_be (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x c0[4], u32x c1[4], u32x c2[4], u32x c3[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -4930,17 +4906,11 @@ DECLSPEC void switch_buffer_by_offset_carry_be (u32x w0[4], u32x w1[4], u32x w2[
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DECLSPEC void switch_buffer_by_offset_8x4_le (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x w4[4], u32x w5[4], u32x w6[4], u32x w7[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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w0[0] = swap32 (w0[0]);
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@ -6742,13 +6712,7 @@ DECLSPEC void switch_buffer_by_offset_8x4_le (u32x w0[4], u32x w1[4], u32x w2[4]
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DECLSPEC void switch_buffer_by_offset_8x4_be (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x w4[4], u32x w5[4], u32x w6[4], u32x w7[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -9076,13 +9040,7 @@ DECLSPEC void switch_buffer_by_offset_8x4_be (u32x w0[4], u32x w1[4], u32x w2[4]
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DECLSPEC void switch_buffer_by_offset_8x4_carry_be (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x w4[4], u32x w5[4], u32x w6[4], u32x w7[4], u32x c0[4], u32x c1[4], u32x c2[4], u32x c3[4], u32x c4[4], u32x c5[4], u32x c6[4], u32x c7[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -12466,17 +12424,11 @@ DECLSPEC void switch_buffer_by_offset_8x4_carry_be (u32x w0[4], u32x w1[4], u32x
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DECLSPEC void switch_buffer_by_offset_1x64_le (u32x w[64], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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@ -21212,13 +21164,7 @@ DECLSPEC void switch_buffer_by_offset_1x64_le (u32x w[64], const u32 offset)
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DECLSPEC void switch_buffer_by_offset_1x64_be (u32x w[64], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -32504,17 +32450,11 @@ DECLSPEC void undo_utf16le_S (const u32 in1[4], const u32 in2[4], u32 out[4])
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DECLSPEC void switch_buffer_by_offset_le_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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w0[0] = swap32_S (w0[0]);
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@ -33212,17 +33152,11 @@ DECLSPEC void switch_buffer_by_offset_le_S (u32 w0[4], u32 w1[4], u32 w2[4], u32
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DECLSPEC void switch_buffer_by_offset_carry_le_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 c0[4], u32 c1[4], u32 c2[4], u32 c3[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if defined IS_AMD || defined IS_GENERIC
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w0[0] = swap32_S (w0[0]);
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@ -34536,13 +34470,7 @@ DECLSPEC void switch_buffer_by_offset_carry_le_S (u32 w0[4], u32 w1[4], u32 w2[4
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DECLSPEC void switch_buffer_by_offset_be_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -35206,13 +35134,7 @@ DECLSPEC void switch_buffer_by_offset_be_S (u32 w0[4], u32 w1[4], u32 w2[4], u32
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DECLSPEC void switch_buffer_by_offset_carry_be_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 c0[4], u32 c1[4], u32 c2[4], u32 c3[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -36148,17 +36070,11 @@ DECLSPEC void switch_buffer_by_offset_carry_be_S (u32 w0[4], u32 w1[4], u32 w2[4
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DECLSPEC void switch_buffer_by_offset_8x4_le_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 w4[4], u32 w5[4], u32 w6[4], u32 w7[4], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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w0[0] = swap32_S (w0[0]);
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@ -37960,13 +37876,7 @@ DECLSPEC void switch_buffer_by_offset_8x4_le_S (u32 w0[4], u32 w1[4], u32 w2[4],
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DECLSPEC void switch_buffer_by_offset_8x4_be_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 w4[4], u32 w5[4], u32 w6[4], u32 w7[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -40294,13 +40204,7 @@ DECLSPEC void switch_buffer_by_offset_8x4_be_S (u32 w0[4], u32 w1[4], u32 w2[4],
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DECLSPEC void switch_buffer_by_offset_8x4_carry_be_S (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 w4[4], u32 w5[4], u32 w6[4], u32 w7[4], u32 c0[4], u32 c1[4], u32 c2[4], u32 c3[4], u32 c4[4], u32 c5[4], u32 c6[4], u32 c7[4], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -43684,17 +43588,11 @@ DECLSPEC void switch_buffer_by_offset_8x4_carry_be_S (u32 w0[4], u32 w1[4], u32
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DECLSPEC void switch_buffer_by_offset_1x64_le_S (u32 w[64], const u32 offset)
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{
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if (offset == 0) return;
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const int offset_mod_4 = offset & 3;
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const int offset_minus_4 = 4 - offset_mod_4;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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@ -52430,13 +52328,7 @@ DECLSPEC void switch_buffer_by_offset_1x64_le_S (u32 w[64], const u32 offset)
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DECLSPEC void switch_buffer_by_offset_1x64_be_S (u32 w[64], const u32 offset)
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{
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if (offset == 0) return;
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#ifdef IS_AMD
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const int offset_switch = offset / 4;
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#else
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const int offset_switch = offset / 4;
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#endif
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#if (defined IS_AMD && AMD_GCN < 3) || defined IS_GENERIC
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switch (offset_switch)
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@ -1,8 +1,8 @@
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// important notes on this:
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// input buf unused bytes needs to be set to zero
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// input buf needs to be in algorithm native byte order (md5 = LE, sha1 = BE, etc)
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// input buf needs to be 64 byte aligned when using md5_update()
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// input buf needs to be in algorithm native byte order (md4 = LE, sha1 = BE, etc)
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// input buf needs to be 64 byte aligned when using md4_update()
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typedef struct md4_ctx
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{
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@ -110,14 +110,55 @@ DECLSPEC void md4_init (md4_ctx_t *ctx)
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DECLSPEC void md4_update_64 (md4_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
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{
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#ifdef IS_AMD
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const int pos = ctx->len & 63;
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#else
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const int pos = ctx->len & 63;
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#endif
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ctx->len += len;
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if (pos == 0)
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{
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if (len < 64)
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{
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ctx->w0[0] = w0[0];
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ctx->w0[1] = w0[1];
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ctx->w0[2] = w0[2];
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ctx->w0[3] = w0[3];
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ctx->w1[0] = w1[0];
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ctx->w1[1] = w1[1];
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ctx->w1[2] = w1[2];
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ctx->w1[3] = w1[3];
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ctx->w2[0] = w2[0];
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ctx->w2[1] = w2[1];
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ctx->w2[2] = w2[2];
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ctx->w2[3] = w2[3];
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ctx->w3[0] = w3[0];
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ctx->w3[1] = w3[1];
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ctx->w3[2] = w3[2];
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ctx->w3[3] = w3[3];
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}
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else
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{
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md4_transform (w0, w1, w2, w3, ctx->h);
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ctx->w0[0] = 0;
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ctx->w0[1] = 0;
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ctx->w0[2] = 0;
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ctx->w0[3] = 0;
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ctx->w1[0] = 0;
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ctx->w1[1] = 0;
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ctx->w1[2] = 0;
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ctx->w1[3] = 0;
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ctx->w2[0] = 0;
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ctx->w2[1] = 0;
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ctx->w2[2] = 0;
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ctx->w2[3] = 0;
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ctx->w3[0] = 0;
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ctx->w3[1] = 0;
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ctx->w3[2] = 0;
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ctx->w3[3] = 0;
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}
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}
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else
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{
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if ((pos + len) < 64)
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{
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switch_buffer_by_offset_le_S (w0, w1, w2, w3, pos);
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@ -185,6 +226,7 @@ DECLSPEC void md4_update_64 (md4_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u3
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ctx->w3[3] = c3[3];
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}
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}
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}
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DECLSPEC void md4_update (md4_ctx_t *ctx, const u32 *w, const int len)
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{
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@ -1234,14 +1276,55 @@ DECLSPEC void md4_init_vector_from_scalar (md4_ctx_vector_t *ctx, md4_ctx_t *ctx
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DECLSPEC void md4_update_vector_64 (md4_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
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{
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#ifdef IS_AMD
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const int pos = ctx->len & 63;
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#else
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const int pos = ctx->len & 63;
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#endif
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ctx->len += len;
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if (pos == 0)
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{
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if (len < 64)
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{
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ctx->w0[0] = w0[0];
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ctx->w0[1] = w0[1];
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ctx->w0[2] = w0[2];
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ctx->w0[3] = w0[3];
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ctx->w1[0] = w1[0];
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ctx->w1[1] = w1[1];
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ctx->w1[2] = w1[2];
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ctx->w1[3] = w1[3];
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ctx->w2[0] = w2[0];
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ctx->w2[1] = w2[1];
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ctx->w2[2] = w2[2];
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ctx->w2[3] = w2[3];
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ctx->w3[0] = w3[0];
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ctx->w3[1] = w3[1];
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ctx->w3[2] = w3[2];
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ctx->w3[3] = w3[3];
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||||
}
|
||||
else
|
||||
{
|
||||
md4_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_le (w0, w1, w2, w3, pos);
|
||||
@ -1309,6 +1392,7 @@ DECLSPEC void md4_update_vector_64 (md4_ctx_vector_t *ctx, u32x w0[4], u32x w1[4
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void md4_update_vector (md4_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -146,14 +146,55 @@ DECLSPEC void md5_init (md5_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void md5_update_64 (md5_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
md5_transform (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_le_S (w0, w1, w2, w3, pos);
|
||||
@ -221,6 +262,7 @@ DECLSPEC void md5_update_64 (md5_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u3
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void md5_update (md5_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -1306,14 +1348,55 @@ DECLSPEC void md5_init_vector_from_scalar (md5_ctx_vector_t *ctx, md5_ctx_t *ctx
|
||||
|
||||
DECLSPEC void md5_update_vector_64 (md5_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
md5_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_le (w0, w1, w2, w3, pos);
|
||||
@ -1381,6 +1464,7 @@ DECLSPEC void md5_update_vector_64 (md5_ctx_vector_t *ctx, u32x w0[4], u32x w1[4
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void md5_update_vector (md5_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -244,14 +244,55 @@ DECLSPEC void ripemd160_init (ripemd160_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void ripemd160_update_64 (ripemd160_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
ripemd160_transform (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_le_S (w0, w1, w2, w3, pos);
|
||||
@ -319,6 +360,7 @@ DECLSPEC void ripemd160_update_64 (ripemd160_ctx_t *ctx, u32 w0[4], u32 w1[4], u
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void ripemd160_update (ripemd160_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -1503,14 +1545,55 @@ DECLSPEC void ripemd160_init_vector_from_scalar (ripemd160_ctx_vector_t *ctx, ri
|
||||
|
||||
DECLSPEC void ripemd160_update_vector_64 (ripemd160_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
ripemd160_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_le (w0, w1, w2, w3, pos);
|
||||
@ -1578,6 +1661,7 @@ DECLSPEC void ripemd160_update_vector_64 (ripemd160_ctx_vector_t *ctx, u32x w0[4
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void ripemd160_update_vector (ripemd160_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -176,14 +176,55 @@ DECLSPEC void sha1_init (sha1_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void sha1_update_64 (sha1_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha1_transform (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be_S (w0, w1, w2, w3, pos);
|
||||
@ -251,6 +292,7 @@ DECLSPEC void sha1_update_64 (sha1_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4],
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha1_update (sha1_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -1603,17 +1645,58 @@ DECLSPEC void sha1_init_vector_from_scalar (sha1_ctx_vector_t *ctx, sha1_ctx_t *
|
||||
|
||||
DECLSPEC void sha1_update_vector_64 (sha1_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha1_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
//switch_buffer_by_offset_be (w0, w1, w2, w3, pos);
|
||||
switch_buffer_by_offset_be (w0, w1, w2, w3, pos);
|
||||
|
||||
ctx->w0[0] |= w0[0];
|
||||
ctx->w0[1] |= w0[1];
|
||||
@ -1639,7 +1722,7 @@ DECLSPEC void sha1_update_vector_64 (sha1_ctx_vector_t *ctx, u32x w0[4], u32x w1
|
||||
u32x c2[4] = { 0 };
|
||||
u32x c3[4] = { 0 };
|
||||
|
||||
//switch_buffer_by_offset_carry_be (w0, w1, w2, w3, c0, c1, c2, c3, pos);
|
||||
switch_buffer_by_offset_carry_be (w0, w1, w2, w3, c0, c1, c2, c3, pos);
|
||||
|
||||
ctx->w0[0] |= w0[0];
|
||||
ctx->w0[1] |= w0[1];
|
||||
@ -1678,6 +1761,7 @@ DECLSPEC void sha1_update_vector_64 (sha1_ctx_vector_t *ctx, u32x w0[4], u32x w1
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha1_update_vector (sha1_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -161,14 +161,55 @@ DECLSPEC void sha224_init (sha224_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void sha224_update_64 (sha224_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha224_transform (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be_S (w0, w1, w2, w3, pos);
|
||||
@ -236,6 +277,7 @@ DECLSPEC void sha224_update_64 (sha224_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha224_update (sha224_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -1320,14 +1362,55 @@ DECLSPEC void sha224_init_vector_from_scalar (sha224_ctx_vector_t *ctx, sha224_c
|
||||
|
||||
DECLSPEC void sha224_update_vector_64 (sha224_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha224_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be (w0, w1, w2, w3, pos);
|
||||
@ -1395,6 +1478,7 @@ DECLSPEC void sha224_update_vector_64 (sha224_ctx_vector_t *ctx, u32x w0[4], u32
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha224_update_vector (sha224_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -161,14 +161,55 @@ DECLSPEC void sha256_init (sha256_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void sha256_update_64 (sha256_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha256_transform (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be_S (w0, w1, w2, w3, pos);
|
||||
@ -236,6 +277,7 @@ DECLSPEC void sha256_update_64 (sha256_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha256_update (sha256_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -1320,14 +1362,55 @@ DECLSPEC void sha256_init_vector_from_scalar (sha256_ctx_vector_t *ctx, sha256_c
|
||||
|
||||
DECLSPEC void sha256_update_vector_64 (sha256_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha256_transform_vector (w0, w1, w2, w3, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be (w0, w1, w2, w3, pos);
|
||||
@ -1395,6 +1478,7 @@ DECLSPEC void sha256_update_vector_64 (sha256_ctx_vector_t *ctx, u32x w0[4], u32
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha256_update_vector (sha256_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -185,14 +185,87 @@ DECLSPEC void sha384_init (sha384_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void sha384_update_128 (sha384_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 w4[4], u32 w5[4], u32 w6[4], u32 w7[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 127;
|
||||
#else
|
||||
const int pos = ctx->len & 127;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 128)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
ctx->w4[0] = w4[0];
|
||||
ctx->w4[1] = w4[1];
|
||||
ctx->w4[2] = w4[2];
|
||||
ctx->w4[3] = w4[3];
|
||||
ctx->w5[0] = w5[0];
|
||||
ctx->w5[1] = w5[1];
|
||||
ctx->w5[2] = w5[2];
|
||||
ctx->w5[3] = w5[3];
|
||||
ctx->w6[0] = w6[0];
|
||||
ctx->w6[1] = w6[1];
|
||||
ctx->w6[2] = w6[2];
|
||||
ctx->w6[3] = w6[3];
|
||||
ctx->w7[0] = w7[0];
|
||||
ctx->w7[1] = w7[1];
|
||||
ctx->w7[2] = w7[2];
|
||||
ctx->w7[3] = w7[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha384_transform (w0, w1, w2, w3, w4, w5, w6, w7, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
ctx->w4[0] = 0;
|
||||
ctx->w4[1] = 0;
|
||||
ctx->w4[2] = 0;
|
||||
ctx->w4[3] = 0;
|
||||
ctx->w5[0] = 0;
|
||||
ctx->w5[1] = 0;
|
||||
ctx->w5[2] = 0;
|
||||
ctx->w5[3] = 0;
|
||||
ctx->w6[0] = 0;
|
||||
ctx->w6[1] = 0;
|
||||
ctx->w6[2] = 0;
|
||||
ctx->w6[3] = 0;
|
||||
ctx->w7[0] = 0;
|
||||
ctx->w7[1] = 0;
|
||||
ctx->w7[2] = 0;
|
||||
ctx->w7[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 128)
|
||||
{
|
||||
switch_buffer_by_offset_8x4_be_S (w0, w1, w2, w3, w4, w5, w6, w7, pos);
|
||||
@ -312,6 +385,7 @@ DECLSPEC void sha384_update_128 (sha384_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2
|
||||
ctx->w7[3] = c7[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha384_update (sha384_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -2016,14 +2090,87 @@ DECLSPEC void sha384_init_vector_from_scalar (sha384_ctx_vector_t *ctx, sha384_c
|
||||
|
||||
DECLSPEC void sha384_update_vector_128 (sha384_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x w4[4], u32x w5[4], u32x w6[4], u32x w7[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 127;
|
||||
#else
|
||||
const int pos = ctx->len & 127;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 128)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
ctx->w4[0] = w4[0];
|
||||
ctx->w4[1] = w4[1];
|
||||
ctx->w4[2] = w4[2];
|
||||
ctx->w4[3] = w4[3];
|
||||
ctx->w5[0] = w5[0];
|
||||
ctx->w5[1] = w5[1];
|
||||
ctx->w5[2] = w5[2];
|
||||
ctx->w5[3] = w5[3];
|
||||
ctx->w6[0] = w6[0];
|
||||
ctx->w6[1] = w6[1];
|
||||
ctx->w6[2] = w6[2];
|
||||
ctx->w6[3] = w6[3];
|
||||
ctx->w7[0] = w7[0];
|
||||
ctx->w7[1] = w7[1];
|
||||
ctx->w7[2] = w7[2];
|
||||
ctx->w7[3] = w7[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha384_transform_vector (w0, w1, w2, w3, w4, w5, w6, w7, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
ctx->w4[0] = 0;
|
||||
ctx->w4[1] = 0;
|
||||
ctx->w4[2] = 0;
|
||||
ctx->w4[3] = 0;
|
||||
ctx->w5[0] = 0;
|
||||
ctx->w5[1] = 0;
|
||||
ctx->w5[2] = 0;
|
||||
ctx->w5[3] = 0;
|
||||
ctx->w6[0] = 0;
|
||||
ctx->w6[1] = 0;
|
||||
ctx->w6[2] = 0;
|
||||
ctx->w6[3] = 0;
|
||||
ctx->w7[0] = 0;
|
||||
ctx->w7[1] = 0;
|
||||
ctx->w7[2] = 0;
|
||||
ctx->w7[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 128)
|
||||
{
|
||||
switch_buffer_by_offset_8x4_be (w0, w1, w2, w3, w4, w5, w6, w7, pos);
|
||||
@ -2143,6 +2290,7 @@ DECLSPEC void sha384_update_vector_128 (sha384_ctx_vector_t *ctx, u32x w0[4], u3
|
||||
ctx->w7[3] = c7[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha384_update_vector (sha384_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -185,14 +185,87 @@ DECLSPEC void sha512_init (sha512_ctx_t *ctx)
|
||||
|
||||
DECLSPEC void sha512_update_128 (sha512_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], u32 w4[4], u32 w5[4], u32 w6[4], u32 w7[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 127;
|
||||
#else
|
||||
const int pos = ctx->len & 127;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 128)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
ctx->w4[0] = w4[0];
|
||||
ctx->w4[1] = w4[1];
|
||||
ctx->w4[2] = w4[2];
|
||||
ctx->w4[3] = w4[3];
|
||||
ctx->w5[0] = w5[0];
|
||||
ctx->w5[1] = w5[1];
|
||||
ctx->w5[2] = w5[2];
|
||||
ctx->w5[3] = w5[3];
|
||||
ctx->w6[0] = w6[0];
|
||||
ctx->w6[1] = w6[1];
|
||||
ctx->w6[2] = w6[2];
|
||||
ctx->w6[3] = w6[3];
|
||||
ctx->w7[0] = w7[0];
|
||||
ctx->w7[1] = w7[1];
|
||||
ctx->w7[2] = w7[2];
|
||||
ctx->w7[3] = w7[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha512_transform (w0, w1, w2, w3, w4, w5, w6, w7, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
ctx->w4[0] = 0;
|
||||
ctx->w4[1] = 0;
|
||||
ctx->w4[2] = 0;
|
||||
ctx->w4[3] = 0;
|
||||
ctx->w5[0] = 0;
|
||||
ctx->w5[1] = 0;
|
||||
ctx->w5[2] = 0;
|
||||
ctx->w5[3] = 0;
|
||||
ctx->w6[0] = 0;
|
||||
ctx->w6[1] = 0;
|
||||
ctx->w6[2] = 0;
|
||||
ctx->w6[3] = 0;
|
||||
ctx->w7[0] = 0;
|
||||
ctx->w7[1] = 0;
|
||||
ctx->w7[2] = 0;
|
||||
ctx->w7[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 128)
|
||||
{
|
||||
switch_buffer_by_offset_8x4_be_S (w0, w1, w2, w3, w4, w5, w6, w7, pos);
|
||||
@ -312,6 +385,7 @@ DECLSPEC void sha512_update_128 (sha512_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2
|
||||
ctx->w7[3] = c7[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha512_update (sha512_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -2016,14 +2090,87 @@ DECLSPEC void sha512_init_vector_from_scalar (sha512_ctx_vector_t *ctx, sha512_c
|
||||
|
||||
DECLSPEC void sha512_update_vector_128 (sha512_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x w4[4], u32x w5[4], u32x w6[4], u32x w7[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 127;
|
||||
#else
|
||||
const int pos = ctx->len & 127;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 128)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
ctx->w4[0] = w4[0];
|
||||
ctx->w4[1] = w4[1];
|
||||
ctx->w4[2] = w4[2];
|
||||
ctx->w4[3] = w4[3];
|
||||
ctx->w5[0] = w5[0];
|
||||
ctx->w5[1] = w5[1];
|
||||
ctx->w5[2] = w5[2];
|
||||
ctx->w5[3] = w5[3];
|
||||
ctx->w6[0] = w6[0];
|
||||
ctx->w6[1] = w6[1];
|
||||
ctx->w6[2] = w6[2];
|
||||
ctx->w6[3] = w6[3];
|
||||
ctx->w7[0] = w7[0];
|
||||
ctx->w7[1] = w7[1];
|
||||
ctx->w7[2] = w7[2];
|
||||
ctx->w7[3] = w7[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
sha512_transform_vector (w0, w1, w2, w3, w4, w5, w6, w7, ctx->h);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
ctx->w4[0] = 0;
|
||||
ctx->w4[1] = 0;
|
||||
ctx->w4[2] = 0;
|
||||
ctx->w4[3] = 0;
|
||||
ctx->w5[0] = 0;
|
||||
ctx->w5[1] = 0;
|
||||
ctx->w5[2] = 0;
|
||||
ctx->w5[3] = 0;
|
||||
ctx->w6[0] = 0;
|
||||
ctx->w6[1] = 0;
|
||||
ctx->w6[2] = 0;
|
||||
ctx->w6[3] = 0;
|
||||
ctx->w7[0] = 0;
|
||||
ctx->w7[1] = 0;
|
||||
ctx->w7[2] = 0;
|
||||
ctx->w7[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 128)
|
||||
{
|
||||
switch_buffer_by_offset_8x4_be (w0, w1, w2, w3, w4, w5, w6, w7, pos);
|
||||
@ -2143,6 +2290,7 @@ DECLSPEC void sha512_update_vector_128 (sha512_ctx_vector_t *ctx, u32x w0[4], u3
|
||||
ctx->w7[3] = c7[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void sha512_update_vector (sha512_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
@ -1344,14 +1344,55 @@ DECLSPEC void whirlpool_init (whirlpool_ctx_t *ctx, SHM_TYPE u32 (*s_Ch)[256], S
|
||||
|
||||
DECLSPEC void whirlpool_update_64 (whirlpool_ctx_t *ctx, u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
whirlpool_transform (w0, w1, w2, w3, ctx->h, ctx->s_Ch, ctx->s_Cl);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be_S (w0, w1, w2, w3, pos);
|
||||
@ -1419,6 +1460,7 @@ DECLSPEC void whirlpool_update_64 (whirlpool_ctx_t *ctx, u32 w0[4], u32 w1[4], u
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void whirlpool_update (whirlpool_ctx_t *ctx, const u32 *w, const int len)
|
||||
{
|
||||
@ -2607,14 +2649,55 @@ DECLSPEC void whirlpool_init_vector_from_scalar (whirlpool_ctx_vector_t *ctx, wh
|
||||
|
||||
DECLSPEC void whirlpool_update_vector_64 (whirlpool_ctx_vector_t *ctx, u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], const int len)
|
||||
{
|
||||
#ifdef IS_AMD
|
||||
const int pos = ctx->len & 63;
|
||||
#else
|
||||
const int pos = ctx->len & 63;
|
||||
#endif
|
||||
|
||||
ctx->len += len;
|
||||
|
||||
if (pos == 0)
|
||||
{
|
||||
if (len < 64)
|
||||
{
|
||||
ctx->w0[0] = w0[0];
|
||||
ctx->w0[1] = w0[1];
|
||||
ctx->w0[2] = w0[2];
|
||||
ctx->w0[3] = w0[3];
|
||||
ctx->w1[0] = w1[0];
|
||||
ctx->w1[1] = w1[1];
|
||||
ctx->w1[2] = w1[2];
|
||||
ctx->w1[3] = w1[3];
|
||||
ctx->w2[0] = w2[0];
|
||||
ctx->w2[1] = w2[1];
|
||||
ctx->w2[2] = w2[2];
|
||||
ctx->w2[3] = w2[3];
|
||||
ctx->w3[0] = w3[0];
|
||||
ctx->w3[1] = w3[1];
|
||||
ctx->w3[2] = w3[2];
|
||||
ctx->w3[3] = w3[3];
|
||||
}
|
||||
else
|
||||
{
|
||||
whirlpool_transform_vector (w0, w1, w2, w3, ctx->h, ctx->s_Ch, ctx->s_Cl);
|
||||
|
||||
ctx->w0[0] = 0;
|
||||
ctx->w0[1] = 0;
|
||||
ctx->w0[2] = 0;
|
||||
ctx->w0[3] = 0;
|
||||
ctx->w1[0] = 0;
|
||||
ctx->w1[1] = 0;
|
||||
ctx->w1[2] = 0;
|
||||
ctx->w1[3] = 0;
|
||||
ctx->w2[0] = 0;
|
||||
ctx->w2[1] = 0;
|
||||
ctx->w2[2] = 0;
|
||||
ctx->w2[3] = 0;
|
||||
ctx->w3[0] = 0;
|
||||
ctx->w3[1] = 0;
|
||||
ctx->w3[2] = 0;
|
||||
ctx->w3[3] = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((pos + len) < 64)
|
||||
{
|
||||
switch_buffer_by_offset_be (w0, w1, w2, w3, pos);
|
||||
@ -2682,6 +2765,7 @@ DECLSPEC void whirlpool_update_vector_64 (whirlpool_ctx_vector_t *ctx, u32x w0[4
|
||||
ctx->w3[3] = c3[3];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLSPEC void whirlpool_update_vector (whirlpool_ctx_vector_t *ctx, const u32x *w, const int len)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user