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Slightly increase blowfish based algorithms for NV
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747c4a8d6a
commit
6c22de104e
@ -294,11 +294,12 @@ __constant u32 c_sbox3[256] =
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0xb74e6132, 0xce77e25b, 0x578fdfe3, 0x3ac372e6
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};
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#ifdef IS_AMD
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#define BF_ROUND(L,R,N) \
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{ \
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uchar4 c = as_uchar4 ((L)); \
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\
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u32 tmp; \
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u32 tmp; \
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\
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tmp = S0[c.s3]; \
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tmp += S1[c.s2]; \
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@ -307,6 +308,21 @@ __constant u32 c_sbox3[256] =
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\
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(R) ^= tmp ^ P[(N)]; \
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}
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#endif
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#ifdef IS_NV
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#define BF_ROUND(L,R,N) \
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{ \
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u32 tmp; \
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\
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tmp = S0[__bfe ((L), 24, 8)]; \
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tmp += S1[__bfe ((L), 16, 8)]; \
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tmp ^= S2[__bfe ((L), 8, 8)]; \
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tmp += S3[__bfe ((L), 0, 8)]; \
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\
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(R) ^= tmp ^ P[(N)]; \
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}
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#endif
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#define BF_ENCRYPT(L,R) \
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{ \
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@ -294,7 +294,6 @@ __constant u32 c_sbox3[256] =
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0xb74e6132, 0xce77e25b, 0x578fdfe3, 0x3ac372e6
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};
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#ifdef IS_AMD
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#define BF_ROUND(L,R,N) \
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{ \
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@ -316,10 +315,10 @@ __constant u32 c_sbox3[256] =
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{ \
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u32 tmp; \
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\
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tmp = S0[((L) >> 24) & 0xff]; \
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tmp += S1[((L) >> 16) & 0xff]; \
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tmp ^= S2[((L) >> 8) & 0xff]; \
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tmp += S3[((L) >> 0) & 0xff]; \
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tmp = S0[__bfe ((L), 24, 8)]; \
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tmp += S1[__bfe ((L), 16, 8)]; \
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tmp ^= S2[__bfe ((L), 8, 8)]; \
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tmp += S3[__bfe ((L), 0, 8)]; \
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\
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(R) ^= tmp ^ P[(N)]; \
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}
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@ -22,15 +22,25 @@ static inline u64 swap64 (const u64 v)
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#endif
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#ifdef IS_NV
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static inline u32 __byte_perm (const u32 a, const u32 b, const u32 s)
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static inline u32 __byte_perm (const u32 a, const u32 b, const u32 c)
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{
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u32 r;
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asm ("prmt.b32 %0, %1, %2, %3;" : "=r"(r) : "r"(a), "r"(b), "r"(s));
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asm ("prmt.b32 %0, %1, %2, %3;" : "=r"(r) : "r"(a), "r"(b), "r"(c));
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return r;
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}
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static inline u32 __bfe (const u32 a, const u32 b, const u32 c)
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{
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u32 r;
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asm ("bfe.u32 %0, %1, %2, %3;" : "=r"(r) : "r"(a), "r"(b), "r"(c));
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return r;
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}
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#if CUDA_ARCH >= 350
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static inline u32 amd_bytealign (const u32 a, const u32 b, const u32 c)
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