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Add VEGA specific inline assembly to improve all MD4, MD5, SHA1 and SHA256 based kernels
This commit is contained in:
parent
7cebc936fd
commit
00e38cc2c6
@ -34,23 +34,23 @@
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#define MD4_STEP_S(f,a,b,c,d,x,K,s) \
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#define MD4_STEP_S(f,a,b,c,d,x,K,s) \
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{ \
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{ \
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a += K; \
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a += K; \
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a += x; \
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const u32 t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3_S (a, x, t); \
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a = rotl32_S (a, s); \
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a = rotl32_S (a, s); \
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}
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}
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#define MD4_STEP(f,a,b,c,d,x,K,s) \
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#define MD4_STEP(f,a,b,c,d,x,K,s) \
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{ \
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{ \
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a += K; \
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a += K; \
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a += x; \
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const u32x t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3 (a, x, t); \
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a = rotl32 (a, s); \
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a = rotl32 (a, s); \
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}
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}
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#define MD4_STEP0(f,a,b,c,d,K,s) \
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#define MD4_STEP0(f,a,b,c,d,K,s) \
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{ \
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{ \
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a += K; \
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const u32x t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3 (a, K, t); \
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a = rotl32 (a, s); \
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a = rotl32 (a, s); \
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}
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}
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@ -72,7 +72,7 @@
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#define MD5_F(x,y,z) ((z) ^ ((x) & ((y) ^ (z))))
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#define MD5_F(x,y,z) ((z) ^ ((x) & ((y) ^ (z))))
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#define MD5_G(x,y,z) ((y) ^ ((z) & ((x) ^ (y))))
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#define MD5_G(x,y,z) ((y) ^ ((z) & ((x) ^ (y))))
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#define MD5_H(x,y,z) ((x) ^ (y) ^ (z))
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#define MD5_H(x,y,z) ((x) ^ (y) ^ (z))
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#define MD5_I(x,y,z) (bitselect (0xffffffffU, (x), (z)) ^ (y))
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#define MD5_I(x,y,z) ((y) ^ ((x) | ~(z)))
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#define MD5_Fo(x,y,z) (bitselect ((z), (y), (x)))
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#define MD5_Fo(x,y,z) (bitselect ((z), (y), (x)))
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#define MD5_Go(x,y,z) (bitselect ((y), (x), (z)))
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#define MD5_Go(x,y,z) (bitselect ((y), (x), (z)))
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#endif
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#endif
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@ -89,8 +89,8 @@
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#define MD5_STEP_S(f,a,b,c,d,x,K,s) \
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#define MD5_STEP_S(f,a,b,c,d,x,K,s) \
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{ \
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{ \
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a += K; \
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a += K; \
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a += x; \
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const u32 t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3_S (a, x, t); \
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a = rotl32_S (a, s); \
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a = rotl32_S (a, s); \
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a += b; \
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a += b; \
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}
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}
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@ -98,16 +98,16 @@
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#define MD5_STEP(f,a,b,c,d,x,K,s) \
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#define MD5_STEP(f,a,b,c,d,x,K,s) \
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{ \
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{ \
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a += K; \
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a += K; \
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a += x; \
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const u32x t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3 (a, x, t); \
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a = rotl32 (a, s); \
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a = rotl32 (a, s); \
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a += b; \
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a += b; \
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}
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}
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#define MD5_STEP0(f,a,b,c,d,K,s) \
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#define MD5_STEP0(f,a,b,c,d,K,s) \
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{ \
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{ \
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a += K; \
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const u32x t = f (b, c, d); \
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a += f (b, c, d); \
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a = __add3 (a, K, t); \
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a = rotl32 (a, s); \
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a = rotl32 (a, s); \
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a += b; \
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a += b; \
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}
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}
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@ -139,8 +139,8 @@
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#define SHA1_STEP_S(f,a,b,c,d,e,x) \
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#define SHA1_STEP_S(f,a,b,c,d,e,x) \
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{ \
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{ \
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e += K; \
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e += K; \
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e += x; \
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const u32 t = f (b, c, d); \
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e += f (b, c, d); \
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e = __add3_S (e, x, t); \
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e += rotl32_S (a, 5u); \
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e += rotl32_S (a, 5u); \
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b = rotl32_S (b, 30u); \
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b = rotl32_S (b, 30u); \
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}
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}
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@ -148,24 +148,24 @@
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#define SHA1_STEP(f,a,b,c,d,e,x) \
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#define SHA1_STEP(f,a,b,c,d,e,x) \
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{ \
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{ \
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e += K; \
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e += K; \
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e += x; \
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const u32x t = f (b, c, d); \
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e += f (b, c, d); \
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e = __add3 (e, x, t); \
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e += rotl32 (a, 5u); \
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e += rotl32 (a, 5u); \
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b = rotl32 (b, 30u); \
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b = rotl32 (b, 30u); \
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}
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}
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#define SHA1_STEP0(f,a,b,c,d,e,x) \
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#define SHA1_STEP0(f,a,b,c,d,e,x) \
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{ \
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{ \
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e += K; \
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const u32x t = f (b, c, d); \
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e += f (b, c, d); \
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e = __add3 (e, K, t); \
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e += rotl32 (a, 5u); \
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e += rotl32 (a, 5u); \
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b = rotl32 (b, 30u); \
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b = rotl32 (b, 30u); \
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}
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}
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#define SHA1_STEPX(f,a,b,c,d,e,x) \
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#define SHA1_STEPX(f,a,b,c,d,e,x) \
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{ \
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{ \
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e += x; \
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const u32x t = f (b, c, d); \
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e += f (b, c, d); \
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e = __add3 (e, x, t); \
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e += rotl32 (a, 5u); \
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e += rotl32 (a, 5u); \
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b = rotl32 (b, 30u); \
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b = rotl32 (b, 30u); \
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}
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}
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@ -218,26 +218,28 @@
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#define SHA256_STEP_S(F0,F1,a,b,c,d,e,f,g,h,x,K) \
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#define SHA256_STEP_S(F0,F1,a,b,c,d,e,f,g,h,x,K) \
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{ \
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{ \
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h += K; \
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const u32 t1 = SHA256_S3_S (e); \
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h += x; \
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const u32 t2 = F1 (e,f,g); \
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h += SHA256_S3_S (e); \
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h = __add3_S (h, K, x); \
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h += F1 (e,f,g); \
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h = __add3_S (h, t1, t2); \
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d += h; \
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d += h; \
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h += SHA256_S2_S (a); \
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const u32 t3 = SHA256_S2_S (a); \
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h += F0 (a,b,c); \
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const u32 t4 = F0 (a,b,c); \
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h = __add3_S (h, t3, t4); \
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}
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}
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#define SHA256_EXPAND_S(x,y,z,w) (SHA256_S1_S (x) + y + SHA256_S0_S (z) + w)
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#define SHA256_EXPAND_S(x,y,z,w) (SHA256_S1_S (x) + y + SHA256_S0_S (z) + w)
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#define SHA256_STEP(F0,F1,a,b,c,d,e,f,g,h,x,K) \
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#define SHA256_STEP(F0,F1,a,b,c,d,e,f,g,h,x,K) \
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{ \
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{ \
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h += K; \
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const u32 t1 = SHA256_S3 (e); \
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h += x; \
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const u32 t2 = F1 (e,f,g); \
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h += SHA256_S3 (e); \
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h = __add3 (h, K, x); \
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h += F1 (e,f,g); \
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h = __add3 (h, t1, t2); \
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d += h; \
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d += h; \
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h += SHA256_S2 (a); \
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const u32 t3 = SHA256_S2 (a); \
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h += F0 (a,b,c); \
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const u32 t4 = F0 (a,b,c); \
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h = __add3 (h, t3, t4); \
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}
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}
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#define SHA256_EXPAND(x,y,z,w) (SHA256_S1 (x) + y + SHA256_S0 (z) + w)
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#define SHA256_EXPAND(x,y,z,w) (SHA256_S1 (x) + y + SHA256_S0 (z) + w)
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@ -339,6 +339,82 @@ static u32 __byte_perm_S (const u32 a, const u32 b, const u32 c)
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}
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}
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#endif
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#endif
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#ifdef IS_AMD_ROCM_VEGA
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static u32x __add3 (const u32x a, const u32x b, const u32x c)
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{
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u32x r;
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#if VECT_SIZE == 1
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r) : "v"(b), "v"(a), "v"(c));
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#endif
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#if VECT_SIZE >= 2
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s0) : "v"(b.s0), "v"(a.s0), "v"(c.s0));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s1) : "v"(b.s1), "v"(a.s1), "v"(c.s1));
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#endif
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#if VECT_SIZE >= 4
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s0) : "v"(b.s0), "v"(a.s0), "v"(c.s0));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s1) : "v"(b.s1), "v"(a.s1), "v"(c.s1));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s2) : "v"(b.s2), "v"(a.s2), "v"(c.s2));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s3) : "v"(b.s3), "v"(a.s3), "v"(c.s3));
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#endif
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#if VECT_SIZE >= 8
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s0) : "v"(b.s0), "v"(a.s0), "v"(c.s0));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s1) : "v"(b.s1), "v"(a.s1), "v"(c.s1));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s2) : "v"(b.s2), "v"(a.s2), "v"(c.s2));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s3) : "v"(b.s3), "v"(a.s3), "v"(c.s3));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s4) : "v"(b.s4), "v"(a.s4), "v"(c.s4));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s5) : "v"(b.s5), "v"(a.s5), "v"(c.s5));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s6) : "v"(b.s6), "v"(a.s6), "v"(c.s6));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s7) : "v"(b.s7), "v"(a.s7), "v"(c.s7));
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#endif
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#if VECT_SIZE >= 16
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s0) : "v"(b.s0), "v"(a.s0), "v"(c.s0));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s1) : "v"(b.s1), "v"(a.s1), "v"(c.s1));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s2) : "v"(b.s2), "v"(a.s2), "v"(c.s2));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s3) : "v"(b.s3), "v"(a.s3), "v"(c.s3));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s4) : "v"(b.s4), "v"(a.s4), "v"(c.s4));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s5) : "v"(b.s5), "v"(a.s5), "v"(c.s5));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s6) : "v"(b.s6), "v"(a.s6), "v"(c.s6));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s7) : "v"(b.s7), "v"(a.s7), "v"(c.s7));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s8) : "v"(b.s8), "v"(a.s8), "v"(c.s8));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.s9) : "v"(b.s9), "v"(a.s9), "v"(c.s9));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.sa) : "v"(b.sa), "v"(a.sa), "v"(c.sa));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.sb) : "v"(b.sb), "v"(a.sb), "v"(c.sb));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.sc) : "v"(b.sc), "v"(a.sc), "v"(c.sc));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.sd) : "v"(b.sd), "v"(a.sd), "v"(c.sd));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.se) : "v"(b.se), "v"(a.se), "v"(c.se));
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r.sf) : "v"(b.sf), "v"(a.sf), "v"(c.sf));
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#endif
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return r;
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}
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#else
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static u32x __add3 (const u32x a, const u32x b, const u32x c)
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{
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return a + b + c;
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}
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#endif
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#ifdef IS_AMD_ROCM_VEGA
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static u32 __add3_S (const u32 a, const u32 b, const u32 c)
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{
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u32 r;
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__asm__ volatile ("V_ADD3_U32 %0, %1, %2, %3;" : "=v"(r) : "v"(b), "v"(a), "v"(c));
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return r;
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}
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#else
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static u32 __add3_S (const u32 a, const u32 b, const u32 c)
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{
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return a + b + c;
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}
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#endif
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#endif
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#endif
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#ifdef IS_NV
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#ifdef IS_NV
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@ -571,6 +647,17 @@ static u32 amd_bytealign_S (const u32 a, const u32 b, const u32 c)
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return r;
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return r;
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}
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}
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static u32x __add3 (const u32x a, const u32x b, const u32x c)
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{
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return a + b + c;
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}
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static u32 __add3_S (const u32 a, const u32 b, const u32 c)
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{
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return a + b + c;
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}
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#endif
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#endif
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#ifdef IS_GENERIC
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#ifdef IS_GENERIC
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@ -710,6 +797,16 @@ static u32 amd_bytealign_S (const u32 a, const u32 b, const u32 c)
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return (u32) (tmp);
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return (u32) (tmp);
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}
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}
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static u32x __add3 (const u32x a, const u32x b, const u32x c)
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{
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return a + b + c;
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}
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static u32 __add3_S (const u32 a, const u32 b, const u32 c)
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{
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return a + b + c;
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}
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#endif
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#endif
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||||||
|
|
||||||
typedef struct digest
|
typedef struct digest
|
||||||
|
@ -36,6 +36,9 @@
|
|||||||
#else
|
#else
|
||||||
#define IS_AMD
|
#define IS_AMD
|
||||||
#define IS_AMD_ROCM
|
#define IS_AMD_ROCM
|
||||||
|
#if defined __gfx900__ || defined __gfx901__ || defined __gfx902__ || defined __gfx903__
|
||||||
|
#define IS_AMD_ROCM_VEGA
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
#elif VENDOR_ID == (1 << 1)
|
#elif VENDOR_ID == (1 << 1)
|
||||||
#define IS_APPLE
|
#define IS_APPLE
|
||||||
|
Loading…
Reference in New Issue
Block a user