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hashcat/OpenCL/m01100_a0.cl

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21 KiB
Common Lisp
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Initial commit
2015-12-04 14:47:52 +00:00
/**
* Author......: Jens Steube <jens.steube@gmail.com>
* License.....: MIT
*/
#define _MD4_
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
#define NEW_SIMD_CODE
Initial commit
2015-12-04 14:47:52 +00:00
#include "include/constants.h"
#include "include/kernel_vendor.h"
#define DGST_R0 0
#define DGST_R1 3
#define DGST_R2 2
#define DGST_R3 1
#include "include/kernel_functions.c"
Fix path to includes
2016-01-03 00:48:05 +00:00
#include "OpenCL/types_ocl.c"
#include "OpenCL/common.c"
Replace the substring GPU to a more appropriate "device" or "kernel" substring depending on the context
2016-01-05 07:26:44 +00:00
#include "include/rp_kernel.h"
Fix path to includes
2016-01-03 00:56:41 +00:00
#include "OpenCL/rp.c"
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
#include "OpenCL/simd.c"
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_m04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* modifier
*/
const u32 lid = get_local_id (0);
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 11:04:22 +00:00
u32 pw_buf0[4];
u32 pw_buf1[4];
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
pw_buf0[0] = pws[gid].i[0];
pw_buf0[1] = pws[gid].i[1];
pw_buf0[2] = pws[gid].i[2];
pw_buf0[3] = pws[gid].i[3];
pw_buf1[0] = pws[gid].i[4];
pw_buf1[1] = pws[gid].i[5];
pw_buf1[2] = pws[gid].i[6];
pw_buf1[3] = pws[gid].i[7];
Initial commit
2015-12-04 14:47:52 +00:00
const u32 pw_len = pws[gid].pw_len;
/**
* salt
*/
Use real registers for salt, high-end maxwells didn't like it with global memory access
2016-05-09 21:07:23 +00:00
const u32 salt_buf0 = salt_bufs[salt_pos].salt_buf[0];
const u32 salt_buf1 = salt_bufs[salt_pos].salt_buf[1];
const u32 salt_buf2 = salt_bufs[salt_pos].salt_buf[2];
const u32 salt_buf3 = salt_bufs[salt_pos].salt_buf[3];
const u32 salt_buf4 = salt_bufs[salt_pos].salt_buf[4];
const u32 salt_buf5 = salt_bufs[salt_pos].salt_buf[5];
const u32 salt_buf6 = salt_bufs[salt_pos].salt_buf[6];
const u32 salt_buf7 = salt_bufs[salt_pos].salt_buf[7];
const u32 salt_buf8 = salt_bufs[salt_pos].salt_buf[8];
const u32 salt_buf9 = salt_bufs[salt_pos].salt_buf[9];
const u32 salt_len = salt_bufs[salt_pos].salt_len;
Initial commit
2015-12-04 14:47:52 +00:00
/**
* loop
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 14:47:52 +00:00
{
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
u32x w0[4] = { 0 };
u32x w1[4] = { 0 };
u32x w2[4] = { 0 };
u32x w3[4] = { 0 };
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
const u32x out_len = apply_rules_vect (pw_buf0, pw_buf1, pw_len, rules_buf, il_pos, w0, w1);
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
append_0x80_2x4_VV (w0, w1, out_len);
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
make_unicode (w1, w2, w3);
make_unicode (w0, w0, w1);
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w3[2] = out_len * 2 * 8;
w3[3] = 0;
Initial commit
2015-12-04 14:47:52 +00:00
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
u32x a = MD4M_A;
u32x b = MD4M_B;
u32x c = MD4M_C;
u32x d = MD4M_D;
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
MD4_STEP (MD4_Fo, a, b, c, d, w0[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w0[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w0[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w0[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w1[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w1[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w1[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w1[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w2[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w2[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w2[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w2[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w3[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w3[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w3[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w3[3], MD4C00, MD4S03);
MD4_STEP (MD4_Go, a, b, c, d, w0[0], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[0], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[0], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[0], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[1], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[1], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[1], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[1], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[2], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[2], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[2], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[2], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[3], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[3], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[3], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[3], MD4C01, MD4S13);
MD4_STEP (MD4_H , a, b, c, d, w0[0], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[0], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[0], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[0], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[2], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[2], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[2], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[2], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[1], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[1], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[1], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[1], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[3], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[3], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[3], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[3], MD4C02, MD4S23);
Initial commit
2015-12-04 14:47:52 +00:00
a += MD4M_A;
b += MD4M_B;
c += MD4M_C;
d += MD4M_D;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w0[0] = a;
w0[1] = b;
w0[2] = c;
w0[3] = d;
Use real registers for salt, high-end maxwells didn't like it with global memory access
2016-05-09 21:07:23 +00:00
w1[0] = salt_buf0;
w1[1] = salt_buf1;
w1[2] = salt_buf2;
w1[3] = salt_buf3;
w2[0] = salt_buf4;
w2[1] = salt_buf5;
w2[2] = salt_buf6;
w2[3] = salt_buf7;
w3[0] = salt_buf8;
w3[1] = salt_buf9;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w3[2] = (16 + salt_len) * 8;
w3[3] = 0;
Initial commit
2015-12-04 14:47:52 +00:00
a = MD4M_A;
b = MD4M_B;
c = MD4M_C;
d = MD4M_D;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
MD4_STEP (MD4_Fo, a, b, c, d, w0[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w0[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w0[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w0[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w1[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w1[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w1[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w1[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w2[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w2[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w2[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w2[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w3[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w3[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w3[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w3[3], MD4C00, MD4S03);
MD4_STEP (MD4_Go, a, b, c, d, w0[0], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[0], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[0], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[0], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[1], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[1], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[1], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[1], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[2], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[2], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[2], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[2], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[3], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[3], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[3], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[3], MD4C01, MD4S13);
MD4_STEP (MD4_H , a, b, c, d, w0[0], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[0], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[0], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[0], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[2], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[2], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[2], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[2], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[1], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[1], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[1], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[1], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[3], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[3], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[3], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[3], MD4C02, MD4S23);
Initial commit
2015-12-04 14:47:52 +00:00
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
COMPARE_M_SIMD (a, d, c, b);
Initial commit
2015-12-04 14:47:52 +00:00
}
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_m08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_m16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_s04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* modifier
*/
const u32 lid = get_local_id (0);
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 11:04:22 +00:00
u32 pw_buf0[4];
u32 pw_buf1[4];
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
pw_buf0[0] = pws[gid].i[0];
pw_buf0[1] = pws[gid].i[1];
pw_buf0[2] = pws[gid].i[2];
pw_buf0[3] = pws[gid].i[3];
pw_buf1[0] = pws[gid].i[4];
pw_buf1[1] = pws[gid].i[5];
pw_buf1[2] = pws[gid].i[6];
pw_buf1[3] = pws[gid].i[7];
Initial commit
2015-12-04 14:47:52 +00:00
const u32 pw_len = pws[gid].pw_len;
/**
* digest
*/
const u32 search[4] =
{
digests_buf[digests_offset].digest_buf[DGST_R0],
digests_buf[digests_offset].digest_buf[DGST_R1],
digests_buf[digests_offset].digest_buf[DGST_R2],
digests_buf[digests_offset].digest_buf[DGST_R3]
};
/**
* salt
*/
Use real registers for salt, high-end maxwells didn't like it with global memory access
2016-05-09 21:07:23 +00:00
const u32 salt_buf0 = salt_bufs[salt_pos].salt_buf[0];
const u32 salt_buf1 = salt_bufs[salt_pos].salt_buf[1];
const u32 salt_buf2 = salt_bufs[salt_pos].salt_buf[2];
const u32 salt_buf3 = salt_bufs[salt_pos].salt_buf[3];
const u32 salt_buf4 = salt_bufs[salt_pos].salt_buf[4];
const u32 salt_buf5 = salt_bufs[salt_pos].salt_buf[5];
const u32 salt_buf6 = salt_bufs[salt_pos].salt_buf[6];
const u32 salt_buf7 = salt_bufs[salt_pos].salt_buf[7];
const u32 salt_buf8 = salt_bufs[salt_pos].salt_buf[8];
const u32 salt_buf9 = salt_bufs[salt_pos].salt_buf[9];
const u32 salt_len = salt_bufs[salt_pos].salt_len;
Initial commit
2015-12-04 14:47:52 +00:00
/**
* loop
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 14:47:52 +00:00
{
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
u32x w0[4] = { 0 };
u32x w1[4] = { 0 };
u32x w2[4] = { 0 };
u32x w3[4] = { 0 };
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
const u32x out_len = apply_rules_vect (pw_buf0, pw_buf1, pw_len, rules_buf, il_pos, w0, w1);
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
append_0x80_2x4_VV (w0, w1, out_len);
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
make_unicode (w1, w2, w3);
make_unicode (w0, w0, w1);
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w3[2] = out_len * 2 * 8;
w3[3] = 0;
Initial commit
2015-12-04 14:47:52 +00:00
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
u32x a = MD4M_A;
u32x b = MD4M_B;
u32x c = MD4M_C;
u32x d = MD4M_D;
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
MD4_STEP (MD4_Fo, a, b, c, d, w0[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w0[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w0[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w0[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w1[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w1[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w1[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w1[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w2[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w2[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w2[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w2[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w3[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w3[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w3[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w3[3], MD4C00, MD4S03);
MD4_STEP (MD4_Go, a, b, c, d, w0[0], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[0], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[0], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[0], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[1], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[1], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[1], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[1], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[2], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[2], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[2], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[2], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[3], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[3], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[3], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[3], MD4C01, MD4S13);
MD4_STEP (MD4_H , a, b, c, d, w0[0], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[0], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[0], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[0], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[2], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[2], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[2], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[2], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[1], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[1], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[1], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[1], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[3], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[3], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[3], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[3], MD4C02, MD4S23);
Initial commit
2015-12-04 14:47:52 +00:00
a += MD4M_A;
b += MD4M_B;
c += MD4M_C;
d += MD4M_D;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w0[0] = a;
w0[1] = b;
w0[2] = c;
w0[3] = d;
Use real registers for salt, high-end maxwells didn't like it with global memory access
2016-05-09 21:07:23 +00:00
w1[0] = salt_buf0;
w1[1] = salt_buf1;
w1[2] = salt_buf2;
w1[3] = salt_buf3;
w2[0] = salt_buf4;
w2[1] = salt_buf5;
w2[2] = salt_buf6;
w2[3] = salt_buf7;
w3[0] = salt_buf8;
w3[1] = salt_buf9;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
w3[2] = (16 + salt_len) * 8;
w3[3] = 0;
Initial commit
2015-12-04 14:47:52 +00:00
a = MD4M_A;
b = MD4M_B;
c = MD4M_C;
d = MD4M_D;
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
MD4_STEP (MD4_Fo, a, b, c, d, w0[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w0[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w0[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w0[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w1[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w1[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w1[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w1[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w2[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w2[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w2[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w2[3], MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w3[0], MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w3[1], MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w3[2], MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w3[3], MD4C00, MD4S03);
MD4_STEP (MD4_Go, a, b, c, d, w0[0], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[0], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[0], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[0], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[1], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[1], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[1], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[1], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[2], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[2], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[2], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[2], MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w0[3], MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w1[3], MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w2[3], MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, w3[3], MD4C01, MD4S13);
MD4_STEP (MD4_H , a, b, c, d, w0[0], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[0], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[0], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[0], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[2], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[2], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[2], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[2], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[1], MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w2[1], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[1], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[1], MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w0[3], MD4C02, MD4S20);
Initial commit
2015-12-04 14:47:52 +00:00
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
if (MATCHES_NONE_VS (a, search[0])) continue;
Initial commit
2015-12-04 14:47:52 +00:00
Cleanup -m 1100 kernels to latest standard
2016-03-04 15:54:28 +00:00
MD4_STEP (MD4_H , d, a, b, c, w2[3], MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w1[3], MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, w3[3], MD4C02, MD4S23);
Initial commit
2015-12-04 14:47:52 +00:00
Converted to new SIMD: -m 1100 -a 0
2016-02-05 16:43:10 +00:00
COMPARE_S_SIMD (a, d, c, b);
Initial commit
2015-12-04 14:47:52 +00:00
}
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_s08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m01100_s16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
}
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