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hashcat/OpenCL/m09900_a3.cl

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Initial commit
2015-12-04 14:47:52 +00:00
/**
* Author......: Jens Steube <jens.steube@gmail.com>
* License.....: MIT
*/
#define _MD5_
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
#define NEW_SIMD_CODE
Initial commit
2015-12-04 14:47:52 +00:00
#include "include/constants.h"
#include "include/kernel_vendor.h"
#define DGST_R0 0
#define DGST_R1 3
#define DGST_R2 2
#define DGST_R3 1
#include "include/kernel_functions.c"
Fix path to includes
2016-01-03 00:48:05 +00:00
#include "OpenCL/types_ocl.c"
#include "OpenCL/common.c"
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
#include "OpenCL/simd.c"
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
static void m09900m (u32 w[16], const u32 pw_len, __global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
/**
* base
*/
const u32 F_w0c00 = 0 + MD5C00;
const u32 F_w1c01 = w[ 1] + MD5C01;
const u32 F_w2c02 = w[ 2] + MD5C02;
const u32 F_w3c03 = w[ 3] + MD5C03;
const u32 F_w4c04 = w[ 4] + MD5C04;
const u32 F_w5c05 = w[ 5] + MD5C05;
const u32 F_w6c06 = w[ 6] + MD5C06;
const u32 F_w7c07 = w[ 7] + MD5C07;
const u32 F_w8c08 = w[ 8] + MD5C08;
const u32 F_w9c09 = w[ 9] + MD5C09;
const u32 F_wac0a = w[10] + MD5C0a;
const u32 F_wbc0b = w[11] + MD5C0b;
const u32 F_wcc0c = w[12] + MD5C0c;
const u32 F_wdc0d = w[13] + MD5C0d;
const u32 F_wec0e = w[14] + MD5C0e;
const u32 F_wfc0f = w[15] + MD5C0f;
const u32 G_w1c10 = w[ 1] + MD5C10;
const u32 G_w6c11 = w[ 6] + MD5C11;
const u32 G_wbc12 = w[11] + MD5C12;
const u32 G_w0c13 = 0 + MD5C13;
const u32 G_w5c14 = w[ 5] + MD5C14;
const u32 G_wac15 = w[10] + MD5C15;
const u32 G_wfc16 = w[15] + MD5C16;
const u32 G_w4c17 = w[ 4] + MD5C17;
const u32 G_w9c18 = w[ 9] + MD5C18;
const u32 G_wec19 = w[14] + MD5C19;
const u32 G_w3c1a = w[ 3] + MD5C1a;
const u32 G_w8c1b = w[ 8] + MD5C1b;
const u32 G_wdc1c = w[13] + MD5C1c;
const u32 G_w2c1d = w[ 2] + MD5C1d;
const u32 G_w7c1e = w[ 7] + MD5C1e;
const u32 G_wcc1f = w[12] + MD5C1f;
const u32 H_w5c20 = w[ 5] + MD5C20;
const u32 H_w8c21 = w[ 8] + MD5C21;
const u32 H_wbc22 = w[11] + MD5C22;
const u32 H_wec23 = w[14] + MD5C23;
const u32 H_w1c24 = w[ 1] + MD5C24;
const u32 H_w4c25 = w[ 4] + MD5C25;
const u32 H_w7c26 = w[ 7] + MD5C26;
const u32 H_wac27 = w[10] + MD5C27;
const u32 H_wdc28 = w[13] + MD5C28;
const u32 H_w0c29 = 0 + MD5C29;
const u32 H_w3c2a = w[ 3] + MD5C2a;
const u32 H_w6c2b = w[ 6] + MD5C2b;
const u32 H_w9c2c = w[ 9] + MD5C2c;
const u32 H_wcc2d = w[12] + MD5C2d;
const u32 H_wfc2e = w[15] + MD5C2e;
const u32 H_w2c2f = w[ 2] + MD5C2f;
const u32 I_w0c30 = 0 + MD5C30;
const u32 I_w7c31 = w[ 7] + MD5C31;
const u32 I_wec32 = w[14] + MD5C32;
const u32 I_w5c33 = w[ 5] + MD5C33;
const u32 I_wcc34 = w[12] + MD5C34;
const u32 I_w3c35 = w[ 3] + MD5C35;
const u32 I_wac36 = w[10] + MD5C36;
const u32 I_w1c37 = w[ 1] + MD5C37;
const u32 I_w8c38 = w[ 8] + MD5C38;
const u32 I_wfc39 = w[15] + MD5C39;
const u32 I_w6c3a = w[ 6] + MD5C3a;
const u32 I_wdc3b = w[13] + MD5C3b;
const u32 I_w4c3c = w[ 4] + MD5C3c;
const u32 I_wbc3d = w[11] + MD5C3d;
const u32 I_w2c3e = w[ 2] + MD5C3e;
const u32 I_w9c3f = w[ 9] + MD5C3f;
/**
* loop
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 11:04:22 +00:00
u32 w0l = w[0];
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 14:47:52 +00:00
{
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
const u32x w0r = words_buf_r[il_pos / VECT_SIZE];
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
const u32x w0 = w0l | w0r;
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x a = MD5M_A;
u32x b = MD5M_B;
u32x c = MD5M_C;
u32x d = MD5M_D;
Initial commit
2015-12-04 14:47:52 +00:00
MD5_STEP (MD5_Fo, a, b, c, d, w0, F_w0c00, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w1c01, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_w2c02, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_w3c03, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_w4c04, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w5c05, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_w6c06, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_w7c07, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_w8c08, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w9c09, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_wac0a, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_wbc0b, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_wcc0c, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_wdc0d, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_wec0e, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_wfc0f, MD5S03);
MD5_STEP0(MD5_Go, a, b, c, d, G_w1c10, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_w6c11, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_wbc12, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, w0, G_w0c13, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_w5c14, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_wac15, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_wfc16, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_w4c17, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_w9c18, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_wec19, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_w3c1a, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_w8c1b, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_wdc1c, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_w2c1d, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_w7c1e, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_wcc1f, MD5S13);
MD5_STEP0(MD5_H , a, b, c, d, H_w5c20, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_w8c21, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_wbc22, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_wec23, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_w1c24, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_w4c25, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_w7c26, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_wac27, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_wdc28, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, w0, H_w0c29, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_w3c2a, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_w6c2b, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_w9c2c, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_wcc2d, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_wfc2e, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_w2c2f, MD5S23);
MD5_STEP (MD5_I , a, b, c, d, w0, I_w0c30, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_w7c31, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_wec32, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w5c33, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_wcc34, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_w3c35, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_wac36, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w1c37, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_w8c38, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_wfc39, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_w6c3a, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_wdc3b, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_w4c3c, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_wbc3d, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_w2c3e, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w9c3f, MD5S33);
a += MD5M_A;
b += MD5M_B;
c += MD5M_C;
d += MD5M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x r_a = a;
u32x r_b = b;
u32x r_c = c;
u32x r_d = d;
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x t0[4];
u32x t1[4];
u32x t2[4];
u32x t3[4];
Initial commit
2015-12-04 14:47:52 +00:00
t0[0] = 0;
t0[1] = 0;
t0[2] = 0;
t0[3] = 0;
t1[0] = 0;
t1[1] = 0;
t1[2] = 0;
t1[3] = 0;
t2[0] = 0;
t2[1] = 0x80;
t2[2] = 0;
t2[3] = 0;
t3[0] = 0;
t3[1] = 0;
t3[2] = 100 * 8;
t3[3] = 0;
MD5_STEP (MD5_Fo, a, b, c, d, t0[0], MD5C00, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t0[1], MD5C01, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t0[2], MD5C02, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t0[3], MD5C03, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t1[0], MD5C04, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t1[1], MD5C05, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t1[2], MD5C06, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t1[3], MD5C07, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t2[0], MD5C08, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t2[1], MD5C09, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t2[2], MD5C0a, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t2[3], MD5C0b, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t3[0], MD5C0c, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t3[1], MD5C0d, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t3[2], MD5C0e, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t3[3], MD5C0f, MD5S03);
MD5_STEP (MD5_Go, a, b, c, d, t0[1], MD5C10, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t1[2], MD5C11, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t2[3], MD5C12, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t0[0], MD5C13, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t1[1], MD5C14, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t2[2], MD5C15, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t3[3], MD5C16, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t1[0], MD5C17, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t2[1], MD5C18, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t3[2], MD5C19, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t0[3], MD5C1a, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t2[0], MD5C1b, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t3[1], MD5C1c, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t0[2], MD5C1d, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t1[3], MD5C1e, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t3[0], MD5C1f, MD5S13);
MD5_STEP (MD5_H , a, b, c, d, t1[1], MD5C20, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t2[0], MD5C21, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t2[3], MD5C22, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t3[2], MD5C23, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t0[1], MD5C24, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t1[0], MD5C25, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t1[3], MD5C26, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t2[2], MD5C27, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t3[1], MD5C28, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t0[0], MD5C29, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t0[3], MD5C2a, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t1[2], MD5C2b, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t2[1], MD5C2c, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t3[0], MD5C2d, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t3[3], MD5C2e, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t0[2], MD5C2f, MD5S23);
MD5_STEP (MD5_I , a, b, c, d, t0[0], MD5C30, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t1[3], MD5C31, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t3[2], MD5C32, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t1[1], MD5C33, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t3[0], MD5C34, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t0[3], MD5C35, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t2[2], MD5C36, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t0[1], MD5C37, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t2[0], MD5C38, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t3[3], MD5C39, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t1[2], MD5C3a, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t3[1], MD5C3b, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t1[0], MD5C3c, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t2[3], MD5C3d, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t0[2], MD5C3e, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t2[1], MD5C3f, MD5S33);
a += r_a;
b += r_b;
c += r_c;
d += r_d;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
COMPARE_M_SIMD (a, d, c, b);
Initial commit
2015-12-04 14:47:52 +00:00
}
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
static void m09900s (u32 w[16], const u32 pw_len, __global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
/**
* base
*/
const u32 F_w0c00 = 0 + MD5C00;
const u32 F_w1c01 = w[ 1] + MD5C01;
const u32 F_w2c02 = w[ 2] + MD5C02;
const u32 F_w3c03 = w[ 3] + MD5C03;
const u32 F_w4c04 = w[ 4] + MD5C04;
const u32 F_w5c05 = w[ 5] + MD5C05;
const u32 F_w6c06 = w[ 6] + MD5C06;
const u32 F_w7c07 = w[ 7] + MD5C07;
const u32 F_w8c08 = w[ 8] + MD5C08;
const u32 F_w9c09 = w[ 9] + MD5C09;
const u32 F_wac0a = w[10] + MD5C0a;
const u32 F_wbc0b = w[11] + MD5C0b;
const u32 F_wcc0c = w[12] + MD5C0c;
const u32 F_wdc0d = w[13] + MD5C0d;
const u32 F_wec0e = w[14] + MD5C0e;
const u32 F_wfc0f = w[15] + MD5C0f;
const u32 G_w1c10 = w[ 1] + MD5C10;
const u32 G_w6c11 = w[ 6] + MD5C11;
const u32 G_wbc12 = w[11] + MD5C12;
const u32 G_w0c13 = 0 + MD5C13;
const u32 G_w5c14 = w[ 5] + MD5C14;
const u32 G_wac15 = w[10] + MD5C15;
const u32 G_wfc16 = w[15] + MD5C16;
const u32 G_w4c17 = w[ 4] + MD5C17;
const u32 G_w9c18 = w[ 9] + MD5C18;
const u32 G_wec19 = w[14] + MD5C19;
const u32 G_w3c1a = w[ 3] + MD5C1a;
const u32 G_w8c1b = w[ 8] + MD5C1b;
const u32 G_wdc1c = w[13] + MD5C1c;
const u32 G_w2c1d = w[ 2] + MD5C1d;
const u32 G_w7c1e = w[ 7] + MD5C1e;
const u32 G_wcc1f = w[12] + MD5C1f;
const u32 H_w5c20 = w[ 5] + MD5C20;
const u32 H_w8c21 = w[ 8] + MD5C21;
const u32 H_wbc22 = w[11] + MD5C22;
const u32 H_wec23 = w[14] + MD5C23;
const u32 H_w1c24 = w[ 1] + MD5C24;
const u32 H_w4c25 = w[ 4] + MD5C25;
const u32 H_w7c26 = w[ 7] + MD5C26;
const u32 H_wac27 = w[10] + MD5C27;
const u32 H_wdc28 = w[13] + MD5C28;
const u32 H_w0c29 = 0 + MD5C29;
const u32 H_w3c2a = w[ 3] + MD5C2a;
const u32 H_w6c2b = w[ 6] + MD5C2b;
const u32 H_w9c2c = w[ 9] + MD5C2c;
const u32 H_wcc2d = w[12] + MD5C2d;
const u32 H_wfc2e = w[15] + MD5C2e;
const u32 H_w2c2f = w[ 2] + MD5C2f;
const u32 I_w0c30 = 0 + MD5C30;
const u32 I_w7c31 = w[ 7] + MD5C31;
const u32 I_wec32 = w[14] + MD5C32;
const u32 I_w5c33 = w[ 5] + MD5C33;
const u32 I_wcc34 = w[12] + MD5C34;
const u32 I_w3c35 = w[ 3] + MD5C35;
const u32 I_wac36 = w[10] + MD5C36;
const u32 I_w1c37 = w[ 1] + MD5C37;
const u32 I_w8c38 = w[ 8] + MD5C38;
const u32 I_wfc39 = w[15] + MD5C39;
const u32 I_w6c3a = w[ 6] + MD5C3a;
const u32 I_wdc3b = w[13] + MD5C3b;
const u32 I_w4c3c = w[ 4] + MD5C3c;
const u32 I_wbc3d = w[11] + MD5C3d;
const u32 I_w2c3e = w[ 2] + MD5C3e;
const u32 I_w9c3f = w[ 9] + MD5C3f;
/**
* digest
*/
const u32 search[4] =
{
digests_buf[digests_offset].digest_buf[DGST_R0],
digests_buf[digests_offset].digest_buf[DGST_R1],
digests_buf[digests_offset].digest_buf[DGST_R2],
digests_buf[digests_offset].digest_buf[DGST_R3]
};
/**
* loop
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 11:04:22 +00:00
u32 w0l = w[0];
Initial commit
2015-12-04 14:47:52 +00:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 14:47:52 +00:00
{
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
const u32x w0r = words_buf_r[il_pos / VECT_SIZE];
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
const u32x w0 = w0l | w0r;
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x a = MD5M_A;
u32x b = MD5M_B;
u32x c = MD5M_C;
u32x d = MD5M_D;
Initial commit
2015-12-04 14:47:52 +00:00
MD5_STEP (MD5_Fo, a, b, c, d, w0, F_w0c00, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w1c01, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_w2c02, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_w3c03, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_w4c04, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w5c05, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_w6c06, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_w7c07, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_w8c08, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_w9c09, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_wac0a, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_wbc0b, MD5S03);
MD5_STEP0(MD5_Fo, a, b, c, d, F_wcc0c, MD5S00);
MD5_STEP0(MD5_Fo, d, a, b, c, F_wdc0d, MD5S01);
MD5_STEP0(MD5_Fo, c, d, a, b, F_wec0e, MD5S02);
MD5_STEP0(MD5_Fo, b, c, d, a, F_wfc0f, MD5S03);
MD5_STEP0(MD5_Go, a, b, c, d, G_w1c10, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_w6c11, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_wbc12, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, w0, G_w0c13, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_w5c14, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_wac15, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_wfc16, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_w4c17, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_w9c18, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_wec19, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_w3c1a, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_w8c1b, MD5S13);
MD5_STEP0(MD5_Go, a, b, c, d, G_wdc1c, MD5S10);
MD5_STEP0(MD5_Go, d, a, b, c, G_w2c1d, MD5S11);
MD5_STEP0(MD5_Go, c, d, a, b, G_w7c1e, MD5S12);
MD5_STEP0(MD5_Go, b, c, d, a, G_wcc1f, MD5S13);
MD5_STEP0(MD5_H , a, b, c, d, H_w5c20, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_w8c21, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_wbc22, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_wec23, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_w1c24, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_w4c25, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_w7c26, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_wac27, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_wdc28, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, w0, H_w0c29, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_w3c2a, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_w6c2b, MD5S23);
MD5_STEP0(MD5_H , a, b, c, d, H_w9c2c, MD5S20);
MD5_STEP0(MD5_H , d, a, b, c, H_wcc2d, MD5S21);
MD5_STEP0(MD5_H , c, d, a, b, H_wfc2e, MD5S22);
MD5_STEP0(MD5_H , b, c, d, a, H_w2c2f, MD5S23);
MD5_STEP (MD5_I , a, b, c, d, w0, I_w0c30, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_w7c31, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_wec32, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w5c33, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_wcc34, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_w3c35, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_wac36, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w1c37, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_w8c38, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_wfc39, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_w6c3a, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_wdc3b, MD5S33);
MD5_STEP0(MD5_I , a, b, c, d, I_w4c3c, MD5S30);
MD5_STEP0(MD5_I , d, a, b, c, I_wbc3d, MD5S31);
MD5_STEP0(MD5_I , c, d, a, b, I_w2c3e, MD5S32);
MD5_STEP0(MD5_I , b, c, d, a, I_w9c3f, MD5S33);
a += MD5M_A;
b += MD5M_B;
c += MD5M_C;
d += MD5M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x r_a = a;
u32x r_b = b;
u32x r_c = c;
u32x r_d = d;
Initial commit
2015-12-04 14:47:52 +00:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
u32x t0[4];
u32x t1[4];
u32x t2[4];
u32x t3[4];
Initial commit
2015-12-04 14:47:52 +00:00
t0[0] = 0;
t0[1] = 0;
t0[2] = 0;
t0[3] = 0;
t1[0] = 0;
t1[1] = 0;
t1[2] = 0;
t1[3] = 0;
t2[0] = 0;
t2[1] = 0x80;
t2[2] = 0;
t2[3] = 0;
t3[0] = 0;
t3[1] = 0;
t3[2] = 100 * 8;
t3[3] = 0;
MD5_STEP (MD5_Fo, a, b, c, d, t0[0], MD5C00, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t0[1], MD5C01, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t0[2], MD5C02, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t0[3], MD5C03, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t1[0], MD5C04, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t1[1], MD5C05, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t1[2], MD5C06, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t1[3], MD5C07, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t2[0], MD5C08, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t2[1], MD5C09, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t2[2], MD5C0a, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t2[3], MD5C0b, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, t3[0], MD5C0c, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, t3[1], MD5C0d, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, t3[2], MD5C0e, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, t3[3], MD5C0f, MD5S03);
MD5_STEP (MD5_Go, a, b, c, d, t0[1], MD5C10, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t1[2], MD5C11, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t2[3], MD5C12, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t0[0], MD5C13, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t1[1], MD5C14, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t2[2], MD5C15, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t3[3], MD5C16, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t1[0], MD5C17, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t2[1], MD5C18, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t3[2], MD5C19, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t0[3], MD5C1a, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t2[0], MD5C1b, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, t3[1], MD5C1c, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, t0[2], MD5C1d, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, t1[3], MD5C1e, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, t3[0], MD5C1f, MD5S13);
MD5_STEP (MD5_H , a, b, c, d, t1[1], MD5C20, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t2[0], MD5C21, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t2[3], MD5C22, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t3[2], MD5C23, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t0[1], MD5C24, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t1[0], MD5C25, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t1[3], MD5C26, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t2[2], MD5C27, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t3[1], MD5C28, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t0[0], MD5C29, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t0[3], MD5C2a, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t1[2], MD5C2b, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, t2[1], MD5C2c, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, t3[0], MD5C2d, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, t3[3], MD5C2e, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, t0[2], MD5C2f, MD5S23);
MD5_STEP (MD5_I , a, b, c, d, t0[0], MD5C30, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t1[3], MD5C31, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t3[2], MD5C32, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t1[1], MD5C33, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t3[0], MD5C34, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t0[3], MD5C35, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t2[2], MD5C36, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t0[1], MD5C37, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t2[0], MD5C38, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, t3[3], MD5C39, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t1[2], MD5C3a, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t3[1], MD5C3b, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, t1[0], MD5C3c, MD5S30);
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
if (MATCHES_NONE_VS ((a + r_a), search[0])) continue;
Initial commit
2015-12-04 14:47:52 +00:00
MD5_STEP (MD5_I , d, a, b, c, t2[3], MD5C3d, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, t0[2], MD5C3e, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, t2[1], MD5C3f, MD5S33);
a += r_a;
b += r_b;
c += r_c;
d += r_d;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 14:32:31 +00:00
COMPARE_S_SIMD (a, d, c, b);
Initial commit
2015-12-04 14:47:52 +00:00
}
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_m04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = 0;
w[ 5] = 0;
w[ 6] = 0;
w[ 7] = 0;
w[ 8] = 0;
w[ 9] = 0;
w[10] = 0;
w[11] = 0;
w[12] = 0;
w[13] = 0;
w[14] = 0;
w[15] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900m (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_m08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = pws[gid].i[ 4];
w[ 5] = pws[gid].i[ 5];
w[ 6] = pws[gid].i[ 6];
w[ 7] = pws[gid].i[ 7];
w[ 8] = 0;
w[ 9] = 0;
w[10] = 0;
w[11] = 0;
w[12] = 0;
w[13] = 0;
w[14] = 0;
w[15] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900m (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_m16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = pws[gid].i[ 4];
w[ 5] = pws[gid].i[ 5];
w[ 6] = pws[gid].i[ 6];
w[ 7] = pws[gid].i[ 7];
w[ 8] = pws[gid].i[ 8];
w[ 9] = pws[gid].i[ 9];
w[10] = pws[gid].i[10];
w[11] = pws[gid].i[11];
w[12] = pws[gid].i[12];
w[13] = pws[gid].i[13];
w[14] = pws[gid].i[14];
w[15] = pws[gid].i[15];
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900m (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_s04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = 0;
w[ 5] = 0;
w[ 6] = 0;
w[ 7] = 0;
w[ 8] = 0;
w[ 9] = 0;
w[10] = 0;
w[11] = 0;
w[12] = 0;
w[13] = 0;
w[14] = 0;
w[15] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900s (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_s08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = pws[gid].i[ 4];
w[ 5] = pws[gid].i[ 5];
w[ 6] = pws[gid].i[ 6];
w[ 7] = pws[gid].i[ 7];
w[ 8] = 0;
w[ 9] = 0;
w[10] = 0;
w[11] = 0;
w[12] = 0;
w[13] = 0;
w[14] = 0;
w[15] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900s (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
__kernel void m09900_s16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __constant u32x * words_buf_r, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global void *esalt_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 14:47:52 +00:00
{
/**
* base
*/
const u32 gid = get_global_id (0);
if (gid >= gid_max) return;
u32 w[16];
w[ 0] = pws[gid].i[ 0];
w[ 1] = pws[gid].i[ 1];
w[ 2] = pws[gid].i[ 2];
w[ 3] = pws[gid].i[ 3];
w[ 4] = pws[gid].i[ 4];
w[ 5] = pws[gid].i[ 5];
w[ 6] = pws[gid].i[ 6];
w[ 7] = pws[gid].i[ 7];
w[ 8] = pws[gid].i[ 8];
w[ 9] = pws[gid].i[ 9];
w[10] = pws[gid].i[10];
w[11] = pws[gid].i[11];
w[12] = pws[gid].i[12];
w[13] = pws[gid].i[13];
w[14] = pws[gid].i[14];
w[15] = pws[gid].i[15];
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 16:18:54 +00:00
m09900s (w, pw_len, pws, rules_buf, combs_buf, words_buf_r, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, esalt_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset);
Initial commit
2015-12-04 14:47:52 +00:00
}
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