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Fix port numbering for Wic slot 1 & 2

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This commit is contained in:
Julien Duponchelle 2017-05-12 14:12:24 +02:00
parent 19a6157f64
commit 5721dd3f30
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GPG Key ID: CE8B29639E07F5E8
2 changed files with 11 additions and 5 deletions
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12
gns3server/controller/ports/port_factory.py
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@ -181,7 +181,9 @@ class DynamipsPortFactory:
ports = []
adapter_number = 0
wic_port_number = 16
wic_slot = 1
wic_port_number = wic_slot * 16
display_wic_port_number = 0
for name in sorted(properties.keys()):
if name.startswith("slot") and properties[name]:
port_class = cls.ADAPTER_MATRIX[properties[name]]["port"]
@ -194,9 +196,13 @@ class DynamipsPortFactory:
port_class = cls.WIC_MATRIX[properties[name]]["port"]
if port_class:
for port_number in range(0, cls.WIC_MATRIX[properties[name]]["nb_ports"]):
name = "{}{}/{}".format(port_class.long_name_type(), 0, wic_port_number - 16)
name = "{}{}/{}".format(port_class.long_name_type(), 0, display_wic_port_number)
port = port_class(name, 0, 0, wic_port_number)
port.short_name = "{}{}/{}".format(port.short_name_type, 0, wic_port_number - 16)
port.short_name = "{}{}/{}".format(port.short_name_type, 0, display_wic_port_number)
ports.append(port)
display_wic_port_number += 1
wic_port_number += 1
wic_slot += 1
wic_port_number = wic_slot * 16
return ports

4
tests/controller/test_node_port_name.py
View File

@ -576,7 +576,7 @@ def test_list_ports_dynamips(project, compute):
"Cisco HDLC": "DLT_C_HDLC",
"Cisco PPP": "DLT_PPP_SERIAL",
"Frame Relay": "DLT_FRELAY"},
"port_number": 18,
"port_number": 32,
"adapter_number": 0,
"link_type": "serial"
},
@ -587,7 +587,7 @@ def test_list_ports_dynamips(project, compute):
"Cisco HDLC": "DLT_C_HDLC",
"Cisco PPP": "DLT_PPP_SERIAL",
"Frame Relay": "DLT_FRELAY"},
"port_number": 19,
"port_number": 33,
"adapter_number": 0,
"link_type": "serial"
}