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Code Issues Releases Wiki Activity

Fixes ATM mapping.

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This commit is contained in:
grossmj 2017-05-12 13:09:26 +08:00
parent 87d42f4eb9
commit 18cfcaa081
1 changed files with 37 additions and 12 deletions
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49
gns3server/compute/dynamips/nodes/atm_switch.py
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@ -188,22 +188,33 @@ class ATMSwitch(Device):
raise DynamipsError("Port {} is not allocated".format(port_number)) raise DynamipsError("Port {} is not allocated".format(port_number))
# remove VCs mapped with the port # remove VCs mapped with the port
pvc_entry = re.compile(r"""^([0-9]*):([0-9]*):([0-9]*)$""")
for source, destination in self._active_mappings.copy().items(): for source, destination in self._active_mappings.copy().items():
match_source_pvc = pvc_entry.search(source) if len(source) == 3 and len(destination) == 3:
match_destination_pvc = pvc_entry.search(destination)
if match_source_pvc and match_destination_pvc:
# remove the virtual channels mapped with this port/nio # remove the virtual channels mapped with this port/nio
source_port, source_vpi, source_vci = map(int, match_source_pvc.group(1, 2, 3)) source_port, source_vpi, source_vci = source
destination_port, destination_vpi, destination_vci = map(int, match_destination_pvc.group(1, 2, 3)) destination_port, destination_vpi, destination_vci = destination
if port_number == source_port: if port_number == source_port:
log.info('ATM switch "{name}" [{id}]: unmapping VCC between port {source_port} VPI {source_vpi} VCI {source_vci} and port {destination_port} VPI {destination_vpi} VCI {destination_vci}'.format(name=self._name,
id=self._id,
source_port=source_port,
source_vpi=source_vpi,
source_vci=source_vci,
destination_port=destination_port,
destination_vpi=destination_vpi,
destination_vci=destination_vci))
yield from self.unmap_pvc(source_port, source_vpi, source_vci, destination_port, destination_vpi, destination_vci) yield from self.unmap_pvc(source_port, source_vpi, source_vci, destination_port, destination_vpi, destination_vci)
yield from self.unmap_pvc(destination_port, destination_vpi, destination_vci, source_port, source_vpi, source_vci) yield from self.unmap_pvc(destination_port, destination_vpi, destination_vci, source_port, source_vpi, source_vci)
else: else:
# remove the virtual paths mapped with this port/nio # remove the virtual paths mapped with this port/nio
source_port, source_vpi = map(int, source.split(':')) source_port, source_vpi = source
destination_port, destination_vpi = map(int, destination.split(':')) destination_port, destination_vpi = destination
if port_number == source_port: if port_number == source_port:
log.info('ATM switch "{name}" [{id}]: unmapping VPC between port {source_port} VPI {source_vpi} and port {destination_port} VPI {destination_vpi}'.format(name=self._name,
id=self._id,
source_port=source_port,
source_vpi=source_vpi,
destination_port=destination_port,
destination_vpi=destination_vpi))
yield from self.unmap_vp(source_port, source_vpi, destination_port, destination_vpi) yield from self.unmap_vp(source_port, source_vpi, destination_port, destination_vpi)
yield from self.unmap_vp(destination_port, destination_vpi, source_port, source_vpi) yield from self.unmap_vp(destination_port, destination_vpi, source_port, source_vpi)
@ -239,6 +250,14 @@ class ATMSwitch(Device):
if self.has_port(destination_port): if self.has_port(destination_port):
if (source_port, source_vpi, source_vci) not in self._active_mappings and \ if (source_port, source_vpi, source_vci) not in self._active_mappings and \
(destination_port, destination_vpi, destination_vci) not in self._active_mappings: (destination_port, destination_vpi, destination_vci) not in self._active_mappings:
log.info('ATM switch "{name}" [{id}]: mapping VCC between port {source_port} VPI {source_vpi} VCI {source_vci} and port {destination_port} VPI {destination_vpi} VCI {destination_vci}'.format(name=self._name,
id=self._id,
source_port=source_port,
source_vpi=source_vpi,
source_vci=source_vci,
destination_port=destination_port,
destination_vpi=destination_vpi,
destination_vci=destination_vci))
yield from self.map_pvc(source_port, source_vpi, source_vci, destination_port, destination_vpi, destination_vci) yield from self.map_pvc(source_port, source_vpi, source_vci, destination_port, destination_vpi, destination_vci)
yield from self.map_pvc(destination_port, destination_vpi, destination_vci, source_port, source_vpi, source_vci) yield from self.map_pvc(destination_port, destination_vpi, destination_vci, source_port, source_vpi, source_vci)
else: else:
@ -247,6 +266,12 @@ class ATMSwitch(Device):
destination_port, destination_vpi = map(int, destination.split(':')) destination_port, destination_vpi = map(int, destination.split(':'))
if self.has_port(destination_port): if self.has_port(destination_port):
if (source_port, source_vpi) not in self._active_mappings and (destination_port, destination_vpi) not in self._active_mappings: if (source_port, source_vpi) not in self._active_mappings and (destination_port, destination_vpi) not in self._active_mappings:
log.info('ATM switch "{name}" [{id}]: mapping VPC between port {source_port} VPI {source_vpi} and port {destination_port} VPI {destination_vpi}'.format(name=self._name,
id=self._id,
source_port=source_port,
source_vpi=source_vpi,
destination_port=destination_port,
destination_vpi=destination_vpi))
yield from self.map_vp(source_port, source_vpi, destination_port, destination_vpi) yield from self.map_vp(source_port, source_vpi, destination_port, destination_vpi)
yield from self.map_vp(destination_port, destination_vpi, source_port, source_vpi) yield from self.map_vp(destination_port, destination_vpi, source_port, source_vpi)
@ -283,7 +308,7 @@ class ATMSwitch(Device):
port2=port2, port2=port2,
vpi2=vpi2)) vpi2=vpi2))
self._active_mappings["{}:{}".format(port1, vpi1)] = "{}:{}".format(port2, vpi2) self._active_mappings[(port1, vpi1)] = (port2, vpi2)
@asyncio.coroutine @asyncio.coroutine
def unmap_vp(self, port1, vpi1, port2, vpi2): def unmap_vp(self, port1, vpi1, port2, vpi2):
@ -318,7 +343,7 @@ class ATMSwitch(Device):
port2=port2, port2=port2,
vpi2=vpi2)) vpi2=vpi2))
del self._active_mappings["{}:{}".format(port1, vpi1)] del self._active_mappings[(port1, vpi1)]
@asyncio.coroutine @asyncio.coroutine
def map_pvc(self, port1, vpi1, vci1, port2, vpi2, vci2): def map_pvc(self, port1, vpi1, vci1, port2, vpi2, vci2):
@ -359,7 +384,7 @@ class ATMSwitch(Device):
vpi2=vpi2, vpi2=vpi2,
vci2=vci2)) vci2=vci2))
self._active_mappings["{}:{}:{}".format(port1, vpi1, vci1)] = "{}:{}:{}".format(port2, vpi2, vci2) self._active_mappings[(port1, vpi1, vci1)] = (port2, vpi2, vci2)
@asyncio.coroutine @asyncio.coroutine
def unmap_pvc(self, port1, vpi1, vci1, port2, vpi2, vci2): def unmap_pvc(self, port1, vpi1, vci1, port2, vpi2, vci2):
@ -399,7 +424,7 @@ class ATMSwitch(Device):
port2=port2, port2=port2,
vpi2=vpi2, vpi2=vpi2,
vci2=vci2)) vci2=vci2))
del self._active_mappings["{}:{}:{}".format(port1, vpi1, vci1)] del self._active_mappings[(port1, vpi1, vci1)]
@asyncio.coroutine @asyncio.coroutine
def start_capture(self, port_number, output_file, data_link_type="DLT_ATM_RFC1483"): def start_capture(self, port_number, output_file, data_link_type="DLT_ATM_RFC1483"):