mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-11-22 15:38:07 +00:00
9ff2543660
Moved the CET test cases in dedicated folders. Improved shadow-stack operand reporting - a distinction can be made between push/pop shadow stack accesses, and other shadow stack accesses. A new field is now present in the memory information - the shadow stack access type, which indicates: explicit access, implicit via SSP, implicit push/pop via SSP or implicit via IA32_PL0_SSP.
1266 lines
39 KiB
Python
1266 lines
39 KiB
Python
#!/usr/bin/env python3
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#
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# Copyright (c) 2020 Bitdefender
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# SPDX-License-Identifier: Apache-2.0
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#
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import os
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import sys
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import re
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import copy
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import glob
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import disasmlib
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flags = {
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'MODRM' : 'ND_FLAG_MODRM',
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'II64' : 'ND_FLAG_I64',
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'F64' : 'ND_FLAG_F64',
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'D64' : 'ND_FLAG_D64',
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'O64' : 'ND_FLAG_O64',
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'SSECONDB' : 'ND_FLAG_SSE_CONDB',
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'COND' : 'ND_FLAG_COND',
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'VSIB' : 'ND_FLAG_VSIB',
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'MIB' : 'ND_FLAG_MIB',
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'LIG' : 'ND_FLAG_LIG',
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'WIG' : 'ND_FLAG_WIG',
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'3DNOW' : 'ND_FLAG_3DNOW',
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'MMASK' : 'ND_FLAG_MMASK',
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'NOMZ' : 'ND_FLAG_NOMZ',
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'LOCKSP' : 'ND_FLAG_LOCK_SPECIAL',
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'NOL0' : 'ND_FLAG_NOL0',
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'NOA16' : 'ND_FLAG_NOA16',
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'NO66' : 'ND_FLAG_NO66',
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'NORIPREL' : 'ND_FLAG_NO_RIP_REL',
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'VECT' : 'ND_FLAG_VECTOR',
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'S66' : 'ND_FLAG_S66',
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'BITBASE' : 'ND_FLAG_BITBASE',
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'AG' : 'ND_FLAG_AG',
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'SHS' : 'ND_FLAG_SHS',
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'MFR' : 'ND_FLAG_MFR',
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'CETT' : 'ND_FLAG_CETT',
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'SERIAL' : 'ND_FLAG_SERIAL',
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'SIBMEM' : 'ND_FLAG_SIBMEM',
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}
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prefixes_map = {
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'REP' : 'ND_PREF_REP',
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'REPC' : 'ND_PREF_REPC',
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'HLE' : 'ND_PREF_HLE',
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'BND' : 'ND_PREF_BND',
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'LOCK' : 'ND_PREF_LOCK',
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'BH' : 'ND_PREF_BHINT',
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'XACQUIRE' : 'ND_PREF_XACQUIRE',
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'XRELEASE' : 'ND_PREF_XRELEASE',
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'HLEWOL' : 'ND_PREF_HLE_WO_LOCK',
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'DNT' : 'ND_PREF_DNT',
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}
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decorators_map = {
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'MASK' : 'ND_DECO_MASK',
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'BROADCAST': 'ND_DECO_BROADCAST',
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'ZERO' : 'ND_DECO_ZERO',
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'SAE' : 'ND_DECO_SAE',
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'ER' : 'ND_DECO_ER',
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}
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# Per operand flags.
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opflags = {
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'OPDEF' : 'ND_OPF_DEFAULT', # Default operand. Not encoded anywhere.
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'OPSEXO1' : 'ND_OPF_SEX_OP1',
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'OPSEXDW' : 'ND_OPF_SEX_DWS',
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}
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# Explicit operands map.
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optype = {
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'A' : 'ND_OPT_A',
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'B' : 'ND_OPT_B',
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'C' : 'ND_OPT_C',
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'D' : 'ND_OPT_D',
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'E' : 'ND_OPT_E',
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'F' : 'ND_OPT_F',
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'G' : 'ND_OPT_G',
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'H' : 'ND_OPT_H',
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'I' : 'ND_OPT_I',
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'J' : 'ND_OPT_J',
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'K' : 'ND_OPT_K',
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'L' : 'ND_OPT_L',
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'M' : 'ND_OPT_M',
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'N' : 'ND_OPT_N',
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'O' : 'ND_OPT_O',
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'P' : 'ND_OPT_P',
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'Q' : 'ND_OPT_Q',
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'R' : 'ND_OPT_R',
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'S' : 'ND_OPT_S',
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'T' : 'ND_OPT_T',
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'U' : 'ND_OPT_U',
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'V' : 'ND_OPT_V',
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'W' : 'ND_OPT_W',
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'X' : 'ND_OPT_X',
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'Y' : 'ND_OPT_Y',
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'Z' : 'ND_OPT_Z',
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'rB' : 'ND_OPT_rB',
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'mB' : 'ND_OPT_mB',
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'rK' : 'ND_OPT_rK',
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'vK' : 'ND_OPT_vK',
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'mK' : 'ND_OPT_mK',
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'aK' : 'ND_OPT_aK',
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'rM' : 'ND_OPT_rM',
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'mM' : 'ND_OPT_mM',
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'rT' : 'ND_OPT_rT',
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'mT' : 'ND_OPT_mT',
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'vT' : 'ND_OPT_vT',
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# Implicit operands.
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'1' : 'ND_OPT_CONST_1',
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'AH' : 'ND_OPT_GPR_AH',
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'rAX' : 'ND_OPT_GPR_rAX',
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'rCX' : 'ND_OPT_GPR_rCX',
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'rDX' : 'ND_OPT_GPR_rDX',
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'rBX' : 'ND_OPT_GPR_rBX',
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'rSP' : 'ND_OPT_GPR_rSP',
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'rBP' : 'ND_OPT_GPR_rBP',
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'rSI' : 'ND_OPT_GPR_rSI',
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'rDI' : 'ND_OPT_GPR_rDI',
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'rR11' : 'ND_OPT_GPR_rR11',
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'rIP' : 'ND_OPT_RIP',
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'CS' : 'ND_OPT_SEG_CS',
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'SS' : 'ND_OPT_SEG_SS',
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'DS' : 'ND_OPT_SEG_DS',
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'ES' : 'ND_OPT_SEG_ES',
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'FS' : 'ND_OPT_SEG_FS',
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'GS' : 'ND_OPT_SEG_GS',
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'ST(0)' : 'ND_OPT_FPU_ST0',
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'ST(i)' : 'ND_OPT_FPU_STX',
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'XMM0' : 'ND_OPT_SSE_XMM0',
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# Memory operands
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'pBXAL' : 'ND_OPT_MEM_rBX_AL',
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'pDI' : 'ND_OPT_MEM_rDI',
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'SHS' : 'ND_OPT_MEM_SHS',
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'SHS0' : 'ND_OPT_MEM_SHS0',
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'SHSP' : 'ND_OPT_MEM_SHSP',
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# System registers, MSRs, XCRs, etc.
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'GDTR' : 'ND_OPT_SYS_GDTR',
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'IDTR' : 'ND_OPT_SYS_IDTR',
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'LDTR' : 'ND_OPT_SYS_LDTR',
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'TR' : 'ND_OPT_SYS_TR',
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'CR0' : 'ND_OPT_CR_0',
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'XCR' : 'ND_OPT_XCR',
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'XCR0' : 'ND_OPT_XCR_0',
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'MSR' : 'ND_OPT_MSR',
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'FSBASE' : 'ND_OPT_MSR_FSBASE',
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'GSBASE' : 'ND_OPT_MSR_GSBASE',
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'KGSBASE' : 'ND_OPT_MSR_KGSBASE',
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'SCS' : 'ND_OPT_MSR_SCS',
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'SEIP' : 'ND_OPT_MSR_SEIP',
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'SESP' : 'ND_OPT_MSR_SESP',
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'TSC' : 'ND_OPT_MSR_TSC',
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'TSCAUX' : 'ND_OPT_MSR_TSCAUX',
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'STAR' : 'ND_OPT_MSR_STAR',
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'LSTAR' : 'ND_OPT_MSR_LSTAR',
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'FMASK' : 'ND_OPT_MSR_FMASK',
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'BANK' : 'ND_OPT_REG_BANK',
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'X87CONTROL':'ND_OPT_X87_CONTROL',
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'X87TAG' : 'ND_OPT_X87_TAG',
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'X87STATUS': 'ND_OPT_X87_STATUS',
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'MXCSR' : 'ND_OPT_MXCSR',
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'PKRU' : 'ND_OPT_PKRU',
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'SSP' : 'ND_OPT_SSP',
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}
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opsize = {
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'a' : 'ND_OPS_a',
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'b' : 'ND_OPS_b',
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'c' : 'ND_OPS_c',
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'd' : 'ND_OPS_d',
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'dq' : 'ND_OPS_dq',
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'e' : 'ND_OPS_e',
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'f' : 'ND_OPS_f',
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'h' : 'ND_OPS_h',
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'n' : 'ND_OPS_n',
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'u' : 'ND_OPS_u',
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'vm32x' : 'ND_OPS_vm32x',
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'vm32y' : 'ND_OPS_vm32y',
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'vm32z' : 'ND_OPS_vm32z',
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'vm32h' : 'ND_OPS_vm32h',
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'vm32n' : 'ND_OPS_vm32n',
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'vm64x' : 'ND_OPS_vm64x',
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'vm64y' : 'ND_OPS_vm64y',
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'vm64z' : 'ND_OPS_vm64z',
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'vm64h' : 'ND_OPS_vm64h',
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'vm64n' : 'ND_OPS_vm64n',
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'mib' : 'ND_OPS_mib',
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'v2' : 'ND_OPS_v2',
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'v3' : 'ND_OPS_v3',
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'v4' : 'ND_OPS_v4',
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'v8' : 'ND_OPS_v8',
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'oq' : 'ND_OPS_oq',
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'p' : 'ND_OPS_p',
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'pd' : 'ND_OPS_pd',
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'ps' : 'ND_OPS_ps',
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'q' : 'ND_OPS_q',
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'qq' : 'ND_OPS_qq',
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's' : 'ND_OPS_s',
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'sd' : 'ND_OPS_sd',
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'ss' : 'ND_OPS_ss',
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'v' : 'ND_OPS_v',
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'w' : 'ND_OPS_w',
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'x' : 'ND_OPS_x',
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'y' : 'ND_OPS_y',
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'yf' : 'ND_OPS_yf',
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'z' : 'ND_OPS_z',
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'?' : 'ND_OPS_unknown',
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'0' : 'ND_OPS_0',
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'asz' : 'ND_OPS_asz',
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'ssz' : 'ND_OPS_ssz',
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'fa' : 'ND_OPS_fa',
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'fw' : 'ND_OPS_fw',
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'fd' : 'ND_OPS_fd',
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'fq' : 'ND_OPS_fq',
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'ft' : 'ND_OPS_ft',
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'fe' : 'ND_OPS_fe',
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'fs' : 'ND_OPS_fs',
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'l' : 'ND_OPS_l',
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'rx' : 'ND_OPS_rx',
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'cl' : 'ND_OPS_cl',
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'12' : 'ND_OPS_12',
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't' : 'ND_OPS_t',
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}
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opdecorators = {
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'{K}' : 'ND_OPD_MASK',
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'{z}' : 'ND_OPD_Z',
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'{sae}' : 'ND_OPD_SAE',
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'{er}' : 'ND_OPD_ER',
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'|B32' : 'ND_OPD_B32',
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'|B64' : 'ND_OPD_B64',
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}
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accessmap = {
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'R' : 'ND_OPF_R',
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'W' : 'ND_OPF_W',
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'CR' : 'ND_OPF_CR',
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'CW' : 'ND_OPF_CW',
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'RW' : 'ND_OPF_RW',
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'RCW' : 'ND_OPF_RCW',
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'CRW' : 'ND_OPF_CRW',
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'CRCW' : 'ND_OPF_CRCW',
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'N' : 'ND_OPF_N',
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}
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tuples = {
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None : '0',
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'fv' : 'ND_TUPLE_FV',
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'hv' : 'ND_TUPLE_HV',
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'fvm' : 'ND_TUPLE_FVM',
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'hvm' : 'ND_TUPLE_HVM',
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'qvm' : 'ND_TUPLE_QVM',
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'ovm' : 'ND_TUPLE_OVM',
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'dup' : 'ND_TUPLE_DUP',
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'm128' : 'ND_TUPLE_M128',
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't1s8' : 'ND_TUPLE_T1S8',
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't1s16' : 'ND_TUPLE_T1S16',
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't1s' : 'ND_TUPLE_T1S',
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't1f' : 'ND_TUPLE_T1F',
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't2' : 'ND_TUPLE_T2',
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't4' : 'ND_TUPLE_T4',
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't8' : 'ND_TUPLE_T8',
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't1_4x' : 'ND_TUPLE_T1_4X',
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}
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extype = {
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None : '0',
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# SSE/AVX
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'1' : 'ND_EXT_1',
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'2' : 'ND_EXT_2',
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'3' : 'ND_EXT_3',
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'4' : 'ND_EXT_4',
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'5' : 'ND_EXT_5',
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'6' : 'ND_EXT_6',
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'7' : 'ND_EXT_7',
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'8' : 'ND_EXT_8',
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'9' : 'ND_EXT_9',
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'10' : 'ND_EXT_10',
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'11' : 'ND_EXT_11',
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'12' : 'ND_EXT_12',
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'13' : 'ND_EXT_13',
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# EVEX
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'E1' : 'ND_EXT_E1',
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'E1NF' : 'ND_EXT_E1NF',
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'E2' : 'ND_EXT_E2',
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'E3' : 'ND_EXT_E3',
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'E3NF' : 'ND_EXT_E3NF',
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'E4' : 'ND_EXT_E4',
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'E4nb' : 'ND_EXT_E4nb',
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'E4NF' : 'ND_EXT_E4NF',
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'E4NFnb': 'ND_EXT_E4NFnb',
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'E5' : 'ND_EXT_E5',
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'E5NF' : 'ND_EXT_E5NF',
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'E6' : 'ND_EXT_E6',
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'E6NF' : 'ND_EXT_E6NF',
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'E7NM' : 'ND_EXT_E7NM',
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'E9' : 'ND_EXT_E9',
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'E9NF' : 'ND_EXT_E9NF',
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'E10' : 'ND_EXT_E10',
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'E10NF' : 'ND_EXT_E10NF',
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'E11' : 'ND_EXT_E11',
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'E12' : 'ND_EXT_E12',
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'E12NP' : 'ND_EXT_E12NP',
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# Opmask
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'K20' : 'ND_EXT_K20',
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'K21' : 'ND_EXT_K21',
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# AMX
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'AMX_E1': 'ND_EXT_AMX_E1',
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'AMX_E2': 'ND_EXT_AMX_E2',
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'AMX_E3': 'ND_EXT_AMX_E3',
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'AMX_E4': 'ND_EXT_AMX_E4',
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'AMX_E5': 'ND_EXT_AMX_E5',
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'AMX_E6': 'ND_EXT_AMX_E6',
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}
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modes = {
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'r0' : 'ND_MOD_R0',
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'r1' : 'ND_MOD_R1',
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'r2' : 'ND_MOD_R2',
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'r3' : 'ND_MOD_R3',
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'real' : 'ND_MOD_REAL',
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'v8086' : 'ND_MOD_V8086',
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'prot' : 'ND_MOD_PROT',
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'compat': 'ND_MOD_COMPAT',
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'long' : 'ND_MOD_LONG',
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'smm' : 'ND_MOD_SMM',
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'sgx' : 'ND_MOD_SGX',
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'tsx' : 'ND_MOD_TSX',
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'vmxr' : 'ND_MOD_VMXR',
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'vmxn' : 'ND_MOD_VMXN',
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'vmxo' : 'ND_MOD_VMXO',
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}
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indexes = {
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"root" : 0,
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"None" : 0,
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None : 0,
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# modrm.mod
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"mem" : 0,
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"reg" : 1,
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# mandatory prefixes
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"NP" : 0,
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"66" : 1,
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"F3" : 2,
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"F2" : 3,
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# other prefixes
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"rex" : 1,
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"rexw" : 2,
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"64" : 3,
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"aF3" : 4,
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"rep" : 5,
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"sib" : 6,
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# Mode
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"m16" : 1,
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"m32" : 2,
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"m64" : 3,
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# Default data size
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"ds16" : 1,
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"ds32" : 2,
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"ds64" : 3,
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"dds64" : 4,
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"fds64" : 5,
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# Default address size
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"as16" : 1,
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"as32" : 2,
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"as64" : 3,
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# Vendor redirection.
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"any" : 0,
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"intel" : 1,
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"amd" : 2,
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"geode" : 3,
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"cyrix" : 4,
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}
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ilut = {
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"root" : ("ND_ILUT_ROOT", 1, "ND_TABLE"),
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"opcode" : ("ND_ILUT_OPCODE", 256, "ND_TABLE_OPCODE"),
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"opcode_3dnow" : ("ND_ILUT_OPCODE_3DNOW", 256, "ND_TABLE_OPCODE"),
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"modrmmod" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"),
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"modrmmodpost" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"),
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"modrmreg" : ("ND_ILUT_MODRM_REG", 8, "ND_TABLE_MODRM_REG"),
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"modrmrm" : ("ND_ILUT_MODRM_RM", 8, "ND_TABLE_MODRM_RM"),
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"mprefix" : ("ND_ILUT_MAN_PREFIX", 4, "ND_TABLE_MPREFIX"),
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"mode" : ("ND_ILUT_MODE", 4, "ND_TABLE_MODE"),
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"dsize" : ("ND_ILUT_DSIZE", 6, "ND_TABLE_DSIZE"),
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"asize" : ("ND_ILUT_ASIZE", 4, "ND_TABLE_ASIZE"),
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"auxiliary" : ("ND_ILUT_AUXILIARY", 6, "ND_TABLE_AUXILIARY"),
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"vendor" : ("ND_ILUT_VENDOR", 6, "ND_TABLE_VENDOR"),
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"mmmmm" : ("ND_ILUT_VEX_MMMMM", 32, "ND_TABLE_VEX_MMMMM"),
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"pp" : ("ND_ILUT_VEX_PP", 4, "ND_TABLE_VEX_PP"),
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"l" : ("ND_ILUT_VEX_L", 4, "ND_TABLE_VEX_L"),
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"w" : ("ND_ILUT_VEX_W", 2, "ND_TABLE_VEX_W"),
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}
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mnemonics = []
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mnemonics_prefix = []
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instructions = []
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prefixes = []
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features = []
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#
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# Convert one operand into it's C/C++ representation.
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#
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def cdef_operand(self):
|
|
return "OP(%s, %s, %s, %s, %d)" % (optype[self.Type], opsize[self.Size], \
|
|
'|'.join([opflags[x] for x in self.Flags] + [accessmap[self.Access]]) or '0', \
|
|
'|'.join([opdecorators[x] for x in self.Decorators]) or 0, self.Block)
|
|
|
|
disasmlib.Operand.cdef = cdef_operand
|
|
|
|
|
|
#
|
|
# Convert one instruction into it's C/C++ representation.
|
|
#
|
|
def cdef_instruction(self):
|
|
c = ''
|
|
|
|
c += ' // Pos:%d Instruction:"%s" Encoding:"%s"/"%s"\n' % \
|
|
(self.Icount, self.__str__(), self.RawEnc, ''.join([x.Encoding for x in self.ExpOps]).replace('S', ''))
|
|
|
|
c += ' {\n '
|
|
|
|
# Add the instruction class
|
|
c += 'ND_INS_' + self.Class + ', '
|
|
|
|
# Add the instruction type
|
|
c += 'ND_CAT_' + self.Category + ', '
|
|
|
|
# Add the instruction set
|
|
c += 'ND_SET_' + self.Set + ', '
|
|
|
|
# Add the mneomonic index.
|
|
c += '%d, ' % (mnemonics.index(self.Mnemonic))
|
|
|
|
c += '\n '
|
|
|
|
|
|
# Add the valid modes map.
|
|
all = True
|
|
for m in modes:
|
|
if m not in self.Modes:
|
|
all = False
|
|
if all:
|
|
c += 'ND_MOD_ANY, '
|
|
else:
|
|
c += '|'.join([modes[m] for m in self.Modes]) + ', '
|
|
|
|
c += '\n '
|
|
|
|
# Add the prefixes map.
|
|
c += '|'.join([prefixes_map[x] for x in self.Prefmap] or '0') + ', '
|
|
|
|
# Add the decorators map.
|
|
c += '|'.join([decorators_map[x] for x in self.DecoFlags] or '0') + ', '
|
|
|
|
# Add the tuple type and the explicit operands count.
|
|
c += 'ND_OPS_CNT(%d, %d), ' % (len(self.ExpOps), len(self.ImpOps))
|
|
|
|
exclass = None
|
|
if self.ExClass:
|
|
if self.ExClass in ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13']:
|
|
exclass = 'ND_EXC_SSE_AVX'
|
|
elif self.ExClass in ['K20', 'K21']:
|
|
exclass = 'ND_EXC_OPMASK'
|
|
elif self.ExClass.startswith('AMX_'):
|
|
exclass = 'ND_EXC_AMX'
|
|
else:
|
|
exclass = 'ND_EXC_EVEX'
|
|
|
|
if self.Evex:
|
|
# EVEX encoded instructions, store the tuple type.
|
|
c += '%s, ' % (tuples[self.Tuple])
|
|
else:
|
|
c += '0, '
|
|
|
|
# Store exception type & class, if any.
|
|
if exclass:
|
|
c += '%s, %s, ' % (extype[self.ExClass], exclass)
|
|
else:
|
|
c += '0, 0, '
|
|
|
|
# Add the FPU flags access, if the instruction is fpu.
|
|
if self.Set == 'X87':
|
|
value = 0
|
|
acc = { '0': 0, '1': 1, 'm': 2, 'u': 3 }
|
|
for i in range(0, 4):
|
|
value |= acc[self.FpuFlags[i]] << (i * 2)
|
|
c += '0x%02x, ' % value
|
|
else:
|
|
c += '0, '
|
|
|
|
# The 2 reserved fields.
|
|
c += '0, 0, '
|
|
|
|
# Add the instruction flags
|
|
fs = '|'.join([flags[x] for x in self.Flags if x != 'nil' and not x.startswith('OP1') and not x.startswith('OP2')\
|
|
and not x.startswith('OP3') and not x.startswith('OP4')\
|
|
and not x.startswith('OP5') and not x.startswith('OP6')\
|
|
]) or 0
|
|
|
|
c += '%s, ' % fs
|
|
|
|
# Store the CPUID flag, if any
|
|
flg = "0"
|
|
for feat in features:
|
|
if feat.Name == self.Id:
|
|
flg = "ND_CFF_%s" % feat.Name
|
|
c += "%s, " % flg
|
|
|
|
# Store the accessed flags, if any.
|
|
for m in ['t', 'm', '1', '0']:
|
|
flg = "0"
|
|
dst = self.RevFlagsAccess[m]
|
|
if m == '1' or m == '0':
|
|
dst = dst + self.RevFlagsAccess['u']
|
|
for f in dst:
|
|
flg += '|REG_RFLAG_%s' % f.upper()
|
|
c += "\n %s," % flg
|
|
|
|
# Add the instruction operands
|
|
for op in self.ExpOps + self.ImpOps:
|
|
c += "\n " + op.cdef() + ", "
|
|
|
|
c += '\n }'
|
|
|
|
return c
|
|
|
|
disasmlib.Instruction.cdef = cdef_instruction
|
|
|
|
|
|
#
|
|
# Initially, t is an empty hash-table.
|
|
#
|
|
def group_instructions(ilist):
|
|
d = { }
|
|
is3dnow = False
|
|
priorities = ["opcode", "vendor", "modrmmod", "modrmreg", "modrmmodpost", "modrmrm", "mprefix", "mode", "dsize", \
|
|
"asize", "auxiliary", "_"]
|
|
|
|
for i in ilist:
|
|
if '3DNOW' in i.Flags:
|
|
is3dnow = True
|
|
else:
|
|
is3dnow = False
|
|
|
|
if i.Spec["opcodes"]:
|
|
if is3dnow:
|
|
d["__TYPE__"] = "opcode_3dnow"
|
|
else:
|
|
d["__TYPE__"] = "opcode"
|
|
elif i.Spec["mpre"] and i.ModrmRedirAfterMpref:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]:
|
|
d["__TYPE__"] = "mprefix"
|
|
elif i.Spec["vendor"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-10:]:
|
|
d["__TYPE__"] = "vendor"
|
|
elif i.Spec["modrm"]["mod"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-9:]:
|
|
d["__TYPE__"] = "modrmmod"
|
|
elif i.Spec["modrm"]["reg"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-8:]:
|
|
d["__TYPE__"] = "modrmreg"
|
|
elif i.Spec["modrm"]["modpost"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-7:]:
|
|
d["__TYPE__"] = "modrmmodpost"
|
|
elif i.Spec["modrm"]["rm"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-6:]:
|
|
d["__TYPE__"] = "modrmrm"
|
|
elif i.Spec["mpre"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-5:]:
|
|
d["__TYPE__"] = "mprefix"
|
|
elif i.Spec["mode"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-4:]:
|
|
d["__TYPE__"] = "mode"
|
|
elif i.Spec["dsize"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-3:]:
|
|
d["__TYPE__"] = "dsize"
|
|
elif i.Spec["asize"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-2:]:
|
|
d["__TYPE__"] = "asize"
|
|
elif i.Spec["opre"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]:
|
|
d["__TYPE__"] = "auxiliary"
|
|
elif len(ilist) == 1:
|
|
return ilist[0]
|
|
|
|
|
|
for i in ilist:
|
|
if d["__TYPE__"] in ["opcode", "opcode_3dnow"]:
|
|
# Opcode redirection, add the next opcode to the hash, and remove it from the spec.
|
|
if int(i.Spec["opcodes"][0], 16) not in d:
|
|
d[int(i.Spec["opcodes"][0], 16)] = [i]
|
|
else:
|
|
d[int(i.Spec["opcodes"][0], 16)].append(i)
|
|
|
|
# Remove the opcode for this instruction.
|
|
del i.Spec["opcodes"][0]
|
|
elif d["__TYPE__"] == "modrmmod":
|
|
if not i.Spec["modrm"]["mod"]:
|
|
if "mem" not in d:
|
|
d["mem"] = [i]
|
|
else:
|
|
d["mem"].append(i)
|
|
|
|
if "reg" not in d:
|
|
d["reg"] = [copy.deepcopy(i)]
|
|
else:
|
|
d["reg"].append(copy.deepcopy(i))
|
|
else:
|
|
if i.Spec["modrm"]["mod"] not in d:
|
|
d[i.Spec["modrm"]["mod"]] = [i]
|
|
else:
|
|
d[i.Spec["modrm"]["mod"]].append(i)
|
|
# Remove the mod specifier.
|
|
i.Spec["modrm"]["mod"] = None
|
|
elif d["__TYPE__"] == "modrmreg":
|
|
if int(i.Spec["modrm"]["reg"]) not in d:
|
|
d[int(i.Spec["modrm"]["reg"])] = [i]
|
|
else:
|
|
d[int(i.Spec["modrm"]["reg"])].append(i)
|
|
# Remove the reg specifier
|
|
i.Spec["modrm"]["reg"] = None
|
|
elif d["__TYPE__"] == "modrmmodpost":
|
|
if not i.Spec["modrm"]["modpost"]:
|
|
if "mem" not in d:
|
|
d["mem"] = [i]
|
|
else:
|
|
d["mem"].append(i)
|
|
|
|
if "reg" not in d:
|
|
d["reg"] = [copy.deepcopy(i)]
|
|
else:
|
|
d["reg"].append(copy.deepcopy(i))
|
|
else:
|
|
if i.Spec["modrm"]["modpost"] not in d:
|
|
d[i.Spec["modrm"]["modpost"]] = [i]
|
|
else:
|
|
d[i.Spec["modrm"]["modpost"]].append(i)
|
|
# Remove the modpost specifier.
|
|
i.Spec["modrm"]["modpost"] = None
|
|
elif d["__TYPE__"] == "modrmrm":
|
|
if int(i.Spec["modrm"]["rm"]) not in d:
|
|
d[int(i.Spec["modrm"]["rm"])] = [i]
|
|
else:
|
|
d[int(i.Spec["modrm"]["rm"])].append(i)
|
|
# Remove the reg specifier
|
|
i.Spec["modrm"]["rm"] = None
|
|
elif d["__TYPE__"] == "mprefix":
|
|
if not i.Spec["mpre"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["mpre"][0]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the prefix from the list.
|
|
if p != "None":
|
|
del i.Spec["mpre"][0]
|
|
elif d["__TYPE__"] == "mode":
|
|
if not i.Spec["mode"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["mode"][0]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the auxiliary redirector
|
|
if p != "None":
|
|
del i.Spec["mode"][0]
|
|
elif d["__TYPE__"] == "dsize":
|
|
if not i.Spec["dsize"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["dsize"][0]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the auxiliary redirector
|
|
if p != "None":
|
|
del i.Spec["dsize"][0]
|
|
elif d["__TYPE__"] == "asize":
|
|
if not i.Spec["asize"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["asize"][0]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the auxiliary redirector
|
|
if p != "None":
|
|
del i.Spec["asize"][0]
|
|
elif d["__TYPE__"] == "auxiliary":
|
|
if not i.Spec["opre"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["opre"][0]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the auxiliary redirector
|
|
if p != "None":
|
|
del i.Spec["opre"][0]
|
|
elif d["__TYPE__"] == "vendor":
|
|
if not i.Spec["vendor"]:
|
|
p = "None"
|
|
else:
|
|
p = i.Spec["vendor"]
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the vendor redirector
|
|
if p != "None":
|
|
i.Spec["vendor"] = None
|
|
else:
|
|
print("Don't know what to do!")
|
|
raise Exception("WTF???")
|
|
|
|
return d
|
|
|
|
|
|
|
|
def group_instructions_vex_xop_evex(ilist):
|
|
d = { }
|
|
|
|
for i in ilist:
|
|
if i.Spec["mmmmm"]:
|
|
d["__TYPE__"] = "mmmmm"
|
|
elif i.Spec["opcodes"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "pp", "modrmrm", "modrmmodpost", "modrmreg", \
|
|
"modrmmod"]:
|
|
d["__TYPE__"] = "opcode"
|
|
elif i.Spec["pp"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]:
|
|
d["__TYPE__"] = "pp"
|
|
elif i.Spec["modrm"]["mod"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]:
|
|
d["__TYPE__"] = "modrmmod"
|
|
elif i.Spec["modrm"]["reg"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost"]:
|
|
d["__TYPE__"] = "modrmreg"
|
|
elif i.Spec["modrm"]["modpost"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm"]:
|
|
d["__TYPE__"] = "modrmmodpost"
|
|
elif i.Spec["modrm"]["rm"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l"]:
|
|
d["__TYPE__"] = "modrmrm"
|
|
|
|
elif i.Spec["l"]:
|
|
if "__TYPE__" not in d or d["__TYPE__"] in ["w"]:
|
|
d["__TYPE__"] = "l"
|
|
elif i.Spec["w"]:
|
|
if "__TYPE__" not in d:
|
|
d["__TYPE__"] = "w"
|
|
elif len(ilist) == 1:
|
|
return ilist[0]
|
|
|
|
|
|
for i in ilist:
|
|
if d["__TYPE__"] == "mmmmm":
|
|
if int(i.Spec["mmmmm"], 16) not in d:
|
|
d[int(i.Spec["mmmmm"], 16)] = [i]
|
|
else:
|
|
d[int(i.Spec["mmmmm"], 16)].append(i)
|
|
i.Spec["mmmmm"] = None
|
|
elif d["__TYPE__"] == "opcode":
|
|
# Opcode redirection, add the next opcode to the hash, and remove it from the spec.
|
|
if int(i.Spec["opcodes"][0], 16) not in d:
|
|
d[int(i.Spec["opcodes"][0], 16)] = [i]
|
|
else:
|
|
d[int(i.Spec["opcodes"][0], 16)].append(i)
|
|
# Remove the opcode for this instruction.
|
|
del i.Spec["opcodes"][0]
|
|
elif d["__TYPE__"] == "modrmmod":
|
|
if not i.Spec["modrm"]["mod"]:
|
|
if "mem" not in d:
|
|
d["mem"] = [i]
|
|
else:
|
|
d["mem"].append(i)
|
|
|
|
if "reg" not in d:
|
|
d["reg"] = [copy.deepcopy(i)]
|
|
else:
|
|
d["reg"].append(copy.deepcopy(i))
|
|
else:
|
|
if i.Spec["modrm"]["mod"] not in d:
|
|
d[i.Spec["modrm"]["mod"]] = [i]
|
|
else:
|
|
d[i.Spec["modrm"]["mod"]].append(i)
|
|
# Remove the mod specifier.
|
|
i.Spec["modrm"]["mod"] = None
|
|
elif d["__TYPE__"] == "modrmreg":
|
|
if int(i.Spec["modrm"]["reg"]) not in d:
|
|
d[int(i.Spec["modrm"]["reg"])] = [i]
|
|
else:
|
|
d[int(i.Spec["modrm"]["reg"])].append(i)
|
|
# Remove the reg specifier
|
|
i.Spec["modrm"]["reg"] = None
|
|
elif d["__TYPE__"] == "modrmmodpost":
|
|
if not i.Spec["modrm"]["modpost"]:
|
|
if "mem" not in d:
|
|
d["mem"] = [i]
|
|
else:
|
|
d["mem"].append(i)
|
|
|
|
if "reg" not in d:
|
|
d["reg"] = [copy.deepcopy(i)]
|
|
else:
|
|
d["reg"].append(copy.deepcopy(i))
|
|
else:
|
|
if i.Spec["modrm"]["modpost"] not in d:
|
|
d[i.Spec["modrm"]["modpost"]] = [i]
|
|
else:
|
|
d[i.Spec["modrm"]["modpost"]].append(i)
|
|
# Remove the modpost specifier.
|
|
i.Spec["modrm"]["modpost"] = None
|
|
elif d["__TYPE__"] == "modrmrm":
|
|
if int(i.Spec["modrm"]["rm"]) not in d:
|
|
d[int(i.Spec["modrm"]["rm"])] = [i]
|
|
else:
|
|
d[int(i.Spec["modrm"]["rm"])].append(i)
|
|
# Remove the reg specifier
|
|
i.Spec["modrm"]["rm"] = None
|
|
elif d["__TYPE__"] == "pp":
|
|
p = int(i.Spec["pp"])
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the prefix from the list.
|
|
i.Spec["pp"] = None
|
|
elif d["__TYPE__"] == "l":
|
|
p = int(i.Spec["l"])
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the prefix from the list.
|
|
i.Spec["l"] = None
|
|
elif d["__TYPE__"] == "w":
|
|
p = int(i.Spec["w"])
|
|
if p not in d:
|
|
d[p] = [i]
|
|
else:
|
|
d[p].append(i)
|
|
# Remove the prefix from the list.
|
|
i.Spec["w"] = None
|
|
else:
|
|
print("Don't know what to do!")
|
|
raise Exception("WTF???")
|
|
|
|
return d
|
|
|
|
|
|
def build_hash_tree2(t, cbk):
|
|
for k in t:
|
|
if type(disasmlib.Instruction) == type(t[k]):
|
|
# Instruction, leaf, we're done.
|
|
continue
|
|
elif type([]) == type(t[k]):
|
|
# List, group the instructions, and recurse.
|
|
t[k] = cbk(t[k])
|
|
|
|
if type({}) == type(t[k]):
|
|
build_hash_tree2(t[k], cbk)
|
|
|
|
|
|
def dump_hash_tree2(t, level = 0):
|
|
if type(t) == type({}):
|
|
for h in t:
|
|
if h == "__TYPE__":
|
|
continue
|
|
print("%s %s (type: %s)" % (" " * level, h, t["__TYPE__"]))
|
|
dump_hash_tree2(t[h], level + 1)
|
|
else:
|
|
print(" " * level, t)
|
|
|
|
|
|
#
|
|
#
|
|
#
|
|
def generate_translations2(instructions):
|
|
table_st = []
|
|
table_xop = []
|
|
table_vex = []
|
|
table_evex = []
|
|
|
|
hash_st = {}
|
|
hash_vex = {}
|
|
hash_xop = {}
|
|
hash_evex = {}
|
|
|
|
# Distribute each instruction type into its own table.
|
|
for i in instructions:
|
|
if i.Vex:
|
|
table_vex.append(i)
|
|
elif i.Xop:
|
|
table_xop.append(i)
|
|
elif i.Evex:
|
|
table_evex.append(i)
|
|
else:
|
|
table_st.append(i)
|
|
|
|
hash_st["__TYPE__"] = "root"
|
|
hash_st["root"] = table_st
|
|
build_hash_tree2(hash_st, group_instructions)
|
|
|
|
hash_vex["__TYPE__"] = "root"
|
|
hash_vex["root"] = table_vex
|
|
build_hash_tree2(hash_vex, group_instructions_vex_xop_evex)
|
|
|
|
hash_xop["__TYPE__"] = "root"
|
|
hash_xop["root"] = table_xop
|
|
build_hash_tree2(hash_xop, group_instructions_vex_xop_evex)
|
|
|
|
hash_evex["__TYPE__"] = "root"
|
|
hash_evex["root"] = table_evex
|
|
build_hash_tree2(hash_evex, group_instructions_vex_xop_evex)
|
|
|
|
# Dump'em!
|
|
#print "###########################################################################################################"
|
|
#dump_hash_tree2(hash_st)
|
|
print('Writing the table_root.h file...')
|
|
f = open(r'../bddisasm/include/table_root.h', 'wt')
|
|
f.write("#ifndef _TABLE_ROOT_H_\n")
|
|
f.write("#define _TABLE_ROOT_H_\n\n")
|
|
dump_translation_tree_c(hash_st, 'gRootTable', f)
|
|
f.write("\n#endif\n\n")
|
|
f.close()
|
|
#print "###########################################################################################################"
|
|
#dump_hash_tree2(hash_vex)
|
|
print('Writing the table_vex.h file...')
|
|
f = open(r'../bddisasm/include/table_vex.h', 'wt')
|
|
f.write("#ifndef _TABLE_VEX_H_\n")
|
|
f.write("#define _TABLE_VEX_H_\n\n")
|
|
dump_translation_tree_c(hash_vex, 'gVexTable', f)
|
|
f.write("\n#endif\n\n")
|
|
f.close()
|
|
#print "###########################################################################################################"
|
|
#dump_hash_tree2(hash_xop)
|
|
print('Writing the table_xop.h file...')
|
|
f = open(r'../bddisasm/include/table_xop.h', 'wt')
|
|
f.write("#ifndef _TABLE_XOP_H_\n")
|
|
f.write("#define _TABLE_XOP_H_\n\n")
|
|
dump_translation_tree_c(hash_xop, 'gXopTable', f)
|
|
f.write("\n#endif\n\n")
|
|
f.close()
|
|
#print "###########################################################################################################"
|
|
#dump_hash_tree2(hash_evex)
|
|
print('Writing the table_evex.h file...')
|
|
f = open(r'../bddisasm/include/table_evex.h', 'wt')
|
|
f.write("#ifndef _TABLE_EVEX_H_\n")
|
|
f.write("#define _TABLE_EVEX_H_\n\n")
|
|
dump_translation_tree_c(hash_evex, 'gEvexTable', f)
|
|
f.write("\n#endif\n\n")
|
|
f.close()
|
|
#print "###########################################################################################################"
|
|
|
|
return [hash_st, hash_vex, hash_xop, hash_evex]
|
|
|
|
|
|
def generate_mnemonics(instructions):
|
|
mnemonics = []
|
|
|
|
for i in instructions:
|
|
mnemonics.append(i.Mnemonic)
|
|
|
|
return sorted(set(mnemonics))
|
|
|
|
def generate_constants(lst, pre = False):
|
|
constants = []
|
|
|
|
for i in lst:
|
|
if pre:
|
|
constants.append('ND_PRE_' + i.Mnemonic)
|
|
else:
|
|
constants.append('ND_INS_' + i.Class)
|
|
|
|
return sorted(set(constants))
|
|
|
|
def generate_constants2(instructions):
|
|
constants_sets, constants_types = [], []
|
|
|
|
for i in instructions:
|
|
constants_sets.append('ND_SET_' + i.Set)
|
|
constants_types.append('ND_CAT_' + i.Category)
|
|
|
|
return sorted(set(constants_sets)), sorted(set(constants_types))
|
|
|
|
def dump_mnemonics(mnemonics, prefixes, fname):
|
|
f = open(fname, 'wt')
|
|
f.write('#ifndef _MNEMONICS_H_\n')
|
|
f.write('#define _MNEMONICS_H_\n')
|
|
f.write('\n')
|
|
f.write('const char *gMnemonics[%d] = \n' % len(mnemonics))
|
|
f.write('{\n')
|
|
f.write(' ')
|
|
|
|
i = 0
|
|
ln = 0
|
|
for m in mnemonics:
|
|
f.write('"%s", ' % m)
|
|
ln += len(m) + 4
|
|
i += 1
|
|
if ln > 60:
|
|
ln = 0
|
|
f.write('\n ')
|
|
|
|
f.write('\n};\n\n\n')
|
|
|
|
f.write('const char *gPrefixes[%d] = \n' % len(prefixes))
|
|
f.write('{\n')
|
|
f.write(' ')
|
|
|
|
i = 0
|
|
for p in prefixes:
|
|
f.write('"%s", ' % p)
|
|
i += 1
|
|
if i % 8 == 0:
|
|
f.write('\n ')
|
|
|
|
f.write('\n};\n\n#endif\n\n')
|
|
f.close()
|
|
|
|
def dump_constants(constants, prefixes, constants_sets, constants_types, fname):
|
|
f = open(fname, 'wt')
|
|
f.write('//\n')
|
|
f.write('// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY!\n')
|
|
f.write('//\n\n')
|
|
f.write('#ifndef _CONSTANTS_H_\n')
|
|
f.write('#define _CONSTANTS_H_\n\n')
|
|
f.write('\n')
|
|
f.write('typedef enum _ND_INS_CLASS\n')
|
|
f.write('{\n')
|
|
f.write(' ND_INS_INVALID = 0,\n')
|
|
|
|
for c in constants:
|
|
f.write(' %s,\n' % c)
|
|
|
|
f.write('\n} ND_INS_CLASS;\n\n\n')
|
|
|
|
# Now the instruction sets.
|
|
f.write('typedef enum _ND_INS_SET\n')
|
|
f.write('{\n')
|
|
f.write(' ND_SET_INVALID = 0,\n')
|
|
for c in constants_sets:
|
|
f.write(' %s,\n' % c)
|
|
f.write('\n} ND_INS_SET;\n\n\n')
|
|
|
|
# Now the instruction types.
|
|
f.write('typedef enum _ND_INS_TYPE\n')
|
|
f.write('{\n')
|
|
f.write(' ND_CAT_INVALID = 0,\n')
|
|
for c in constants_types:
|
|
f.write(' %s,\n' % c)
|
|
f.write('\n} ND_INS_CATEGORY;\n\n\n')
|
|
|
|
# Done!
|
|
f.write('\n#endif\n')
|
|
|
|
f.close()
|
|
|
|
def dump_tree(translations, level = 0):
|
|
if type(translations) != type([]):
|
|
print('%s%s' % (level * ' ', translations))
|
|
else:
|
|
for i in range(0, len(translations), 1):
|
|
if len(translations) == 1:
|
|
dump_tree(translations[i], level + 1)
|
|
else:
|
|
dump_tree(translations[i], level + 2)
|
|
|
|
def generate_master_table(instructions, fname):
|
|
f = open(fname, 'wt')
|
|
f.write('//\n')
|
|
f.write('// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY!\n')
|
|
f.write('//\n\n')
|
|
f.write('#ifndef _INSTRUCTIONS_H_\n')
|
|
f.write('#define _INSTRUCTIONS_H_\n')
|
|
f.write('\n')
|
|
flags = []
|
|
f.write('const ND_INSTRUCTION gInstructions[%s] = \n' % len(instructions))
|
|
f.write('{\n')
|
|
for i in instructions:
|
|
f.write('%s, \n\n' % i.cdef())
|
|
f.write('\n};\n')
|
|
f.write('\n#endif\n')
|
|
f.close()
|
|
|
|
|
|
def dump_translation_tree_c(t, hname, f):
|
|
if type(t) == type({}):
|
|
pointers = []
|
|
|
|
ttype = t["__TYPE__"]
|
|
|
|
for x in range(0, ilut[ttype][1]): pointers.append(None)
|
|
|
|
tname = '%s_%s' % (hname, ttype)
|
|
|
|
res = 'const %s %s = \n' % (ilut[ttype][2], tname)
|
|
res += '{\n'
|
|
res += ' %s,\n' % ilut[ttype][0]
|
|
res += ' { \n'
|
|
|
|
for h in t:
|
|
if h == "__TYPE__":
|
|
continue
|
|
|
|
if type(0) == type(h):
|
|
name = dump_translation_tree_c(t[h], hname + '_%02x' % h, f)
|
|
else:
|
|
name = dump_translation_tree_c(t[h], hname + '_%s' % h, f)
|
|
|
|
if ttype in ["opcode", "opcode_3dnow", "mmmmm", "pp", "l", "w", "modrmreg", "modrmrm"]:
|
|
index = h
|
|
else:
|
|
index = indexes[h]
|
|
|
|
try:
|
|
pointers[index] = name
|
|
except:
|
|
print(index, name)
|
|
print("fail fail fail", index)
|
|
|
|
i = 0
|
|
for p in pointers:
|
|
if not p:
|
|
res += ' /* %02x */ NULL,\n' % i
|
|
else:
|
|
res += ' /* %02x */ (const void *)&%s,\n' % (i, p)
|
|
i += 1
|
|
|
|
res += ' }\n'
|
|
res += '};\n\n'
|
|
|
|
if ttype == "root":
|
|
f.write("const PND_TABLE %s = (const PND_TABLE)&%s;\n\n" % (hname, name))
|
|
else:
|
|
f.write(res)
|
|
|
|
return tname
|
|
else:
|
|
# Instruction, construct a dummy table that directly points to the instruction.
|
|
name = '%s_leaf' % hname
|
|
res = 'const ND_TABLE_INSTRUCTION %s = \n' % name
|
|
res += '{\n'
|
|
res += ' ND_ILUT_INSTRUCTION,\n'
|
|
res += ' (const void *)&gInstructions[%d]\n' % t.Icount
|
|
res += '};\n\n'
|
|
f.write(res)
|
|
return name
|
|
|
|
def generate_features(features, fname):
|
|
f = open(fname, 'wt')
|
|
f.write('#ifndef _CPUID_FLAGS_H_\n')
|
|
f.write('#define _CPUID_FLAGS_H_\n')
|
|
|
|
f.write('\n')
|
|
f.write('#define ND_CFF_NO_LEAF 0xFFFFFFFF\n')
|
|
f.write('#define ND_CFF_NO_SUBLEAF 0x00FFFFFF\n')
|
|
f.write('\n')
|
|
f.write('\n')
|
|
f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59))\n')
|
|
f.write('\n')
|
|
|
|
for c in features:
|
|
f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'REG_' + c.Reg, c.Bit))
|
|
|
|
f.write('\n')
|
|
|
|
f.write('#endif // _CPUID_FLAGS_H_\n')
|
|
|
|
#
|
|
# =============================================================================
|
|
# Main
|
|
# =============================================================================
|
|
#
|
|
if __name__ == "__main__":
|
|
if len(sys.argv) < 2:
|
|
print('Usage: %s defs-file' % os.path.basename(sys.argv[0]))
|
|
sys.exit(-1)
|
|
|
|
# Extract the flags.
|
|
print('Loading flags access templates...')
|
|
flagsaccess = disasmlib.parse_flags_file('%s/flags.dat' % sys.argv[1])
|
|
|
|
# Extact the CPUID features.
|
|
print('Loading CPUID feature flags templates...')
|
|
features = disasmlib.parse_cff_file('%s/cpuid.dat' % sys.argv[1])
|
|
|
|
# Extract the prefixes.
|
|
print('Loading prefixes...')
|
|
prefixes = disasmlib.parse_pre_file('%s/prefixes.dat' % sys.argv[1])
|
|
|
|
# Extract the valid modes.
|
|
print('Loading CPU operating modes templates...')
|
|
insmodes = disasmlib.parse_modess_file('%s/modes.dat' % sys.argv[1])
|
|
|
|
# Extract the instructions.
|
|
for fn in glob.glob('%s/table*.dat' % sys.argv[1]):
|
|
print('Loading instructions from %s...' % fn)
|
|
instructions = instructions + disasmlib.parse_ins_file(fn, flagsaccess, features, insmodes)
|
|
|
|
# Sort the instructions.
|
|
instructions = sorted(instructions, key = lambda x: x.Mnemonic)
|
|
for i in range(0, len(instructions)):
|
|
instructions[i].Icount = i
|
|
|
|
# Generate the translation tree
|
|
translations = generate_translations2(instructions)
|
|
|
|
# Generate the mnemonics
|
|
mnemonics = generate_mnemonics(instructions)
|
|
mnemonics_prefixes = generate_mnemonics(prefixes)
|
|
|
|
# Generate the constants
|
|
constants = generate_constants(instructions)
|
|
constants_prefixes = generate_constants(prefixes, True)
|
|
constants_sets, constants_types = generate_constants2(instructions)
|
|
|
|
#
|
|
# Dump all data to files.
|
|
#
|
|
|
|
# Dump the mnemonics
|
|
print('Writing the mnemonics.h file...')
|
|
dump_mnemonics(mnemonics, mnemonics_prefixes, r'../bddisasm/include/mnemonics.h')
|
|
|
|
# Dump the instruction constants
|
|
print('Writing the constants.h (instruction definitions) file...')
|
|
dump_constants(constants, constants_prefixes, constants_sets, constants_types, r'../inc/constants.h')
|
|
|
|
print('Writing the instructions.h (main instruction database) file...')
|
|
generate_master_table(instructions, r'../bddisasm/include/instructions.h')
|
|
|
|
print('Writing the cpuidflags.h (CPUID feature flags) file...')
|
|
generate_features(features, r'../inc/cpuidflags.h')
|
|
|
|
print('Instruction succesfully parsed & header files generated!')
|