mirror of
https://github.com/bitdefender/bddisasm.git
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108 lines
8.1 KiB
C
108 lines
8.1 KiB
C
#ifndef _CPUID_FLAGS_H_
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#define _CPUID_FLAGS_H_
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#define ND_CFF_NO_LEAF 0xFFFFFFFF
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#define ND_CFF_NO_SUBLEAF 0x00FFFFFF
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#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59))
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#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 0)
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#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 5)
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#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 8)
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#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 11)
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#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 15)
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#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 19)
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#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 23)
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#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 24)
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#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 25)
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#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 26)
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#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 0)
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#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 1)
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#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 3)
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#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 5)
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#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 6)
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#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 9)
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#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 12)
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#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 19)
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#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 20)
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#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 22)
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#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 23)
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#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 25)
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#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 26)
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#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 28)
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#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 29)
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#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 30)
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#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, REG_EBX, 0)
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#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, REG_EBX, 2)
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#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, REG_EBX, 3)
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#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, REG_EBX, 4)
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#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 5)
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#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 8)
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#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, REG_EBX, 10)
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#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, REG_EBX, 11)
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#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, REG_EBX, 14)
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#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, REG_EBX, 16)
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#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, REG_EBX, 17)
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#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, REG_EBX, 18)
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#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, REG_EBX, 19)
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#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, REG_EBX, 20)
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#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, REG_EBX, 21)
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#define ND_CFF_PCOMMIT ND_CFF(0x00000007, 0x00000000, REG_EBX, 22)
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#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, REG_EBX, 23)
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#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, REG_EBX, 24)
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#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, REG_EBX, 26)
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#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, REG_EBX, 27)
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#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, REG_EBX, 28)
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#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, REG_EBX, 29)
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#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, REG_EBX, 30)
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#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, REG_ECX, 0)
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#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, REG_ECX, 1)
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#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, REG_ECX, 3)
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#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, REG_ECX, 5)
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#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, REG_ECX, 6)
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#define ND_CFF_CET ND_CFF(0x00000007, 0x00000000, REG_ECX, 7)
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#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 8)
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#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, REG_ECX, 9)
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#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 10)
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#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 11)
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#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, REG_ECX, 12)
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#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 14)
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#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, REG_ECX, 22)
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#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, REG_ECX, 25)
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#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, REG_ECX, 27)
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#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, REG_ECX, 28)
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#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, REG_ECX, 29)
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#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, REG_EDX, 2)
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#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, REG_EDX, 3)
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#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, REG_EDX, 8)
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#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, REG_EDX, 14)
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#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, REG_EDX, 16)
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#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, REG_EDX, 18)
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#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, REG_EDX, 22)
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#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, REG_EDX, 24)
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#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, REG_EDX, 25)
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#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, REG_EAX, 5)
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#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, REG_EAX, 0)
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#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, REG_EAX, 1)
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#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, REG_EAX, 3)
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#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, REG_EBX, 4)
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#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 2)
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#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 5)
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#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 6)
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#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 8)
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#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11)
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#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11)
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#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 15)
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#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 16)
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#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 21)
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#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 24)
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#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 27)
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#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 31)
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#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 9)
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#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 4)
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#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 8)
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#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, REG_EAX, 4)
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#endif // _CPUID_FLAGS_H_
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