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bddisasm/bindings/rsbddisasm
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vlutas c282f06215
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 
* Add support for SIMD exceptions reporting in INSTRUX.
* Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4.

Co-authored-by: ianichitei (Rust bindings)
2024-11-07 12:15:29 +02:00
..
bddisasm Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
bddisasm-sys rsbddisasm: Update bindgen to 0.62.0 2024-02-20 14:46:59 +02:00
Cargo.toml Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
fix_symlinks.sh Updates Rust binding to the latest version. 2022-01-05 14:17:13 +02:00
README.md Move rsbddisasm to the bindings directory 2021-10-20 10:03:16 +03:00
update_ins.py BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00

README.md

bddisasm Rust bindings

Build

Run cargo build or cargo build --release.

Directory structure

bddisasm-sys

This crate uses the *-sys crate convention and links with libbddisasm, exposing a raw, low-level, interface.

bddisasm

This crate aims to offer a higher-level interface over bddisasm-sys.

Parts of it are auto-generated, with slight manual changes (for example, the Mnemonic enum and related functions).

TODO

  • encode registers, not just the register index (for example, instead of Gpr we should have Gpr::Rax, Gpr::Eax, etc)
  • more documentation for the operand module, with examples on how to work wit h each operand type
  • more examples for cpuid
  • more examples for cpu_modes
  • an API to check if an instruction is supported with certain CPU modes on or off (currently a user has to manually check the CpuModes structure)
  • implement Display for more types (especially those in operand)
  • remove the bindgen dev dependency? See this issue as to why we may want to do that
  • better directory structure