mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-11-24 00:18:18 +00:00
c282f06215
* Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
55 lines
3.2 KiB
NASM
55 lines
3.2 KiB
NASM
bits 64
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db 0xc4, 0xe2, 0x78, 0x49, 0x00 ; LDTILECFG zmmword ptr [rax]
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db 0xc4, 0xe2, 0x79, 0x49, 0x00 ; STTILECFG zmmword ptr [rax]
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db 0xc4, 0xe2, 0x7A, 0x5c, 0xF4 ; TDPBF16PS tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x78, 0x5e, 0xF4 ; TDPBUUD tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x79, 0x5e, 0xF4 ; TDPBUSD tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x7A, 0x5e, 0xF4 ; TDPBSUD tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x7B, 0x5e, 0xF4 ; TDPBSSD tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x79, 0x4b, 0x04, 0x00 ; TILELOADDT1 tmm0, [rax+rax]
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db 0xc4, 0xe2, 0x7b, 0x4b, 0x04, 0x00 ; TILELOADD tmm0, [rax+rax]
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db 0xc4, 0xe2, 0x7a, 0x4b, 0x04, 0x00 ; TILESTORED tmm0, [rax+rax]
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db 0xc4, 0xe2, 0x79, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADDT1 tmm0, [rax+rax+0]
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db 0xc4, 0xe2, 0x7b, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADD tmm0, [rax+rax+0]
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db 0xc4, 0xe2, 0x7a, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILESTORED tmm0, [rax+rax+0]
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db 0xc4, 0xe2, 0x78, 0x49, 0xC0 ; TILERELEASE
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db 0xc4, 0xe2, 0x7b, 0x49, 0xC0 ; TILEZERO tmm0
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db 0xc4, 0xe2, 0x7b, 0x49, 0xf8 ; TILEZERO tmm7
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db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x78, 0x6C, 0xF4 ; TCMMRLFP16PS tmm6, tmm4, tmm0
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db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm
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db 0xc4, 0xe2, 0x78, 0x48, 0xcf ; TTMMULTF32PS tmm1, tmm7, tmm0
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db 0xc4, 0xe2, 0x79, 0x48, 0xcf ; TMMULTF32PS tmm1, tmm7, tmm0
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db 0xc4, 0xe2, 0x79, 0x4a, 0x04, 0x11 ; TILELOADDRST1 tmm0, [rcx+rdx]
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db 0xc4, 0xe2, 0x7b, 0x4a, 0x04, 0x11 ; TILELOADDRS tmm0, [rcx+rdx]
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db 0xc4, 0xe2, 0x7a, 0x5f, 0xcd ; TTRANSPOSED tmm1, tmm5
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db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x79, 0x6b, 0xcd ; TCONJTFP16 tmm1, tmm5
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db 0xc4, 0xe2, 0x7a, 0x6b, 0xcd ; TTCMMRLFP16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x7b, 0x6b, 0xcd ; TTCMMIMFP16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x7a, 0x6c, 0xcd ; TTDPBF16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x7b, 0x6c, 0xcd ; TTDPFP16PS tmm1, tmm5, tmm0
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db 0xc4, 0xe2, 0x78, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ0 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe2, 0x79, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ1 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe2, 0x78, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ0T1 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe2, 0x79, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ1T1 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe5, 0x78, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ0RS tmm0+1, [rcx+rdx]
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db 0xc4, 0xe5, 0x79, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ1RS tmm0+1, [rcx+rdx]
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db 0xc4, 0xe5, 0x78, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ0RST1 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe5, 0x79, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ1RST1 tmm0+1, [rcx+rdx]
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db 0xc4, 0xe5, 0x78, 0xfd, 0xcd ; TDPBF8PS tmm1, tmm5, tmm0
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db 0xc4, 0xe5, 0x79, 0xfd, 0xcd ; TDPHF8PS tmm1, tmm5, tmm0
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db 0xc4, 0xe5, 0x7a, 0xfd, 0xcd ; TDPHBF8PS tmm1, tmm5, tmm0
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db 0xc4, 0xe5, 0x7b, 0xfd, 0xcd ; TDPBHF8PS tmm1, tmm5, tmm0
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