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bddisasm/bddisasm_test/x86/avx512/avx512fma_64.asm
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 12:22:59 +03:00

93 lines
3.9 KiB
NASM

bits 64
vpmadd52huq xmm2, xmm7, xmm0
vpmadd52huq xmm2, xmm7, [rbx]
vpmadd52huq xmm2, xmm7, [rbx]{1to2}
vpmadd52huq xmm2, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{k5}, xmm7, xmm0
vpmadd52huq xmm2{k5}, xmm7, [rbx]
vpmadd52huq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{k5}{z}, xmm7, xmm0
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmadd52huq ymm16, ymm13, ymm15
vpmadd52huq ymm16, ymm13, [rbx]
vpmadd52huq ymm16, ymm13, [rbx]{1to4}
vpmadd52huq ymm16, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{k5}, ymm13, ymm15
vpmadd52huq ymm16{k5}, ymm13, [rbx]
vpmadd52huq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{k5}{z}, ymm13, ymm15
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmadd52huq zmm24, zmm24, zmm31
vpmadd52huq zmm24, zmm24, [rbx]
vpmadd52huq zmm24, zmm24, [rbx]{1to8}
vpmadd52huq zmm24, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{k5}, zmm24, zmm31
vpmadd52huq zmm24{k5}, zmm24, [rbx]
vpmadd52huq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{k5}{z}, zmm24, zmm31
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmadd52luq xmm2, xmm7, xmm0
vpmadd52luq xmm2, xmm7, [rbx]
vpmadd52luq xmm2, xmm7, [rbx]{1to2}
vpmadd52luq xmm2, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{k5}, xmm7, xmm0
vpmadd52luq xmm2{k5}, xmm7, [rbx]
vpmadd52luq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{k5}{z}, xmm7, xmm0
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmadd52luq ymm16, ymm13, ymm15
vpmadd52luq ymm16, ymm13, [rbx]
vpmadd52luq ymm16, ymm13, [rbx]{1to4}
vpmadd52luq ymm16, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{k5}, ymm13, ymm15
vpmadd52luq ymm16{k5}, ymm13, [rbx]
vpmadd52luq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{k5}{z}, ymm13, ymm15
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmadd52luq zmm24, zmm24, zmm31
vpmadd52luq zmm24, zmm24, [rbx]
vpmadd52luq zmm24, zmm24, [rbx]{1to8}
vpmadd52luq zmm24, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{k5}, zmm24, zmm31
vpmadd52luq zmm24{k5}, zmm24, [rbx]
vpmadd52luq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{k5}{z}, zmm24, zmm31
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]