1
0
mirror of https://github.com/bitdefender/bddisasm.git synced 2024-11-28 02:18:10 +00:00
bddisasm/bddisasm_test/x86/avx/avxifma_64.asm
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 12:22:59 +03:00

11 lines
725 B
NASM

bits 64
db 0xc4, 0xa2, 0xc1, 0xb4, 0xc0 ; VPMADD52LUQ xmm0, xmm7, xmm0
db 0xc4, 0xa2, 0xc1, 0xb4, 0x00 ; VPMADD52LUQ xmm0, xmm7, xmmword ptr [rax]
db 0xc4, 0xa2, 0xc5, 0xb4, 0xc0 ; VPMADD52LUQ ymm0, ymm7, ymm0
db 0xc4, 0xa2, 0xc5, 0xb4, 0x00 ; VPMADD52LUQ ymm0, ymm7, ymmword ptr [rax]
db 0xc4, 0xa2, 0xc1, 0xb5, 0xc0 ; VPMADD52HUQ xmm0, xmm7, xmm0
db 0xc4, 0xa2, 0xc1, 0xb5, 0x00 ; VPMADD52HUQ xmm0, xmm7, xmmword ptr [rax]
db 0xc4, 0xa2, 0xc5, 0xb5, 0xc0 ; VPMADD52HUQ ymm0, ymm7, ymm0
db 0xc4, 0xa2, 0xc5, 0xb5, 0x00 ; VPMADD52HUQ ymm0, ymm7, ymmword ptr [rax]