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114206 lines
4.1 MiB
114206 lines
4.1 MiB
/*
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* Copyright (c) 2024 Bitdefender
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* SPDX-License-Identifier: Apache-2.0
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*/
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//
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// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
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//
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#ifndef BDX86_INSTRUCTIONS_H
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#define BDX86_INSTRUCTIONS_H
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const ND_IDBE gInstructions[4075] =
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{
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// Pos:0 Instruction:"AAA" Encoding:"0x37"/""
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{
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.Instruction = ND_INS_AAA,
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.Category = ND_CAT_DECIMAL,
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.IsaSet = ND_SET_I86,
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.Mnemonic = 0,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(0, 3),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0|NDR_RFLAG_AF,
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.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
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.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.Attributes = ND_FLAG_I64,
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.CpuidFlag = 0,
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.Operands =
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{
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OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I"
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{
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.Instruction = ND_INS_AAD,
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.Category = ND_CAT_DECIMAL,
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.IsaSet = ND_SET_I86,
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.Mnemonic = 1,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(1, 3),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
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.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
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.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
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.Attributes = ND_FLAG_I64,
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.CpuidFlag = 0,
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.Operands =
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{
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
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},
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},
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// Pos:2 Instruction:"AADD My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFC /r:mem"/"MR"
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{
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.Instruction = ND_INS_AADD,
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.Category = ND_CAT_RAOINT,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 2,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_RAOINT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR"
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{
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.Instruction = ND_INS_AADD,
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.Category = ND_CAT_RAOINT,
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.IsaSet = ND_SET_RAOINT,
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.Mnemonic = 2,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_ANY,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
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.CpuidFlag = ND_CFF_RAOINT,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:4 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I"
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{
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.Instruction = ND_INS_AAM,
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.Category = ND_CAT_DECIMAL,
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.IsaSet = ND_SET_I86,
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.Mnemonic = 3,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(1, 3),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
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.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
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.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
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.Attributes = ND_FLAG_I64,
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.CpuidFlag = 0,
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.Operands =
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{
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
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},
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},
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// Pos:5 Instruction:"AAND My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFC /r:mem"/"MR"
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{
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.Instruction = ND_INS_AAND,
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.Category = ND_CAT_RAOINT,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 4,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_RAOINT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:6 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR"
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{
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.Instruction = ND_INS_AAND,
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.Category = ND_CAT_RAOINT,
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.IsaSet = ND_SET_RAOINT,
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.Mnemonic = 4,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_ANY,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
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.CpuidFlag = ND_CFF_RAOINT,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:7 Instruction:"AAS" Encoding:"0x3F"/""
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{
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.Instruction = ND_INS_AAS,
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.Category = ND_CAT_DECIMAL,
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.IsaSet = ND_SET_I86,
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.Mnemonic = 5,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(0, 3),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0|NDR_RFLAG_AF,
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.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
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.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.Attributes = ND_FLAG_I64,
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.CpuidFlag = 0,
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.Operands =
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{
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OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:8 Instruction:"ADC Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x10 /r"/"MR"
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{
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.Instruction = ND_INS_ADC,
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.Category = ND_CAT_ARITH,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 6,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 1),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_INT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0|NDR_RFLAG_CF,
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.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:9 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x11 /r"/"MR"
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{
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.Instruction = ND_INS_ADC,
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.Category = ND_CAT_ARITH,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 6,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 1),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_INT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0|NDR_RFLAG_CF,
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.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:10 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x11 /r"/"MR"
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{
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.Instruction = ND_INS_ADC,
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.Category = ND_CAT_ARITH,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 6,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 1),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_INT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0|NDR_RFLAG_CF,
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.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:11 Instruction:"ADC Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x12 /r"/"RM"
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{
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.Instruction = ND_INS_ADC,
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.Category = ND_CAT_ARITH,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 6,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 1),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_INT,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_LEGACY,
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.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:12 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x13 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:13 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x13 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:14 Instruction:"ADC Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:15 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /2 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:16 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /2 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:17 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:18 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:19 Instruction:"ADC Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x10 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:20 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x11 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:21 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x11 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:22 Instruction:"ADC Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x12 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:23 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x13 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:24 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x13 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:25 Instruction:"ADC Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:26 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /2 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:27 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /2 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:28 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:29 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:30 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:31 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:32 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:33 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:34 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:35 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:36 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:37 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:38 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:39 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 6,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:40 Instruction:"ADCX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x66 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADCX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 7,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:41 Instruction:"ADCX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x66 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADCX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 7,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:42 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADCX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_ADX,
|
|
.Mnemonic = 7,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_ADX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:43 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x00 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:44 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x01 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:45 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x01 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:46 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x02 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:47 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:48 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:49 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:50 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:51 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:52 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:53 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:54 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x00 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:55 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x01 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:56 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x01 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:57 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x02 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:58 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:59 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:60 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:61 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:62 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:63 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:64 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:65 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x00 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:66 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x01 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:67 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x01 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:68 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x02 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:69 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x03 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:70 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x03 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:71 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:72 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /0 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:73 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /0 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:74 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:75 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:76 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x00 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:77 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x01 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:78 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x01 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:79 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x02 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:80 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x03 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:81 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x03 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:82 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:83 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /0 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:84 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /0 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:85 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:86 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:87 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:88 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:89 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:90 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:91 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:92 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:93 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:94 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:95 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:96 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ADD,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 8,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:97 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 9,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:98 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 10,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:99 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 11,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:100 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 12,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:101 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDSUBPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 13,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:102 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADDSUBPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 14,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:103 Instruction:"ADOX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0x66 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADOX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 15,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:104 Instruction:"ADOX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:2 0x66 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_ADOX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 15,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:105 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ADOX,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_ADX,
|
|
.Mnemonic = 15,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_ADX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:106 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDEC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 16,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:107 Instruction:"AESDEC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDEC128KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 17,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:108 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDEC128KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 17,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:109 Instruction:"AESDEC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDEC256KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 18,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:110 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDEC256KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 18,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:111 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESDECLAST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 19,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:112 Instruction:"AESDECWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESDECWIDE128KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 20,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:113 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESDECWIDE128KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 20,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:114 Instruction:"AESDECWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESDECWIDE256KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 21,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:115 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESDECWIDE256KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 21,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:116 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 22,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:117 Instruction:"AESENC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENC128KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 23,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:118 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENC128KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 23,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:119 Instruction:"AESENC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENC256KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 24,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:120 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENC256KL,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 24,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:121 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESENCLAST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 25,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:122 Instruction:"AESENCWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESENCWIDE128KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 26,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:123 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESENCWIDE128KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 26,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:124 Instruction:"AESENCWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESENCWIDE256KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 27,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:125 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_AESENCWIDE256KL,
|
|
.Category = ND_CAT_WIDE_KL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 27,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:126 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AESIMC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 28,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:127 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_AESKEYGENASSIST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 29,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:128 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:129 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:130 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:131 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:132 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:133 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:134 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:135 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:136 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:137 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:138 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:139 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:140 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:141 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:142 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:143 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:144 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:145 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:146 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:147 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:148 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:149 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:150 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:151 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:152 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:153 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:154 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:155 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:156 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:157 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:158 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:159 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:160 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:161 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:162 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:163 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:164 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:165 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:166 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:167 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:168 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:169 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:170 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:171 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:172 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:173 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:174 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:175 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:176 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:177 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:178 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:179 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:180 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:181 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_AND,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 30,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:182 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_ANDN,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 31,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:183 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_ANDN,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 31,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:184 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_ANDN,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 31,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:185 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ANDNPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 32,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:186 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ANDNPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 33,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:187 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ANDPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 34,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:188 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ANDPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 35,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:189 Instruction:"AOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AOR,
|
|
.Category = ND_CAT_RAOINT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 36,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_RAOINT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:190 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AOR,
|
|
.Category = ND_CAT_RAOINT,
|
|
.IsaSet = ND_SET_RAOINT,
|
|
.Mnemonic = 36,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RAOINT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:191 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_ARPL,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 37,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:192 Instruction:"AXOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AXOR,
|
|
.Category = ND_CAT_RAOINT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 38,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_RAOINT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:193 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_AXOR,
|
|
.Category = ND_CAT_RAOINT,
|
|
.IsaSet = ND_SET_RAOINT,
|
|
.Mnemonic = 38,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RAOINT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:194 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BEXTR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 39,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:195 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BEXTR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 39,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:196 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BEXTR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 39,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:197 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_BEXTR,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 39,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:198 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLCFILL,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 40,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:199 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLCI,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 41,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:200 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLCIC,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 42,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:201 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLCMSK,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 43,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:202 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLCS,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 44,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:203 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_BLENDPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 45,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:204 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_BLENDPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 46,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:205 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BLENDVPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 47,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:206 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BLENDVPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 48,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:207 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSFILL,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 49,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:208 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSI,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 50,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:209 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSI,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 50,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:210 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSI,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 50,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:211 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSIC,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 51,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:212 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSMSK,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 52,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:213 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSMSK,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 52,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:214 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSMSK,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 52,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:215 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 53,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:216 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 53,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:217 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_BLSR,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 53,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:218 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDCL,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 54,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:219 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDCN,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 55,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:220 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDCU,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 56,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:221 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx NP 0x0F 0x1A /r:mem mib"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDLDX,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 57,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:222 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDMK,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 58,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:223 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BNDMOV,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 59,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:224 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BNDMOV,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 59,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:225 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx NP 0x0F 0x1B /r:mem mib"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BNDSTX,
|
|
.Category = ND_CAT_MPX,
|
|
.IsaSet = ND_SET_MPX,
|
|
.Mnemonic = 60,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB,
|
|
.CpuidFlag = ND_CFF_MPX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:226 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BOUND,
|
|
.Category = ND_CAT_INTERRUPT,
|
|
.IsaSet = ND_SET_I186,
|
|
.Mnemonic = 61,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_a, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:227 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BSF,
|
|
.Category = ND_CAT_I386,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 62,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:228 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_BSR,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 63,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:229 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:230 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:231 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:232 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:233 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:234 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:235 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:236 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O"
|
|
{
|
|
.Instruction = ND_INS_BSWAP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 64,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:237 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BT,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 65,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:238 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_BT,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 65,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:239 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_BTC,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 66,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:240 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BTC,
|
|
.Category = ND_CAT_I386,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 66,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:241 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BTR,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 67,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:242 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_BTR,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 67,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:243 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR"
|
|
{
|
|
.Instruction = ND_INS_BTS,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 68,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:244 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_BTS,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 68,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:245 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF5 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BZHI,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 69,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:246 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF5 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BZHI,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 69,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:247 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_BZHI,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 69,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:248 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_CALLNR,
|
|
.Category = ND_CAT_CALL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 70,
|
|
.ValidPrefixes = ND_PREF_BND,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:249 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_CALLNI,
|
|
.Category = ND_CAT_CALL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 70,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_DNT,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:250 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D"
|
|
{
|
|
.Instruction = ND_INS_CALLFD,
|
|
.Category = ND_CAT_CALL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 71,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:251 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CALLFI,
|
|
.Category = ND_CAT_CALL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 71,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_CETT|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:252 Instruction:"CBW" Encoding:"ds16 0x98"/""
|
|
{
|
|
.Instruction = ND_INS_CBW,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 72,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:253 Instruction:"CCMPBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:254 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:255 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:256 Instruction:"CCMPBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:257 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:258 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:259 Instruction:"CCMPBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:260 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:261 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:262 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:263 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 73,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:264 Instruction:"CCMPC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:265 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:266 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:267 Instruction:"CCMPC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:268 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:269 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:270 Instruction:"CCMPC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:271 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:272 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:273 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:274 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 74,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:275 Instruction:"CCMPF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:276 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:277 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:278 Instruction:"CCMPF Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:279 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:280 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:281 Instruction:"CCMPF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:282 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:283 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:284 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:285 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 75,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:286 Instruction:"CCMPL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:287 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:288 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:289 Instruction:"CCMPL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:290 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:291 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:292 Instruction:"CCMPL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:293 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:294 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:295 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:296 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 76,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:297 Instruction:"CCMPLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:298 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:299 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:300 Instruction:"CCMPLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:301 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:302 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:303 Instruction:"CCMPLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:304 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:305 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:306 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:307 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 77,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:308 Instruction:"CCMPNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:309 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:310 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:311 Instruction:"CCMPNBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:312 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:313 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:314 Instruction:"CCMPNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:315 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:316 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:317 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:318 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 78,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:319 Instruction:"CCMPNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:320 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:321 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:322 Instruction:"CCMPNC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:323 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:324 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:325 Instruction:"CCMPNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:326 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:327 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:328 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:329 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 79,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:330 Instruction:"CCMPNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:331 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:332 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:333 Instruction:"CCMPNL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:334 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:335 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:336 Instruction:"CCMPNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:337 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:338 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:339 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:340 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 80,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:341 Instruction:"CCMPNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:342 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:343 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:344 Instruction:"CCMPNLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:345 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:346 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:347 Instruction:"CCMPNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:348 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:349 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:350 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:351 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 81,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:352 Instruction:"CCMPNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:353 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:354 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:355 Instruction:"CCMPNO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:356 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:357 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:358 Instruction:"CCMPNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:359 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:360 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:361 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:362 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 82,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:363 Instruction:"CCMPNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:364 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:365 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:366 Instruction:"CCMPNS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:367 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:368 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:369 Instruction:"CCMPNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:370 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:371 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:372 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:373 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 83,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:374 Instruction:"CCMPNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:375 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:376 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:377 Instruction:"CCMPNZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:378 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:379 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:380 Instruction:"CCMPNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:381 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:382 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:383 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:384 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 84,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:385 Instruction:"CCMPO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:386 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:387 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:388 Instruction:"CCMPO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:389 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:390 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:391 Instruction:"CCMPO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:392 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:393 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:394 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:395 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 85,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:396 Instruction:"CCMPS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:397 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:398 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:399 Instruction:"CCMPS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:400 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:401 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:402 Instruction:"CCMPS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:403 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:404 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:405 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:406 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 86,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:407 Instruction:"CCMPT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:408 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:409 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:410 Instruction:"CCMPT Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:411 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:412 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:413 Instruction:"CCMPT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:414 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:415 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:416 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:417 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 87,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:418 Instruction:"CCMPZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:419 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:420 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:421 Instruction:"CCMPZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:422 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:423 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:424 Instruction:"CCMPZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:425 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:426 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:427 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:428 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CCMP,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 88,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:429 Instruction:"CDQ" Encoding:"ds32 0x99"/""
|
|
{
|
|
.Instruction = ND_INS_CDQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 89,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:430 Instruction:"CDQE" Encoding:"ds64 0x98"/""
|
|
{
|
|
.Instruction = ND_INS_CDQE,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 90,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:431 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:432 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:433 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:434 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:435 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:436 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:437 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:438 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 91,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:439 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:440 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:441 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:442 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:443 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:444 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:445 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:446 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 92,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:447 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:448 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:449 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:450 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:451 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:452 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:453 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:454 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 93,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:455 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:456 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:457 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:458 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:459 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:460 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:461 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:462 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 94,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:463 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:464 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:465 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:466 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:467 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:468 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:469 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:470 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 95,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:471 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:472 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:473 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:474 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:475 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:476 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:477 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:478 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 96,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:479 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:480 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:481 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:482 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:483 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:484 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:485 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:486 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 97,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:487 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:488 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:489 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:490 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:491 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:492 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:493 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:494 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 98,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:495 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:496 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:497 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:498 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:499 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:500 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:501 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:502 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 99,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:503 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:504 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:505 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:506 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:507 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:508 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:509 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:510 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:511 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:512 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:513 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:514 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:515 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:516 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:517 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:518 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:519 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:520 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:521 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:522 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:523 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:524 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:525 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:526 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:527 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:528 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:529 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:530 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:531 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:532 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:533 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:534 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:535 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:536 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:537 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:538 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:539 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:540 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:541 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:542 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:543 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:544 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:545 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:546 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:547 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:548 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:549 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:550 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:551 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:552 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:553 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:554 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:555 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:556 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:557 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:558 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CFCMOV,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CFCMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:559 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/""
|
|
{
|
|
.Instruction = ND_INS_CLAC,
|
|
.Category = ND_CAT_SMAP,
|
|
.IsaSet = ND_SET_SMAP,
|
|
.Mnemonic = 107,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_AC,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SMAP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:560 Instruction:"CLC" Encoding:"0xF8"/""
|
|
{
|
|
.Instruction = ND_INS_CLC,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 108,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:561 Instruction:"CLD" Encoding:"0xFC"/""
|
|
{
|
|
.Instruction = ND_INS_CLD,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 109,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_DF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:562 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLDEMOTE,
|
|
.Category = ND_CAT_CLDEMOTE,
|
|
.IsaSet = ND_SET_CLDEMOTE,
|
|
.Mnemonic = 110,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CLDEMOTE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:563 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLEVICT0,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 111,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:564 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLEVICT1,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 112,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:565 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLFLUSH,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_CLFSH,
|
|
.Mnemonic = 113,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CLFSH,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:566 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLFLUSHOPT,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_CLFSHOPT,
|
|
.Mnemonic = 114,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CLFSHOPT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:567 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
|
|
{
|
|
.Instruction = ND_INS_CLGI,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 115,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:568 Instruction:"CLI" Encoding:"0xFA"/""
|
|
{
|
|
.Instruction = ND_INS_CLI,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 116,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_IF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:569 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLRSSBSY,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 117,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:570 Instruction:"CLTS" Encoding:"0x0F 0x06"/""
|
|
{
|
|
.Instruction = ND_INS_CLTS,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 118,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:571 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/""
|
|
{
|
|
.Instruction = ND_INS_CLUI,
|
|
.Category = ND_CAT_UINTR,
|
|
.IsaSet = ND_SET_UINTR,
|
|
.Mnemonic = 119,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_UINTR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:572 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CLWB,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_CLWB,
|
|
.Mnemonic = 120,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CLWB,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:573 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
|
|
{
|
|
.Instruction = ND_INS_CLZERO,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_CLZERO,
|
|
.Mnemonic = 121,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:574 Instruction:"CMC" Encoding:"0xF5"/""
|
|
{
|
|
.Instruction = ND_INS_CMC,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 122,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:575 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 123,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:576 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 123,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:577 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 123,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:578 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 124,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:579 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 124,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:580 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 124,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:581 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 125,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:582 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 125,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:583 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 125,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:584 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 126,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:585 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 126,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:586 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 126,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:587 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 127,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:588 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 127,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:589 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 127,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:590 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 128,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:591 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 128,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:592 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 128,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:593 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 129,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:594 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 129,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:595 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 129,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:596 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 130,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:597 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 130,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:598 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 130,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:599 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 131,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:600 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 131,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:601 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 131,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:602 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 132,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:603 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 132,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:604 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 132,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:605 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 133,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:606 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 133,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:607 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 133,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:608 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 134,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:609 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 134,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:610 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 134,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:611 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 135,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:612 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 135,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:613 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 135,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:614 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 136,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:615 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 136,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:616 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 136,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:617 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 137,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:618 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 137,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:619 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 137,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:620 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 138,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:621 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 138,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:622 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMOVcc,
|
|
.Category = ND_CAT_CMOV,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 138,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMOV,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:623 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:624 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:625 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:626 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:627 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:628 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:629 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:630 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:631 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:632 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_CMP,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:633 Instruction:"CMPBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE6 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPBEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 140,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:634 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPBEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 140,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:635 Instruction:"CMPCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE2 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPCXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 141,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:636 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPCXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 141,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:637 Instruction:"CMPLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEE /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPLEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 142,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:638 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPLEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 142,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:639 Instruction:"CMPLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEC /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPLXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 143,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:640 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPLXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 143,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:641 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE7 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNBEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 144,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:642 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNBEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 144,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:643 Instruction:"CMPNCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE3 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNCXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 145,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:644 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNCXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 145,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:645 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEF /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNLEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 146,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:646 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNLEXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 146,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:647 Instruction:"CMPNLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xED /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNLXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 147,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:648 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNLXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 147,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:649 Instruction:"CMPNOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE1 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNOXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 148,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:650 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNOXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 148,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:651 Instruction:"CMPNPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEB /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNPXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 149,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:652 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNPXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 149,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:653 Instruction:"CMPNSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE9 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNSXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 150,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:654 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNSXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 150,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:655 Instruction:"CMPNZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE5 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNZXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 151,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:656 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPNZXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 151,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:657 Instruction:"CMPOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE0 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPOXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 152,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:658 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPOXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 152,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:659 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_CMPPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 153,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:660 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_CMPPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 154,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:661 Instruction:"CMPPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEA /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPPXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 155,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:662 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPPXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 155,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:663 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 156,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:664 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 156,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:665 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 157,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:666 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 157,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:667 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_CMPSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 157,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:668 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 158,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:669 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 158,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:670 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_CMPSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 159,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:671 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 160,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:672 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/""
|
|
{
|
|
.Instruction = ND_INS_CMPS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 160,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:673 Instruction:"CMPSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE8 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPSXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 161,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:674 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPSXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 161,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:675 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CMPXCHG,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 162,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:676 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_CMPXCHG,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 162,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:677 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CMPXCHG16B,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_CMPXCHG16B,
|
|
.Mnemonic = 163,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CX8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:678 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_CMPXCHG8B,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_PENTIUMREAL,
|
|
.Mnemonic = 164,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CX8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:679 Instruction:"CMPZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE4 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPZXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 165,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:680 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CMPZXADD,
|
|
.Category = ND_CAT_CMPCCXADD,
|
|
.IsaSet = ND_SET_CMPCCXADD,
|
|
.Mnemonic = 165,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_14,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CMPCCXADD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:681 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_COMISD,
|
|
.Category = ND_CAT_SSE2,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 166,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:682 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_COMISS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 167,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:683 Instruction:"CPUID" Encoding:"0x0F 0xA2"/""
|
|
{
|
|
.Instruction = ND_INS_CPUID,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 168,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:684 Instruction:"CQO" Encoding:"ds64 0x99"/""
|
|
{
|
|
.Instruction = ND_INS_CQO,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 169,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:685 Instruction:"CRC32 Gy,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CRC32,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:686 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CRC32,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:687 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CRC32,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:688 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CRC32,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:689 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CRC32,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:690 Instruction:"CTESTBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:691 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:692 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:693 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:694 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:695 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:696 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:697 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:698 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:699 Instruction:"CTESTC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:700 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:701 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:702 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:703 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:704 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:705 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:706 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:707 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:708 Instruction:"CTESTF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:709 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:710 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:711 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:712 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:713 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:714 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:715 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:716 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:717 Instruction:"CTESTL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:718 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:719 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:720 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:721 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:722 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:723 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:724 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:725 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:726 Instruction:"CTESTLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:727 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:728 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:729 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:730 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:731 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:732 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:733 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:734 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:735 Instruction:"CTESTNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:736 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:737 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:738 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:739 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:740 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:741 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:742 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:743 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:744 Instruction:"CTESTNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:745 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:746 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:747 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:748 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:749 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:750 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:751 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:752 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:753 Instruction:"CTESTNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:754 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:755 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:756 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:757 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:758 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:759 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:760 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:761 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 178,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:762 Instruction:"CTESTNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:763 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:764 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:765 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:766 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:767 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:768 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:769 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:770 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 179,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:771 Instruction:"CTESTNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:772 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:773 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:774 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:775 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:776 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:777 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:778 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:779 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 180,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:780 Instruction:"CTESTNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:781 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:782 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:783 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:784 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:785 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:786 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:787 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:788 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 181,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:789 Instruction:"CTESTNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:790 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:791 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:792 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:793 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:794 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:795 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:796 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:797 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 182,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:798 Instruction:"CTESTO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:799 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:800 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:801 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:802 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:803 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:804 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:805 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:806 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 183,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:807 Instruction:"CTESTS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:808 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:809 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:810 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:811 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:812 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:813 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:814 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:815 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 184,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:816 Instruction:"CTESTT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:817 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:818 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:819 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:820 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:821 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:822 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:823 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:824 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 185,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:825 Instruction:"CTESTZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:826 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:827 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r"/"MRV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:828 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:829 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:830 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:831 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:832 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:833 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz"/"MIV"
|
|
{
|
|
.Instruction = ND_INS_CTEST,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_CCMP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_COND,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:834 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTDQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 187,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:835 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTDQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 188,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:836 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 189,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:837 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPD2PI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 190,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:838 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPD2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 191,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:839 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPI2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 192,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:840 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPI2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 193,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:841 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 194,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:842 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPS2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 195,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:843 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTPS2PI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 196,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:844 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 197,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:845 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSD2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 198,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:846 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 199,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:847 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSI2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 200,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:848 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSS2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 201,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:849 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 202,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:850 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 203,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:851 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTPD2PI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 204,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:852 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 205,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:853 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTPS2PI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 206,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:854 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 207,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:855 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_CVTTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 208,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:856 Instruction:"CWD" Encoding:"ds16 0x99"/""
|
|
{
|
|
.Instruction = ND_INS_CWD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 209,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:857 Instruction:"CWDE" Encoding:"ds32 0x98"/""
|
|
{
|
|
.Instruction = ND_INS_CWDE,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 210,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:858 Instruction:"DAA" Encoding:"0x27"/""
|
|
{
|
|
.Instruction = ND_INS_DAA,
|
|
.Category = ND_CAT_DECIMAL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 211,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:859 Instruction:"DAS" Encoding:"0x2F"/""
|
|
{
|
|
.Instruction = ND_INS_DAS,
|
|
.Category = ND_CAT_DECIMAL,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 212,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:860 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:861 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:862 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:863 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:864 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:865 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:866 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:867 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:868 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:869 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:870 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:871 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1"/"VM"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:872 Instruction:"DEC Zv" Encoding:"0x48"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:873 Instruction:"DEC Zv" Encoding:"0x49"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:874 Instruction:"DEC Zv" Encoding:"0x4A"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:875 Instruction:"DEC Zv" Encoding:"0x4B"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:876 Instruction:"DEC Zv" Encoding:"0x4C"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:877 Instruction:"DEC Zv" Encoding:"0x4D"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:878 Instruction:"DEC Zv" Encoding:"0x4E"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:879 Instruction:"DEC Zv" Encoding:"0x4F"/"O"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:880 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:881 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M"
|
|
{
|
|
.Instruction = ND_INS_DEC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 213,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:882 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_DELAY,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 214,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:883 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:884 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:885 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:886 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:887 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:888 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:889 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:890 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_DIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:891 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_DIVPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 216,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:892 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_DIVPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 217,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:893 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_DIVSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 218,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:894 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_DIVSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 219,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:895 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_DPPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 220,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:896 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_DPPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 221,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:897 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/""
|
|
{
|
|
.Instruction = ND_INS_EMMS,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 222,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:898 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/""
|
|
{
|
|
.Instruction = ND_INS_ENCLS,
|
|
.Category = ND_CAT_SGX,
|
|
.IsaSet = ND_SET_SGX,
|
|
.Mnemonic = 223,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SGX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:899 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/""
|
|
{
|
|
.Instruction = ND_INS_ENCLU,
|
|
.Category = ND_CAT_SGX,
|
|
.IsaSet = ND_SET_SGX,
|
|
.Mnemonic = 224,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SGX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:900 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/""
|
|
{
|
|
.Instruction = ND_INS_ENCLV,
|
|
.Category = ND_CAT_SGX,
|
|
.IsaSet = ND_SET_SGX,
|
|
.Mnemonic = 225,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SGX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:901 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ENCODEKEY128,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
|
|
OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:902 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ENCODEKEY128,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
|
|
OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:903 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ENCODEKEY256,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 227,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KEYLOCKER,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2),
|
|
OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:904 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ENCODEKEY256,
|
|
.Category = ND_CAT_AESKL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 227,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2),
|
|
OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:905 Instruction:"ENDBR32" Encoding:"cet repz 0x0F 0x1E /0xFB"/""
|
|
{
|
|
.Instruction = ND_INS_ENDBR,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_IBT,
|
|
.Mnemonic = 228,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_IBT,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:906 Instruction:"ENDBR64" Encoding:"cet repz 0x0F 0x1E /0xFA"/""
|
|
{
|
|
.Instruction = ND_INS_ENDBR,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_IBT,
|
|
.Mnemonic = 229,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_IBT,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:907 Instruction:"ENQCMD rM?,Moq" Encoding:"evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_ENQCMD,
|
|
.Category = ND_CAT_ENQCMD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 230,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_ENQCMD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:908 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_ENQCMD,
|
|
.Category = ND_CAT_ENQCMD,
|
|
.IsaSet = ND_SET_ENQCMD,
|
|
.Mnemonic = 230,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_ENQCMD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:909 Instruction:"ENQCMDS rM?,Moq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_ENQCMDS,
|
|
.Category = ND_CAT_ENQCMD,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 231,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_ENQCMD,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:910 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_ENQCMDS,
|
|
.Category = ND_CAT_ENQCMD,
|
|
.IsaSet = ND_SET_ENQCMD,
|
|
.Mnemonic = 231,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_ENQCMD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:911 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II"
|
|
{
|
|
.Instruction = ND_INS_ENTER,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_I186,
|
|
.Mnemonic = 232,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:912 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/""
|
|
{
|
|
.Instruction = ND_INS_ERETS,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_FRED,
|
|
.Mnemonic = 233,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_FRED,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:913 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/""
|
|
{
|
|
.Instruction = ND_INS_ERETU,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_FRED,
|
|
.Mnemonic = 234,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 9),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_FRED,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:914 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_EXTRACTPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 235,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:915 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 ib ib"/"MII"
|
|
{
|
|
.Instruction = ND_INS_EXTRQ,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 236,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:916 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_EXTRQ,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 236,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:917 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
|
|
{
|
|
.Instruction = ND_INS_F2XM1,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 237,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:918 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
|
|
{
|
|
.Instruction = ND_INS_FABS,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 238,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:919 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 239,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:920 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 239,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:921 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 239,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:922 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 239,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:923 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FADDP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 240,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:924 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FBLD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 241,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:925 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FBSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 242,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:926 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
|
|
{
|
|
.Instruction = ND_INS_FCHS,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 243,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:927 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 244,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:928 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVBE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 245,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:929 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 246,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:930 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVNB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 247,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:931 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVNBE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 248,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:932 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVNE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 249,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:933 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVNU,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 250,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:934 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCMOVU,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 251,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:935 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:936 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:937 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:938 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:939 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMI,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 253,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:940 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMIP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:941 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:942 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:943 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:944 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:945 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:946 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
|
|
{
|
|
.Instruction = ND_INS_FCOMPP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 256,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:947 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
|
|
{
|
|
.Instruction = ND_INS_FCOS,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 257,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xeb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:948 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
|
|
{
|
|
.Instruction = ND_INS_FDECSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 258,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:949 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:950 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:951 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:952 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:953 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 260,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:954 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:955 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:956 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:957 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:958 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FDIVRP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 262,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:959 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
|
|
{
|
|
.Instruction = ND_INS_FEMMS,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 263,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:960 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FFREE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 264,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:961 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FFREEP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 265,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:962 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 266,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:963 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIADD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 266,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:964 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FICOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:965 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FICOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:966 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FICOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:967 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FICOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:968 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 269,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:969 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIDIV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 269,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:970 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 270,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:971 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIDIVR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 270,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:972 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FILD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 271,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:973 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FILD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 271,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:974 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FILD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 271,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:975 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 272,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:976 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 272,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:977 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
|
|
{
|
|
.Instruction = ND_INS_FINCSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 273,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:978 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 274,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:979 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FIST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 274,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:980 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:981 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:982 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:983 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:984 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:985 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISTTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:986 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:987 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:988 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 278,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:989 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FISUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 278,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:990 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:991 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:992 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:993 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLD,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:994 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
|
|
{
|
|
.Instruction = ND_INS_FLD1,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:995 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLDCW,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 281,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:996 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FLDENV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 282,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:997 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
|
|
{
|
|
.Instruction = ND_INS_FLDL2E,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 283,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:998 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
|
|
{
|
|
.Instruction = ND_INS_FLDL2T,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 284,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:999 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
|
|
{
|
|
.Instruction = ND_INS_FLDLG2,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 285,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1000 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
|
|
{
|
|
.Instruction = ND_INS_FLDLN2,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 286,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1001 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
|
|
{
|
|
.Instruction = ND_INS_FLDPI,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 287,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1002 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
|
|
{
|
|
.Instruction = ND_INS_FLDZ,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 288,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1003 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 289,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1004 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 289,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1005 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 289,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1006 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FMUL,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 289,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1007 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FMULP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 290,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1008 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
|
|
{
|
|
.Instruction = ND_INS_FNCLEX,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 291,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1009 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
|
|
{
|
|
.Instruction = ND_INS_FNDISI,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 292,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1010 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
|
|
{
|
|
.Instruction = ND_INS_FNINIT,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 293,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0x00,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1011 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
|
|
{
|
|
.Instruction = ND_INS_FNOP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 294,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1012 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
|
|
{
|
|
.Instruction = ND_INS_FNOP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 294,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1013 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
|
|
{
|
|
.Instruction = ND_INS_FNOP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 294,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1014 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FNSAVE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 295,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0x00,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1015 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FNSTCW,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 296,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1016 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FNSTENV,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 297,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1017 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FNSTSW,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 298,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1018 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
|
|
{
|
|
.Instruction = ND_INS_FNSTSW,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 298,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1019 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
|
|
{
|
|
.Instruction = ND_INS_FPATAN,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 299,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1020 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
|
|
{
|
|
.Instruction = ND_INS_FPREM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 300,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1021 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
|
|
{
|
|
.Instruction = ND_INS_FPREM1,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 301,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1022 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
|
|
{
|
|
.Instruction = ND_INS_FPTAN,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 302,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xeb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1023 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
|
|
{
|
|
.Instruction = ND_INS_FRINEAR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 303,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1024 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
|
|
{
|
|
.Instruction = ND_INS_FRNDINT,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 304,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1025 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FRSTOR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 305,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1026 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
|
|
{
|
|
.Instruction = ND_INS_FSCALE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 306,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1027 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
|
|
{
|
|
.Instruction = ND_INS_FSIN,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 307,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xeb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1028 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
|
|
{
|
|
.Instruction = ND_INS_FSINCOS,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 308,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xeb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1029 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
|
|
{
|
|
.Instruction = ND_INS_FSQRT,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 309,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1030 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 310,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1031 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 310,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1032 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 310,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1033 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
|
|
{
|
|
.Instruction = ND_INS_FSTDW,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 311,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1034 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1035 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1036 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1037 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1038 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1039 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1040 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSTPNCE,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 313,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1041 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
|
|
{
|
|
.Instruction = ND_INS_FSTSG,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 314,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1042 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1043 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1044 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1045 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUB,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1046 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 316,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1047 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1048 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1049 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1050 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBR,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1051 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FSUBRP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 318,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1052 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
|
|
{
|
|
.Instruction = ND_INS_FTST,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 319,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1053 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FUCOM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 320,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1054 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FUCOMI,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 321,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1055 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FUCOMIP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 322,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xa2,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1056 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FUCOMP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 323,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1057 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
|
|
{
|
|
.Instruction = ND_INS_FUCOMPP,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 324,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1058 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
|
|
{
|
|
.Instruction = ND_INS_FXAM,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 325,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xaa,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1059 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXCH,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 326,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1060 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXCH,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 326,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1061 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXCH,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 326,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xf3,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1062 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXRSTOR,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_FXSAVE,
|
|
.Mnemonic = 327,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_FXSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1063 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXRSTOR64,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_FXSAVE,
|
|
.Mnemonic = 328,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_FXSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1064 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXSAVE,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_FXSAVE,
|
|
.Mnemonic = 329,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_FXSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1065 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_FXSAVE64,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_FXSAVE,
|
|
.Mnemonic = 330,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_FXSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1066 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
|
|
{
|
|
.Instruction = ND_INS_FXTRACT,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 331,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1067 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
|
|
{
|
|
.Instruction = ND_INS_FYL2X,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 332,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1068 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
|
|
{
|
|
.Instruction = ND_INS_FYL2XP1,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 333,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xfb,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1069 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
|
|
{
|
|
.Instruction = ND_INS_GETSEC,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SMX,
|
|
.Mnemonic = 334,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = ND_CFF_SMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1070 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_GF2P8AFFINEINVQB,
|
|
.Category = ND_CAT_GFNI,
|
|
.IsaSet = ND_SET_GFNI,
|
|
.Mnemonic = 335,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_GFNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1071 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_GF2P8AFFINEQB,
|
|
.Category = ND_CAT_GFNI,
|
|
.IsaSet = ND_SET_GFNI,
|
|
.Mnemonic = 336,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_GFNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1072 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_GF2P8MULB,
|
|
.Category = ND_CAT_GFNI,
|
|
.IsaSet = ND_SET_GFNI,
|
|
.Mnemonic = 337,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_GFNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1073 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_HADDPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 338,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1074 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_HADDPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 339,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1075 Instruction:"HLT" Encoding:"0xF4"/""
|
|
{
|
|
.Instruction = ND_INS_HLT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 340,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1076 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_HRESET,
|
|
.Category = ND_CAT_HRESET,
|
|
.IsaSet = ND_SET_HRESET,
|
|
.Mnemonic = 341,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_HRESET,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1077 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_HSUBPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 342,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1078 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_HSUBPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 343,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1079 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1080 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1081 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1082 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1083 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1084 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1085 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1086 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_IDIV,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1087 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1088 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1089 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1090 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1091 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1092 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1093 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1094 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1095 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1096 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1097 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1098 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1099 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1100 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1101 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1102 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1103 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1104 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1105 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1106 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1107 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1108 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1109 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1110 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1111 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1112 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1113 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1114 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1115 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1116 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1117 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1118 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1119 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1120 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1121 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_IMUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1122 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_IN,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 346,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1123 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_IN,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 346,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1124 Instruction:"IN AL,DX" Encoding:"0xEC"/""
|
|
{
|
|
.Instruction = ND_INS_IN,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 346,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1125 Instruction:"IN eAX,DX" Encoding:"0xED"/""
|
|
{
|
|
.Instruction = ND_INS_IN,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 346,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1126 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1127 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1128 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1129 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1130 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1131 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1132 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1133 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1134 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1135 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1136 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1137 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0"/"VM"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1138 Instruction:"INC Zv" Encoding:"0x40"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1139 Instruction:"INC Zv" Encoding:"0x41"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1140 Instruction:"INC Zv" Encoding:"0x42"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1141 Instruction:"INC Zv" Encoding:"0x43"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1142 Instruction:"INC Zv" Encoding:"0x44"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1143 Instruction:"INC Zv" Encoding:"0x45"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1144 Instruction:"INC Zv" Encoding:"0x46"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1145 Instruction:"INC Zv" Encoding:"0x47"/"O"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1146 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1147 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_INC,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 347,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1148 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_INCSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 348,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1149 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_INCSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 349,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1150 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 350,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1151 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 350,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1152 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 351,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1153 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 351,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1154 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_INSERTPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 352,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1155 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_INSERTPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 352,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1156 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
|
|
{
|
|
.Instruction = ND_INS_INSERTQ,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 353,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1157 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INSERTQ,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 353,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1158 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 354,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1159 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
|
|
{
|
|
.Instruction = ND_INS_INS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 354,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1160 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_INT,
|
|
.Category = ND_CAT_INTERRUPT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 355,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_CETT,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1161 Instruction:"INT1" Encoding:"0xF1"/""
|
|
{
|
|
.Instruction = ND_INS_INT1,
|
|
.Category = ND_CAT_INTERRUPT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 356,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1162 Instruction:"INT3" Encoding:"0xCC"/""
|
|
{
|
|
.Instruction = ND_INS_INT3,
|
|
.Category = ND_CAT_INTERRUPT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 357,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_CETT,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1163 Instruction:"INTO" Encoding:"0xCE"/""
|
|
{
|
|
.Instruction = ND_INS_INTO,
|
|
.Category = ND_CAT_INTERRUPT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 358,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_CETT|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1164 Instruction:"INVD" Encoding:"0x0F 0x08"/""
|
|
{
|
|
.Instruction = ND_INS_INVD,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 359,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1165 Instruction:"INVEPT Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVEPT,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 360,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INVEPT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1166 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVEPT,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 360,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1167 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_INVLPG,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 361,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1168 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
|
|
{
|
|
.Instruction = ND_INS_INVLPGA,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 362,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1169 Instruction:"INVLPGB" Encoding:"NP 0x0F 0x01 /0xFE"/""
|
|
{
|
|
.Instruction = ND_INS_INVLPGB,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_INVLPGB,
|
|
.Mnemonic = 363,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_INVLPGB,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1170 Instruction:"INVPCID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVPCID,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 364,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INVPCID,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1171 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVPCID,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_INVPCID,
|
|
.Mnemonic = 364,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_INVPCID,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1172 Instruction:"INVVPID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVVPID,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 365,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INVVPID,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1173 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_INVVPID,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 365,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1174 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
|
|
{
|
|
.Instruction = ND_INS_IRET,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 366,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1175 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
|
|
{
|
|
.Instruction = ND_INS_IRET,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 367,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1176 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
|
|
{
|
|
.Instruction = ND_INS_IRET,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 368,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1177 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 369,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1178 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 369,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1179 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 370,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1180 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 370,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1181 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_JrCXZ,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 371,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1182 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_JrCXZ,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 372,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1183 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 373,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1184 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 373,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1185 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 374,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1186 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 374,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1187 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_JMPNR,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 375,
|
|
.ValidPrefixes = ND_PREF_BND,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1188 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_JMPNR,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 375,
|
|
.ValidPrefixes = ND_PREF_BND,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1189 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_JMPNI,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 375,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_DNT,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1190 Instruction:"JMPABS Aq" Encoding:"rex2 w:0 0xA1 cq"/"D"
|
|
{
|
|
.Instruction = ND_INS_JMPABS,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 376,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NO66|ND_FLAG_NO67|ND_FLAG_NOREP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_A, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1191 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_JMPE,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I64,
|
|
.Mnemonic = 377,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1192 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_JMPE,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I64,
|
|
.Mnemonic = 377,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1193 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
|
|
{
|
|
.Instruction = ND_INS_JMPFD,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 378,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1194 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_JMPFI,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 378,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_CETT|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1195 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 379,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1196 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 379,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1197 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 380,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1198 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 380,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1199 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 381,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1200 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 381,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1201 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 382,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1202 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 382,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1203 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 383,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1204 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 383,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1205 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 384,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1206 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 384,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1207 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 385,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1208 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 385,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1209 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 386,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1210 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 386,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1211 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 387,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1212 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 387,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1213 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 388,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1214 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 388,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1215 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_JrCXZ,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 389,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1216 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 390,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1217 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 390,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1218 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 391,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1219 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_Jcc,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 391,
|
|
.ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1220 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KADD,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 392,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1221 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KADD,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 393,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1222 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KADD,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 394,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1223 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KADD,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 395,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1224 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KAND,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 396,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1225 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KAND,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 397,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1226 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
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{
|
|
.Instruction = ND_INS_KANDN,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 398,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1227 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
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{
|
|
.Instruction = ND_INS_KANDN,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 399,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1228 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
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{
|
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.Instruction = ND_INS_KANDN,
|
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.Category = ND_CAT_KMASK,
|
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.IsaSet = ND_SET_AVX512BW,
|
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.Mnemonic = 400,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1229 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
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{
|
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.Instruction = ND_INS_KANDN,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 401,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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|
},
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},
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// Pos:1230 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
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{
|
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.Instruction = ND_INS_KAND,
|
|
.Category = ND_CAT_KMASK,
|
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.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 402,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
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OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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|
},
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|
},
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// Pos:1231 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
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{
|
|
.Instruction = ND_INS_KAND,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 403,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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|
},
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},
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// Pos:1232 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
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{
|
|
.Instruction = ND_INS_KMERGE2L1H,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 404,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
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|
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// Pos:1233 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
|
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{
|
|
.Instruction = ND_INS_KMERGE2L1L,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 405,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1234 Instruction:"KMOVB rKb,Mb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1235 Instruction:"KMOVB rKb,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1236 Instruction:"KMOVB Mb,rKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1237 Instruction:"KMOVB rKb,Ry" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1238 Instruction:"KMOVB Gy,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1239 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1240 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1241 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1242 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1243 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1244 Instruction:"KMOVD rKd,Md" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1245 Instruction:"KMOVD rKd,mKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1246 Instruction:"KMOVD Md,rKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1247 Instruction:"KMOVD rKd,Ry" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1248 Instruction:"KMOVD Gy,mKd" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1249 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1250 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1251 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1252 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1253 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1254 Instruction:"KMOVQ rKq,Mq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1255 Instruction:"KMOVQ rKq,mKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1256 Instruction:"KMOVQ Mq,rKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1257 Instruction:"KMOVQ rKq,Ry" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1258 Instruction:"KMOVQ Gy,mKq" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_KMOV,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1259 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1260 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1261 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K21,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1262 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1263 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KMOV,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1264 Instruction:"KMOVW rKw,Mw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_KMOV,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_VEX,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1265 Instruction:"KMOVW rKw,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_KMOV,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_VEX,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1266 Instruction:"KMOVW Mw,rKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem"/"MR"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_KMOV,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_VEX,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1267 Instruction:"KMOVW rKw,Ry" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_KMOV,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_VEX,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1268 Instruction:"KMOVW Gy,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_APX_F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_APX_EVEX_KMOV,
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.FpuFlags = 0,
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.EvexMode = ND_EVEXM_VEX,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_APX_F,
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.Operands =
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{
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1269 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K21,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1270 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K20,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1271 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K21,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1272 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K20,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1273 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KMOV,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 409,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K20,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1274 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KNOT,
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.Category = ND_CAT_KMASK,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 410,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_K20,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1275 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KNOT,
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.Category = ND_CAT_KMASK,
|
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.IsaSet = ND_SET_AVX512BW,
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.Mnemonic = 411,
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.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
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.FpuFlags = 0,
|
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.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
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.CpuidFlag = ND_CFF_AVX512BW,
|
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:1276 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
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{
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.Instruction = ND_INS_KNOT,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
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.Mnemonic = 412,
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|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
|
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.OpsCount = ND_OPS_CNT(2, 0),
|
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.TupleType = 0,
|
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.ExcType = ND_EXT_K20,
|
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.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
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.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
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.CpuidFlag = ND_CFF_AVX512BW,
|
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.Operands =
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|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1277 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KNOT,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 413,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1278 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 414,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1279 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 415,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1280 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 416,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1281 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KORTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 417,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1282 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KORTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 418,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1283 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KORTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 419,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1284 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KORTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 420,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1285 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 421,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1286 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTL,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 422,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1287 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTL,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 423,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1288 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTL,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 424,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1289 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTL,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 425,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1290 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 426,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1291 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1292 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 428,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1293 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_KSHIFTR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 429,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1294 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 430,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1295 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 431,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1296 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 432,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1297 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_KTEST,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 433,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1298 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KUNPCKBW,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 434,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1299 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KUNPCKDQ,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 435,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1300 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KUNPCKWD,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 436,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1301 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXNOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 437,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1302 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXNOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 438,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1303 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXNOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 439,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1304 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXNOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 440,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1305 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 441,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1306 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 442,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1307 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 443,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1308 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_KXOR,
|
|
.Category = ND_CAT_KMASK,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 444,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_K20,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1309 Instruction:"LAHF" Encoding:"0x9F"/""
|
|
{
|
|
.Instruction = ND_INS_LAHF,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 445,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1310 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LAR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 446,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1311 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LAR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 446,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1312 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LDDQU,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 447,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1313 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LDMXCSR,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 448,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1314 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LDS,
|
|
.Category = ND_CAT_SEGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 449,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_DS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1315 Instruction:"LDTILECFG Moq" Encoding:"evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LDTILECFG,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 450,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_EVEX_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1316 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LDTILECFG,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 450,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1317 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LEA,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 451,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_AG|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_0, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1318 Instruction:"LEAVE" Encoding:"0xC9"/""
|
|
{
|
|
.Instruction = ND_INS_LEAVE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_I186,
|
|
.Mnemonic = 452,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1319 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LES,
|
|
.Category = ND_CAT_SEGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 453,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_ES, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1320 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
|
|
{
|
|
.Instruction = ND_INS_LFENCE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 454,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1321 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LFS,
|
|
.Category = ND_CAT_SEGOP,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 455,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_FS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1322 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LGDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 456,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1323 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LGS,
|
|
.Category = ND_CAT_SEGOP,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 457,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_GS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1324 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LIDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 458,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1325 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_LKGS,
|
|
.Category = ND_CAT_LKGS,
|
|
.IsaSet = ND_SET_LKGS,
|
|
.Mnemonic = 459,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_LKGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1326 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_LKGS,
|
|
.Category = ND_CAT_LKGS,
|
|
.IsaSet = ND_SET_LKGS,
|
|
.Mnemonic = 459,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_LKGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1327 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_LLDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 460,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1328 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_LLWPCB,
|
|
.Category = ND_CAT_LWP,
|
|
.IsaSet = ND_SET_LWP,
|
|
.Mnemonic = 461,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_LWP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1329 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_LMSW,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 462,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1330 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LOADIWKEY,
|
|
.Category = ND_CAT_KL,
|
|
.IsaSet = ND_SET_KL,
|
|
.Mnemonic = 463,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_KL,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1331 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 464,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1332 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 464,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1333 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 465,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1334 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 465,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1335 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 466,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1336 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 466,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1337 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 467,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1338 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
|
|
{
|
|
.Instruction = ND_INS_LODS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 467,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1339 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_LOOP,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 468,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1340 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_LOOPNZ,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 469,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1341 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
|
|
{
|
|
.Instruction = ND_INS_LOOPZ,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 470,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1342 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LSL,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 471,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1343 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LSL,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 471,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1344 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LSS,
|
|
.Category = ND_CAT_SEGOP,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 472,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1345 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_LTR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 473,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1346 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_LWPINS,
|
|
.Category = ND_CAT_LWP,
|
|
.IsaSet = ND_SET_LWP,
|
|
.Mnemonic = 474,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_LWP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1347 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_LWPVAL,
|
|
.Category = ND_CAT_LWP,
|
|
.IsaSet = ND_SET_LWP,
|
|
.Mnemonic = 475,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_LWP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1348 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LZCNT,
|
|
.Category = ND_CAT_LZCNT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1349 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LZCNT,
|
|
.Category = ND_CAT_LZCNT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1350 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LZCNT,
|
|
.Category = ND_CAT_LZCNT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1351 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LZCNT,
|
|
.Category = ND_CAT_LZCNT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1352 Instruction:"LZCNT Gv,Ev" Encoding:"repz 0x0F 0xBD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_LZCNT,
|
|
.Category = ND_CAT_LZCNT,
|
|
.IsaSet = ND_SET_LZCNT,
|
|
.Mnemonic = 476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_LZCNT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1353 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MASKMOVDQU,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 477,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1354 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MASKMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 478,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_pDI, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1355 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MAXPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 479,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1356 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MAXPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 480,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1357 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MAXSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 481,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1358 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MAXSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 482,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1359 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
|
|
{
|
|
.Instruction = ND_INS_MCOMMIT,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_MCOMMIT,
|
|
.Mnemonic = 483,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MCOMMIT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1360 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
|
|
{
|
|
.Instruction = ND_INS_MFENCE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 484,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1361 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MINPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 485,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1362 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MINPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 486,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1363 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MINSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 487,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1364 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MINSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 488,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1365 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
|
|
{
|
|
.Instruction = ND_INS_MONITOR,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 489,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MONITOR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1366 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
|
|
{
|
|
.Instruction = ND_INS_MONITORX,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_MWAITT,
|
|
.Mnemonic = 490,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1367 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1368 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1369 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1370 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1371 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1372 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1373 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1374 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1375 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1376 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1377 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1378 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1379 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1380 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1381 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1382 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1383 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1384 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1385 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1386 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1387 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1388 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1389 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1390 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1391 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1392 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1393 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1394 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1395 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1396 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_MOV,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1397 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV_CR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1398 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV_DR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1399 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV_CR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1400 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV_DR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1401 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOV_TR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1402 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOV_TR,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1403 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 492,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1404 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 492,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1405 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 493,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1406 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 493,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1407 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1408 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1409 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1410 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1411 Instruction:"MOVBE Gv,Mv" Encoding:"NP 0x0F 0x38 0xF0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MOVBE,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVBE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1412 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MOVBE,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVBE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1413 Instruction:"MOVBE Mv,Gv" Encoding:"NP 0x0F 0x38 0xF1 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MOVBE,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVBE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1414 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVBE,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MOVBE,
|
|
.Mnemonic = 494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVBE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1415 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 495,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1416 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 495,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1417 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 495,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_P, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1418 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 495,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1419 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 496,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1420 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_MOVDIR64B,
|
|
.Category = ND_CAT_MOVDIR64B,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 497,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1421 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_MOVDIR64B,
|
|
.Category = ND_CAT_MOVDIR64B,
|
|
.IsaSet = ND_SET_MOVDIR64B,
|
|
.Mnemonic = 497,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVDIR64B,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1422 Instruction:"MOVDIRI My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVDIRI,
|
|
.Category = ND_CAT_MOVDIRI,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 498,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1423 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVDIRI,
|
|
.Category = ND_CAT_MOVDIRI,
|
|
.IsaSet = ND_SET_MOVDIRI,
|
|
.Mnemonic = 498,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MOVDIRI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1424 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVDQ2Q,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 499,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1425 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVDQA,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 500,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1426 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVDQA,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 500,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1427 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVDQU,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 501,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1428 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVDQU,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 501,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1429 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVHLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 502,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1430 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 503,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1431 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 503,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1432 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 504,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1433 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 504,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1434 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVLHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 505,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1435 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 506,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1436 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 506,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1437 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 507,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1438 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVMSKPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 508,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1439 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVMSKPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 509,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1440 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTDQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 510,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1441 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVNTDQA,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 511,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1442 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTI,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 512,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1443 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 513,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1444 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 514,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1445 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 515,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1446 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 516,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1447 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVNTSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE4A,
|
|
.Mnemonic = 517,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4A,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1448 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1449 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1450 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1451 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1452 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1453 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1454 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1455 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1456 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVQ2DQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 519,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1457 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 520,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1458 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 520,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1459 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 521,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1460 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 521,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1461 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 521,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1462 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 521,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1463 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSHDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 522,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1464 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSLDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 523,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1465 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 524,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1466 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 524,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1467 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 525,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1468 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 525,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1469 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 526,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1470 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
|
|
{
|
|
.Instruction = ND_INS_MOVS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 526,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1471 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSX,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 527,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1472 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSX,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 527,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1473 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVSXD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_LONGMODE,
|
|
.Mnemonic = 528,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1474 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 529,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1475 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 529,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1476 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 530,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1477 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_MOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 530,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1478 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVZX,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 531,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1479 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MOVZX,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 531,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1480 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_MPSADBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 532,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1481 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1482 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1483 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1484 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1485 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1486 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1487 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1488 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_MUL,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1489 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MULPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 534,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1490 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MULPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 535,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1491 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MULSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 536,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1492 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_MULSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 537,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1493 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_MULX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 538,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1494 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_MULX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 538,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1495 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
|
|
{
|
|
.Instruction = ND_INS_MWAIT,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SSE3,
|
|
.Mnemonic = 539,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MONITOR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1496 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
|
|
{
|
|
.Instruction = ND_INS_MWAITX,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_MWAITT,
|
|
.Mnemonic = 540,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1497 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1498 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1499 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1500 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1501 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1502 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1503 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1504 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1505 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1506 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1507 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1508 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1509 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1510 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
|
|
{
|
|
.Instruction = ND_INS_NEG,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 541,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1511 Instruction:"NOP" Encoding:"0x90"/""
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1512 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1513 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1514 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1515 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1516 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1517 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1518 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1519 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_NOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1520 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1521 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1522 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1523 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1524 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1525 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1526 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1527 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1528 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1529 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1530 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1531 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1532 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1533 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1534 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1535 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1536 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1537 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1538 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1539 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1540 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1545 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1546 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1547 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1549 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1550 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1551 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1552 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1553 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1554 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1555 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1556 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1557 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1558 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1565 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1567 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1569 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1571 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1572 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1573 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1574 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1575 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1576 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1577 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1578 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1579 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1580 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1581 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
|
|
{
|
|
.Instruction = ND_INS_NOP,
|
|
.Category = ND_CAT_WIDENOP,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1582 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1583 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1584 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1585 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1586 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1587 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1588 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1589 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
|
|
{
|
|
.Instruction = ND_INS_NOT,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 543,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1590 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1591 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1592 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1593 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1594 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1595 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1596 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1597 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1598 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1599 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1600 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1601 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1602 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1603 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1604 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1605 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1606 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1607 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1608 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1609 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1610 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1611 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1612 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1613 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1614 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1615 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1616 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1617 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1618 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1619 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1620 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1621 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1622 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1623 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1624 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1625 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1626 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1627 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1628 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1629 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1630 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1631 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1632 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1633 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1634 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1635 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1636 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1637 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1638 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1639 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1640 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1641 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1642 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1643 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_OR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 544,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1644 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 545,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1645 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_ORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 546,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1646 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_OUT,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 547,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1647 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_OUT,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 547,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1648 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
|
|
{
|
|
.Instruction = ND_INS_OUT,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 547,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1649 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
|
|
{
|
|
.Instruction = ND_INS_OUT,
|
|
.Category = ND_CAT_IO,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 547,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1650 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 548,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1651 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 548,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1652 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 549,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1653 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 549,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1654 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 550,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1655 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
|
|
{
|
|
.Instruction = ND_INS_OUTS,
|
|
.Category = ND_CAT_IOSTRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 550,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1656 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 551,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1657 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 551,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1658 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 552,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1659 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 552,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1660 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 553,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1661 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PABSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 553,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1662 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKSSDW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 554,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1663 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKSSDW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 554,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1664 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKSSWB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 555,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1665 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKSSWB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 555,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1666 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKUSDW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 556,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1667 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKUSWB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 557,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1668 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PACKUSWB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 557,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1669 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 558,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1670 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 558,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1671 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 559,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1672 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 559,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1673 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 560,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1674 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 560,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1675 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDSB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 561,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1676 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 561,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1677 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 562,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1678 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 562,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1679 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDUSB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 563,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1680 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDUSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 563,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1681 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDUSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 564,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1682 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDUSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 564,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1683 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 565,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1684 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PADDW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 565,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1685 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PALIGNR,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 566,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1686 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PALIGNR,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 566,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1687 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAND,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 567,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1688 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAND,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 567,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1689 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PANDN,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 568,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1690 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PANDN,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 568,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1691 Instruction:"PAUSE" Encoding:"repz 0x90"/""
|
|
{
|
|
.Instruction = ND_INS_PAUSE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_PAUSE,
|
|
.Mnemonic = 569,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:1692 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAVGB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 570,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1693 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAVGB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 570,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1694 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAVGUSB,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 571,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1695 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAVGW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 572,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1696 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PAVGW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 572,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1697 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PBLENDVB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 573,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1698 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PBLENDW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 574,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1699 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/""
|
|
{
|
|
.Instruction = ND_INS_PBNDKB,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_TSE,
|
|
.Mnemonic = 575,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_TSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1700 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PCLMULQDQ,
|
|
.Category = ND_CAT_PCLMULQDQ,
|
|
.IsaSet = ND_SET_PCLMULQDQ,
|
|
.Mnemonic = 576,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_PCLMULQDQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1701 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 577,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1702 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 577,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1703 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 578,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1704 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 578,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1705 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 579,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1706 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 580,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1707 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPEQW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 580,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1708 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PCMPESTRI,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 581,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1709 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PCMPESTRM,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 582,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1710 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 583,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1711 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 583,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1712 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 584,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1713 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 584,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1714 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 585,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1715 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 586,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1716 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PCMPGTW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 586,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1717 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PCMPISTRI,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 587,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1718 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PCMPISTRM,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE42,
|
|
.Mnemonic = 588,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE42,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1719 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
|
|
{
|
|
.Instruction = ND_INS_PCONFIG,
|
|
.Category = ND_CAT_PCONFIG,
|
|
.IsaSet = ND_SET_PCONFIG,
|
|
.Mnemonic = 589,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_PCONFIG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1720 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_PDEP,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 590,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1721 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_PDEP,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 590,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1722 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_PEXT,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 591,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1723 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_PEXT,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 591,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1724 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 592,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1725 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 592,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1726 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 593,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1727 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 593,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1728 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 594,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1729 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 594,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1730 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1731 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1732 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1733 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_PEXTRW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1734 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PF2ID,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 596,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1735 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PF2IW,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 597,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1736 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFACC,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 598,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1737 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFADD,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 599,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1738 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFCMPEQ,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 600,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1739 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFCMPGE,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 601,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1740 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFCMPGT,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 602,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1741 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFMAX,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 603,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1742 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFMIN,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 604,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1743 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFMUL,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 605,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1744 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFNACC,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 606,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1745 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFPNACC,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 607,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1746 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRCP,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 608,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1747 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRCPIT1,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 609,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1748 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRCPIT2,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 610,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1749 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRCPV,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 611,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1750 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRSQIT1,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 612,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1751 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRSQRT,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 613,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1752 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFRSQRTV,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 614,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1753 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFSUB,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 615,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1754 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PFSUBR,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 616,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1755 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 617,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1756 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 617,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1757 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 618,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1758 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 618,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1759 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 619,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1760 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHADDW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 619,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1761 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHMINPOSUW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 620,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1762 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 621,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1763 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 621,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1764 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 622,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1765 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 622,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1766 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 623,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1767 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PHSUBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 623,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1768 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PI2FD,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 624,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1769 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PI2FW,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 625,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1770 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 626,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1771 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 626,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1772 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 627,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1773 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 628,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1774 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 629,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1775 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 629,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1776 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 629,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1777 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PINSRW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 629,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1778 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMADDUBSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 630,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1779 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMADDUBSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 630,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1780 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMADDWD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 631,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1781 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMADDWD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 631,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1782 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 632,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1783 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 633,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1784 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 634,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1785 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 634,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1786 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXUB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 635,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1787 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXUB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 635,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1788 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXUD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 636,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1789 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMAXUW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 637,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1790 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 638,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1791 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 639,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1792 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 640,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1793 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 640,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1794 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINUB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 641,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1795 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINUB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 641,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1796 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINUD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 642,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1797 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMINUW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 643,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1798 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVMSKB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 644,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1799 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVMSKB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 644,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1800 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXBD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 645,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1801 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXBQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 646,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1802 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 647,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1803 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 648,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1804 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXWD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 649,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1805 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVSXWQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 650,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1806 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXBD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 651,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1807 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXBQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 652,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1808 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 653,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1809 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 654,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1810 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXWD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 655,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1811 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMOVZXWQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 656,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1812 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 657,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1813 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHRSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 658,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1814 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHRSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 658,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1815 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHRW,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 659,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1816 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHUW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 660,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1817 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHUW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 660,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1818 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 661,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1819 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULHW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 661,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1820 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULLD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 662,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1821 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULLW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 663,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1822 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 663,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1823 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULUDQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 664,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1824 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PMULUDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 664,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1825 Instruction:"POP ES" Encoding:"0x07"/""
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1826 Instruction:"POP SS" Encoding:"0x17"/""
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1827 Instruction:"POP DS" Encoding:"0x1F"/""
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1828 Instruction:"POP Zv" Encoding:"0x58"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1829 Instruction:"POP Zv" Encoding:"0x59"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1830 Instruction:"POP Zv" Encoding:"0x5A"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1831 Instruction:"POP Zv" Encoding:"0x5B"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1832 Instruction:"POP Zv" Encoding:"0x5C"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1833 Instruction:"POP Zv" Encoding:"0x5D"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1834 Instruction:"POP Zv" Encoding:"0x5E"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1835 Instruction:"POP Zv" Encoding:"0x5F"/"O"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1836 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1837 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1838 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
|
|
{
|
|
.Instruction = ND_INS_POP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1839 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM"
|
|
{
|
|
.Instruction = ND_INS_POP2,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 666,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_PP2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1840 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM"
|
|
{
|
|
.Instruction = ND_INS_POP2P,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 667,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_PP2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1841 Instruction:"POPA" Encoding:"ds16 0x61"/""
|
|
{
|
|
.Instruction = ND_INS_POPA,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 668,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1842 Instruction:"POPAD" Encoding:"ds32 0x61"/""
|
|
{
|
|
.Instruction = ND_INS_POPAD,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 669,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1843 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POPCNT,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1844 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POPCNT,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1845 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POPCNT,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1846 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POPCNT,
|
|
.Category = ND_CAT_APX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1847 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POPCNT,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_POPCNT,
|
|
.Mnemonic = 670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_POPCNT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1848 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
|
|
{
|
|
.Instruction = ND_INS_POPF,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 671,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1849 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
|
|
{
|
|
.Instruction = ND_INS_POPF,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 672,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1850 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
|
|
{
|
|
.Instruction = ND_INS_POPF,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 673,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1851 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1852 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1853 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1854 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1855 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1856 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1857 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1858 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O"
|
|
{
|
|
.Instruction = ND_INS_POPP,
|
|
.Category = ND_CAT_POP,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1859 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POR,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 675,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1860 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_POR,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 675,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1861 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCH,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 676,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1862 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCH,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 676,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1863 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCH,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 676,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1864 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCH,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 676,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1865 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHE,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 677,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1866 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHIT0,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCHITI,
|
|
.Mnemonic = 678,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_PREFETCHITI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1867 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHIT1,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCHITI,
|
|
.Mnemonic = 679,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_PREFETCHITI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1868 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHM,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 680,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1869 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHNTA,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 681,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1870 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHNTA,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 681,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1871 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT0,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 682,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1872 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT0,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 682,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1873 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT1,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 683,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1874 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT1,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 683,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1875 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT2,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 684,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1876 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHT2,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 684,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1877 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHW,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 685,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1878 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_PREFETCHWT1,
|
|
.Category = ND_CAT_PREFETCH,
|
|
.IsaSet = ND_SET_PREFETCH_NOP,
|
|
.Mnemonic = 686,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1879 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSADBW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 687,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1880 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSADBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 687,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1881 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSHUFB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 688,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1882 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSHUFB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 688,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1883 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PSHUFD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 689,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1884 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PSHUFHW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 690,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1885 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PSHUFLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 691,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1886 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_PSHUFW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 692,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1887 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGNB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 693,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1888 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGNB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 693,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1889 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGND,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 694,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1890 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGND,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 694,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1891 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGNW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 695,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1892 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSIGNW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSSE3,
|
|
.Mnemonic = 695,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSSE3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1893 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 696,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1894 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 696,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1895 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 696,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1896 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 696,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1897 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 697,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1898 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 698,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1899 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 698,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1900 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 698,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1901 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 698,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1902 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 699,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1903 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSLLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 699,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1904 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 699,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1905 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSLLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 699,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1906 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
|
|
{
|
|
.Instruction = ND_INS_PSMASH,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SNP,
|
|
.Mnemonic = 700,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_SNP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1907 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRAD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 701,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1908 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRAD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 701,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1909 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRAD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 701,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1910 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRAD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 701,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1911 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRAW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 702,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1912 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRAW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 702,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1913 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRAW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 702,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1914 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRAW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 702,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1915 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 703,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1916 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 703,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1917 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 703,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1918 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 703,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1919 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 704,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1920 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 705,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1921 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 705,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1922 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 705,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1923 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 705,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1924 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 706,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1925 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_PSRLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 706,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1926 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 706,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1927 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSRLW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 706,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1928 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 707,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1929 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 707,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1930 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 708,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1931 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 708,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1932 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 709,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1933 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 709,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1934 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBSB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 710,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1935 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 710,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1936 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 711,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1937 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 711,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1938 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBUSB,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 712,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1939 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBUSB,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 712,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1940 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBUSW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 713,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1941 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBUSW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 713,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1942 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 714,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1943 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSUBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 714,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1944 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PSWAPD,
|
|
.Category = ND_CAT_3DNOW,
|
|
.IsaSet = ND_SET_3DNOW,
|
|
.Mnemonic = 715,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_3DNOW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1945 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PTEST,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 716,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1946 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_PTWRITE,
|
|
.Category = ND_CAT_PTWRITE,
|
|
.IsaSet = ND_SET_PTWRITE,
|
|
.Mnemonic = 717,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NO66|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_PTWRITE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1947 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHBW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 718,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1948 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 718,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1949 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHDQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 719,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1950 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 719,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1951 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHQDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 720,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1952 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHWD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 721,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1953 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKHWD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 721,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1954 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLBW,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 722,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1955 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLBW,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 722,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1956 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLDQ,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 723,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1957 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 723,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1958 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLQDQ,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 724,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1959 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLWD,
|
|
.Category = ND_CAT_MMX,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 725,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1960 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PUNPCKLWD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 725,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1961 Instruction:"PUSH ES" Encoding:"0x06"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1962 Instruction:"PUSH CS" Encoding:"0x0E"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1963 Instruction:"PUSH SS" Encoding:"0x16"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1964 Instruction:"PUSH DS" Encoding:"0x1E"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1965 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1966 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1967 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1968 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1969 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1970 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1971 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1972 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1973 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1974 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1975 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1976 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1977 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
|
|
{
|
|
.Instruction = ND_INS_PUSH,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1978 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM"
|
|
{
|
|
.Instruction = ND_INS_PUSH2,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 727,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_PP2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1979 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM"
|
|
{
|
|
.Instruction = ND_INS_PUSH2P,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 728,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_PP2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1980 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
|
|
{
|
|
.Instruction = ND_INS_PUSHA,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 729,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1981 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
|
|
{
|
|
.Instruction = ND_INS_PUSHAD,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 730,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1982 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
|
|
{
|
|
.Instruction = ND_INS_PUSHF,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 731,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1983 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
|
|
{
|
|
.Instruction = ND_INS_PUSHF,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 732,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1984 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
|
|
{
|
|
.Instruction = ND_INS_PUSHF,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 733,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1985 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1986 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1987 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1988 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1989 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1990 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1991 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1992 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O"
|
|
{
|
|
.Instruction = ND_INS_PUSHP,
|
|
.Category = ND_CAT_PUSH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1993 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
|
|
{
|
|
.Instruction = ND_INS_PVALIDATE,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SNP,
|
|
.Mnemonic = 735,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SNP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1994 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PXOR,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_MMX,
|
|
.Mnemonic = 736,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_MMX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1995 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_PXOR,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 736,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1996 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1997 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1998 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:1999 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2000 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2001 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2002 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2003 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2004 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2005 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2006 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2007 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2008 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2009 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2010 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2011 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2012 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2013 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2014 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2015 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2016 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2017 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2018 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2019 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2020 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2021 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2022 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2023 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2024 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2025 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2026 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2027 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2028 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2029 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2030 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2031 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2032 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2033 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2034 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2035 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2036 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2037 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2038 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_RCPPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 738,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2039 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_RCPSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 739,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2040 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2041 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2042 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2043 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2044 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2045 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2046 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2047 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2048 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2049 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2050 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2051 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2052 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2053 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2054 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2055 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2056 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2057 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2058 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2059 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2060 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2061 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2062 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2063 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2064 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2065 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2066 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2067 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2068 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2069 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2070 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2071 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2072 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2073 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2074 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2075 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2076 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2077 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2078 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2079 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2080 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2081 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
|
|
{
|
|
.Instruction = ND_INS_RCR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2082 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDFSBASE,
|
|
.Category = ND_CAT_RDWRFSGS,
|
|
.IsaSet = ND_SET_RDWRFSGS,
|
|
.Mnemonic = 741,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_RDWRFSGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2083 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDGSBASE,
|
|
.Category = ND_CAT_RDWRFSGS,
|
|
.IsaSet = ND_SET_RDWRFSGS,
|
|
.Mnemonic = 742,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_RDWRFSGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2084 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
|
|
{
|
|
.Instruction = ND_INS_RDMSR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_PENTIUMREAL,
|
|
.Mnemonic = 743,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = ND_CFF_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2085 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/""
|
|
{
|
|
.Instruction = ND_INS_RDMSRLIST,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_MSRLIST,
|
|
.Mnemonic = 744,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_MSRLIST,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2086 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDPID,
|
|
.Category = ND_CAT_RDPID,
|
|
.IsaSet = ND_SET_RDPID,
|
|
.Mnemonic = 745,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDPID,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_yf, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2087 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
|
|
{
|
|
.Instruction = ND_INS_RDPKRU,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_PKU,
|
|
.Mnemonic = 746,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_PKU,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2088 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
|
|
{
|
|
.Instruction = ND_INS_RDPMC,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_RDPMC,
|
|
.Mnemonic = 747,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2089 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/""
|
|
{
|
|
.Instruction = ND_INS_RDPRU,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_RDPRU,
|
|
.Mnemonic = 748,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDPRU,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2090 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDRAND,
|
|
.Category = ND_CAT_RDRAND,
|
|
.IsaSet = ND_SET_RDRAND,
|
|
.Mnemonic = 749,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDRAND,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2091 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDRAND,
|
|
.Category = ND_CAT_RDRAND,
|
|
.IsaSet = ND_SET_RDRAND,
|
|
.Mnemonic = 749,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_S66|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDRAND,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2092 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDSEED,
|
|
.Category = ND_CAT_RDSEED,
|
|
.IsaSet = ND_SET_RDSEED,
|
|
.Mnemonic = 750,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDSEED,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2093 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RDSEED,
|
|
.Category = ND_CAT_RDSEED,
|
|
.IsaSet = ND_SET_RDSEED,
|
|
.Mnemonic = 750,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_S66|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDSEED,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2094 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RSSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 751,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2095 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_RSSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 752,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2096 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
|
|
{
|
|
.Instruction = ND_INS_RDTSC,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_PENTIUMREAL,
|
|
.Mnemonic = 753,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2097 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
|
|
{
|
|
.Instruction = ND_INS_RDTSCP,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_RDTSCP,
|
|
.Mnemonic = 754,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RDTSCP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2098 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
|
|
{
|
|
.Instruction = ND_INS_RETF,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 755,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2099 Instruction:"RETF" Encoding:"0xCB"/""
|
|
{
|
|
.Instruction = ND_INS_RETF,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 755,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2100 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
|
|
{
|
|
.Instruction = ND_INS_RETN,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 756,
|
|
.ValidPrefixes = ND_PREF_BND,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2101 Instruction:"RETN" Encoding:"0xC3"/""
|
|
{
|
|
.Instruction = ND_INS_RETN,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 756,
|
|
.ValidPrefixes = ND_PREF_BND,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2102 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
|
|
{
|
|
.Instruction = ND_INS_RMPADJUST,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SNP,
|
|
.Mnemonic = 757,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_SNP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2103 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/""
|
|
{
|
|
.Instruction = ND_INS_RMPQUERY,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SNP,
|
|
.Mnemonic = 758,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_RMPQUERY,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2104 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
|
|
{
|
|
.Instruction = ND_INS_RMPUPDATE,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SNP,
|
|
.Mnemonic = 759,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_SNP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_pCX, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2105 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2106 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2107 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2108 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2109 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2110 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2111 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2112 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2113 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2114 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2115 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2116 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2117 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2118 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2119 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2120 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2121 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2122 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2123 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2124 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2125 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2126 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2127 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2128 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2129 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2130 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2131 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2132 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2133 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2134 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2135 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2136 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2137 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2138 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2139 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2140 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2141 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2142 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2143 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2144 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2145 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2146 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROL,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2147 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2148 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2149 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2150 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2151 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2152 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2153 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2154 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2155 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2156 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2157 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2158 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2159 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2160 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2161 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2162 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2163 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2164 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2165 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2166 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2167 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2168 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2169 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2170 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2171 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2172 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2173 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2174 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2175 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2176 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2177 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2178 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2179 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2180 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2181 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2182 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2183 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2184 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2185 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2186 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2187 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2188 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
|
|
{
|
|
.Instruction = ND_INS_ROR,
|
|
.Category = ND_CAT_ROTATE,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 761,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2189 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_RORX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 762,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2190 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_RORX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 762,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2191 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_ROUNDPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2192 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_ROUNDPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 764,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2193 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_ROUNDSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 765,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2194 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_ROUNDSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE4,
|
|
.Mnemonic = 766,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2195 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
|
|
{
|
|
.Instruction = ND_INS_RSM,
|
|
.Category = ND_CAT_SYSRET,
|
|
.IsaSet = ND_SET_I486,
|
|
.Mnemonic = 767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2196 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_RSQRTPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 768,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2197 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_RSQRTSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 769,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2198 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_RSTORSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 770,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2199 Instruction:"SAHF" Encoding:"0x9E"/""
|
|
{
|
|
.Instruction = ND_INS_SAHF,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 771,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2200 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2201 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2202 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2203 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2204 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2205 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2206 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2207 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2208 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2209 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2210 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2211 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2212 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2213 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2214 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2215 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2216 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2217 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2218 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2219 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2220 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2221 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2222 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2223 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2224 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2225 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2226 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2227 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2228 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2229 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2230 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2231 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2232 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2233 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2234 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2235 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2236 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2237 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2238 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2239 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2240 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2241 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2242 Instruction:"SALC" Encoding:"0xD6"/""
|
|
{
|
|
.Instruction = ND_INS_SALC,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 773,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2243 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2244 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2245 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2246 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2247 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2248 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2249 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2250 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2251 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2252 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2253 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2254 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2255 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2256 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2257 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2258 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2259 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2260 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2261 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2262 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2263 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2264 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2265 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2266 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2267 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2268 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2269 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2270 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2271 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2272 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2273 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2274 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2275 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2276 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2277 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2278 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2279 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2280 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2281 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2282 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2283 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2284 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SAR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2285 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SARX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 775,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2286 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SARX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 775,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2287 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
|
|
{
|
|
.Instruction = ND_INS_SAVEPREVSSP,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 776,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SHS, ND_OPS_12, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2288 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2289 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2290 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2291 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2292 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2293 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2294 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2295 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2296 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2297 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2298 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2299 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2300 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2301 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2302 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2303 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2304 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2305 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2306 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2307 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2308 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2309 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2310 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2311 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2312 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2313 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2314 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2315 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2316 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2317 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2318 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2319 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SBB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 777,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2320 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 778,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2321 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 778,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2322 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 779,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2323 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 779,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2324 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 780,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2325 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 780,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2326 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 781,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2327 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
|
|
{
|
|
.Instruction = ND_INS_SCAS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 781,
|
|
.ValidPrefixes = ND_PREF_REPC,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2328 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
|
|
{
|
|
.Instruction = ND_INS_SEAMCALL,
|
|
.Category = ND_CAT_TDX,
|
|
.IsaSet = ND_SET_TDX,
|
|
.Mnemonic = 782,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2329 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
|
|
{
|
|
.Instruction = ND_INS_SEAMOPS,
|
|
.Category = ND_CAT_TDX,
|
|
.IsaSet = ND_SET_TDX,
|
|
.Mnemonic = 783,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rR8, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rR9, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2330 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
|
|
{
|
|
.Instruction = ND_INS_SEAMRET,
|
|
.Category = ND_CAT_TDX,
|
|
.IsaSet = ND_SET_TDX,
|
|
.Mnemonic = 784,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2331 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_SENDUIPI,
|
|
.Category = ND_CAT_UINTR,
|
|
.IsaSet = ND_SET_UINTR,
|
|
.Mnemonic = 785,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_UINTR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2332 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
|
|
{
|
|
.Instruction = ND_INS_SERIALIZE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SERIALIZE,
|
|
.Mnemonic = 786,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SERIALIZE,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2333 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 787,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2334 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 787,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2335 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 788,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2336 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 788,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2337 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 789,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2338 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 789,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2339 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 790,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2340 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 790,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2341 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 791,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2342 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 791,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2343 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 792,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2344 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 792,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_CF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2345 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 793,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2346 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 793,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2347 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 794,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2348 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 794,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2349 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 795,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2350 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 795,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2351 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 796,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2352 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 796,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2353 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 797,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2354 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 797,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2355 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 798,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2356 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 798,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2357 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 799,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2358 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 799,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_OF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2359 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 800,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2360 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 800,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_PF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2361 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 801,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2362 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 801,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_SF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2363 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
|
|
{
|
|
.Instruction = ND_INS_SETSSBSY,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 802,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SHS0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2364 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 803,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ZU,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2365 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
|
|
{
|
|
.Instruction = ND_INS_SETcc,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 803,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_ZF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2366 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
|
|
{
|
|
.Instruction = ND_INS_SFENCE,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 804,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2367 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_SGDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 805,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2368 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1MSG1,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 806,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2369 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1MSG1,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 806,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2370 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1MSG2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 807,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2371 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1MSG2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 807,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2372 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1NEXTE,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 808,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2373 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA1NEXTE,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 808,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2374 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_SHA1RNDS4,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 809,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2375 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_SHA1RNDS4,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 809,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2376 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256MSG1,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 810,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2377 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256MSG1,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 810,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2378 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256MSG2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 811,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2379 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256MSG2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 811,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2380 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256RNDS2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 812,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_SHA,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2381 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SHA256RNDS2,
|
|
.Category = ND_CAT_SHA,
|
|
.IsaSet = ND_SET_SHA,
|
|
.Mnemonic = 812,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2382 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2383 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2384 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2385 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2386 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2387 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2388 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2389 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2390 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2391 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2392 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2393 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2394 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2395 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2396 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2397 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2398 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2399 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2400 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2401 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2402 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2403 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2404 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2405 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2406 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2407 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2408 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2409 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2410 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2411 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2412 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2413 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2414 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2415 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2416 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2417 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2418 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2419 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2420 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2421 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2422 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2423 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHL,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 813,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2424 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2425 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2426 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2427 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2428 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2429 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2430 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2431 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2432 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2433 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2434 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2435 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2436 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2437 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2438 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2439 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2440 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2441 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHLD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 814,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2442 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SHLX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 815,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2443 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SHLX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 815,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2444 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2445 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2446 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2447 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2448 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2449 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2450 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2451 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2452 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2453 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2454 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2455 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2456 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2457 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2458 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2459 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2460 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2461 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2462 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2463 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2464 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2465 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2466 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2467 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2468 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2469 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2470 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2471 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2472 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2473 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2474 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2475 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2476 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2477 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2478 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2479 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2480 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2481 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2482 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2483 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2484 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2485 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
|
|
{
|
|
.Instruction = ND_INS_SHR,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 816,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2486 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2487 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2488 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2489 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2490 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2491 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2492 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2493 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2494 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2495 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2496 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2497 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(4, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2498 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI"
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{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
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|
|
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// Pos:2499 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
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// Pos:2500 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI"
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{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
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|
|
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// Pos:2501 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC"
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{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2502 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2503 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
|
|
{
|
|
.Instruction = ND_INS_SHRD,
|
|
.Category = ND_CAT_SHIFT,
|
|
.IsaSet = ND_SET_I386,
|
|
.Mnemonic = 817,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2504 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SHRX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 818,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_BMI,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2505 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_SHRX,
|
|
.Category = ND_CAT_BMI2,
|
|
.IsaSet = ND_SET_BMI2,
|
|
.Mnemonic = 818,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_13,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2506 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_SHUFPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 819,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2507 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_SHUFPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 820,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2508 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_SIDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 821,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2509 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
|
|
{
|
|
.Instruction = ND_INS_SKINIT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 822,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2510 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_SLDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 823,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2511 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_SLDT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 823,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2512 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_SLWPCB,
|
|
.Category = ND_CAT_LWP,
|
|
.IsaSet = ND_SET_LWP,
|
|
.Mnemonic = 824,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_LWP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2513 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_SMSW,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 825,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2514 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_SMSW,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286REAL,
|
|
.Mnemonic = 825,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2515 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_SPFLT,
|
|
.Category = ND_CAT_UNKNOWN,
|
|
.IsaSet = ND_SET_UNKNOWN,
|
|
.Mnemonic = 826,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2516 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SQRTPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 827,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2517 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SQRTPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 828,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2518 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SQRTSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 829,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2519 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SQRTSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 830,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2520 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
|
|
{
|
|
.Instruction = ND_INS_STAC,
|
|
.Category = ND_CAT_SMAP,
|
|
.IsaSet = ND_SET_SMAP,
|
|
.Mnemonic = 831,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_AC,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SMAP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2521 Instruction:"STC" Encoding:"0xF9"/""
|
|
{
|
|
.Instruction = ND_INS_STC,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 832,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_CF,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2522 Instruction:"STD" Encoding:"0xFD"/""
|
|
{
|
|
.Instruction = ND_INS_STD,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 833,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_DF,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2523 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
|
|
{
|
|
.Instruction = ND_INS_STGI,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 834,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2524 Instruction:"STI" Encoding:"0xFB"/""
|
|
{
|
|
.Instruction = ND_INS_STI,
|
|
.Category = ND_CAT_FLAGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 835,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0|NDR_RFLAG_IF,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2525 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_STMXCSR,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 836,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2526 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 837,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2527 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 837,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2528 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 838,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2529 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 838,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2530 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 839,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2531 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 839,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2532 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 840,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2533 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
|
|
{
|
|
.Instruction = ND_INS_STOS,
|
|
.Category = ND_CAT_STRINGOP,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 840,
|
|
.ValidPrefixes = ND_PREF_REP,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0|NDR_RFLAG_DF,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2534 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_STR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 841,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2535 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_STR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 841,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2536 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_STTILECFG,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 842,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_EVEX_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2537 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_STTILECFG,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 842,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2538 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
|
|
{
|
|
.Instruction = ND_INS_STUI,
|
|
.Category = ND_CAT_UINTR,
|
|
.IsaSet = ND_SET_UINTR,
|
|
.Mnemonic = 843,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_UINTR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2539 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2540 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2541 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2542 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2543 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2544 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2545 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2546 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2547 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2548 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2549 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2550 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2551 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2552 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2553 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2554 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2555 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2556 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2557 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2558 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2559 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2560 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2561 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2562 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2563 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2564 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2565 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2566 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2567 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2568 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2569 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2570 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2571 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2572 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2573 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2574 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2575 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2576 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2577 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2578 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2579 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2580 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2581 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2582 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2583 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2584 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2585 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2586 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2587 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2588 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2589 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2590 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2591 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2592 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_SUB,
|
|
.Category = ND_CAT_ARITH,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 844,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2593 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUBPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 845,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2594 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUBPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 846,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2595 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUBSD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 847,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2596 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_SUBSS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 848,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2597 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
|
|
{
|
|
.Instruction = ND_INS_SWAPGS,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_LONGMODE,
|
|
.Mnemonic = 849,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2598 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
|
|
{
|
|
.Instruction = ND_INS_SYSCALL,
|
|
.Category = ND_CAT_SYSCALL,
|
|
.IsaSet = ND_SET_AMD,
|
|
.Mnemonic = 850,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 10),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_CETT,
|
|
.CpuidFlag = ND_CFF_FSC,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_LSTAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_FMASK, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2599 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
|
|
{
|
|
.Instruction = ND_INS_SYSENTER,
|
|
.Category = ND_CAT_SYSCALL,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 851,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 9),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_IF,
|
|
.Attributes = ND_FLAG_CETT|ND_FLAG_NOREX2,
|
|
.CpuidFlag = ND_CFF_SEP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SCS, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SESP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SEIP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2600 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
|
|
{
|
|
.Instruction = ND_INS_SYSEXIT,
|
|
.Category = ND_CAT_SYSRET,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 852,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 5),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
|
|
.CpuidFlag = ND_CFF_SEP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2601 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
|
|
{
|
|
.Instruction = ND_INS_SYSRET,
|
|
.Category = ND_CAT_SYSRET,
|
|
.IsaSet = ND_SET_AMD,
|
|
.Mnemonic = 853,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 8),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = ND_CFF_FSC,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2602 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
|
|
{
|
|
.Instruction = ND_INS_T1MSKC,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 854,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2603 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TCMMIMFP16PS,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXCOMPLEX,
|
|
.Mnemonic = 855,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXCOMPLEX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2604 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TCMMRLFP16PS,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXCOMPLEX,
|
|
.Mnemonic = 856,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXCOMPLEX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2605 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
|
|
{
|
|
.Instruction = ND_INS_TDCALL,
|
|
.Category = ND_CAT_TDX,
|
|
.IsaSet = ND_SET_TDX,
|
|
.Mnemonic = 857,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2606 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPBF16PS,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXBF16,
|
|
.Mnemonic = 858,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXBF16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2607 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPBSSD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXINT8,
|
|
.Mnemonic = 859,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2608 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPBSUD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXINT8,
|
|
.Mnemonic = 860,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2609 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPBUSD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXINT8,
|
|
.Mnemonic = 861,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2610 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPBUUD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXINT8,
|
|
.Mnemonic = 862,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2611 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/""
|
|
{
|
|
.Instruction = ND_INS_TDPFP16PS,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXFP16,
|
|
.Mnemonic = 863,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXFP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2612 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2613 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2614 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2615 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_NOREX2,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2616 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2617 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2618 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2619 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_TEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 864,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2620 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
|
|
{
|
|
.Instruction = ND_INS_TESTUI,
|
|
.Category = ND_CAT_UINTR,
|
|
.IsaSet = ND_SET_UINTR,
|
|
.Mnemonic = 865,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_UINTR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2621 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILELOADD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 866,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_EVEX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2622 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILELOADD,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 866,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2623 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILELOADDT1,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 867,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_EVEX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2624 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILELOADDT1,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 867,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2625 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
|
|
{
|
|
.Instruction = ND_INS_TILERELEASE,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 868,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2626 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILESTORED,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 869,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_EVEX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2627 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
|
|
{
|
|
.Instruction = ND_INS_TILESTORED,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 869,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2628 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
|
|
{
|
|
.Instruction = ND_INS_TILEZERO,
|
|
.Category = ND_CAT_AMX,
|
|
.IsaSet = ND_SET_AMXTILE,
|
|
.Mnemonic = 870,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_AMX_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_AMXTILE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2629 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/""
|
|
{
|
|
.Instruction = ND_INS_TLBSYNC,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_INVLPGB,
|
|
.Mnemonic = 871,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_INVLPGB,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2630 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_TPAUSE,
|
|
.Category = ND_CAT_WAITPKG,
|
|
.IsaSet = ND_SET_WAITPKG,
|
|
.Mnemonic = 872,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_WAITPKG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2631 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_TZCNT,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 873,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2632 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_TZCNT,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 873,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2633 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_TZCNT,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 873,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2634 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_TZCNT,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 873,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2635 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_TZCNT,
|
|
.Category = ND_CAT_BMI1,
|
|
.IsaSet = ND_SET_BMI1,
|
|
.Mnemonic = 873,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_BMI1,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2636 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
|
|
{
|
|
.Instruction = ND_INS_TZMSK,
|
|
.Category = ND_CAT_BITBYTE,
|
|
.IsaSet = ND_SET_TBM,
|
|
.Mnemonic = 874,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TBM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2637 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UCOMISD,
|
|
.Category = ND_CAT_SSE2,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 875,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2638 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UCOMISS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 876,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2639 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UD0,
|
|
.Category = ND_CAT_UD,
|
|
.IsaSet = ND_SET_UD,
|
|
.Mnemonic = 877,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2640 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UD1,
|
|
.Category = ND_CAT_UD,
|
|
.IsaSet = ND_SET_UD,
|
|
.Mnemonic = 878,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2641 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
|
|
{
|
|
.Instruction = ND_INS_UD2,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_PPRO,
|
|
.Mnemonic = 879,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:2642 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
|
|
{
|
|
.Instruction = ND_INS_UIRET,
|
|
.Category = ND_CAT_RET,
|
|
.IsaSet = ND_SET_UINTR,
|
|
.Mnemonic = 880,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 6),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_UINTR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2643 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_UMONITOR,
|
|
.Category = ND_CAT_WAITPKG,
|
|
.IsaSet = ND_SET_WAITPKG,
|
|
.Mnemonic = 881,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_WAITPKG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2644 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_UMWAIT,
|
|
.Category = ND_CAT_WAITPKG,
|
|
.IsaSet = ND_SET_WAITPKG,
|
|
.Mnemonic = 882,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_WAITPKG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2645 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UNPCKHPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 883,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2646 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UNPCKHPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 884,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2647 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UNPCKLPD,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 885,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2648 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UNPCKLPS,
|
|
.Category = ND_CAT_SSE,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 886,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2649 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_URDMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 887,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_USER_MSR,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2650 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI"
|
|
{
|
|
.Instruction = ND_INS_URDMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 887,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2651 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_URDMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_USER_MSR,
|
|
.Mnemonic = 887,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_USER_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2652 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI"
|
|
{
|
|
.Instruction = ND_INS_URDMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_USER_MSR,
|
|
.Mnemonic = 887,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_USER_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2653 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UWRMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 888,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_USER_MSR,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2654 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM"
|
|
{
|
|
.Instruction = ND_INS_UWRMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 888,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_VEX,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2655 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_UWRMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_USER_MSR,
|
|
.Mnemonic = 888,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_USER_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2656 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM"
|
|
{
|
|
.Instruction = ND_INS_UWRMSR,
|
|
.Category = ND_CAT_USER_MSR,
|
|
.IsaSet = ND_SET_USER_MSR,
|
|
.Mnemonic = 888,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_USER_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2657 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_V4FMADDPS,
|
|
.Category = ND_CAT_VFMAPS,
|
|
.IsaSet = ND_SET_AVX5124FMAPS,
|
|
.Mnemonic = 889,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124FMAPS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2658 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_V4FMADDSS,
|
|
.Category = ND_CAT_VFMAPS,
|
|
.IsaSet = ND_SET_AVX5124FMAPS,
|
|
.Mnemonic = 890,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124FMAPS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2659 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_V4FNMADDPS,
|
|
.Category = ND_CAT_VFMAPS,
|
|
.IsaSet = ND_SET_AVX5124FMAPS,
|
|
.Mnemonic = 891,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124FMAPS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2660 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_V4FNMADDSS,
|
|
.Category = ND_CAT_VFMAPS,
|
|
.IsaSet = ND_SET_AVX5124FMAPS,
|
|
.Mnemonic = 892,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124FMAPS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2661 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 893,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2662 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 893,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2663 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 894,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2664 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 895,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2665 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 895,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2666 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 896,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2667 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 896,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2668 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 897,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2669 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 898,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2670 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 898,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2671 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSUBPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 899,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2672 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VADDSUBPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 900,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2673 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESDEC,
|
|
.Category = ND_CAT_VAES,
|
|
.IsaSet = ND_SET_VAES,
|
|
.Mnemonic = 901,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VAES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2674 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESDEC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 901,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2675 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESDECLAST,
|
|
.Category = ND_CAT_VAES,
|
|
.IsaSet = ND_SET_VAES,
|
|
.Mnemonic = 902,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VAES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2676 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESDECLAST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 902,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2677 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESENC,
|
|
.Category = ND_CAT_VAES,
|
|
.IsaSet = ND_SET_VAES,
|
|
.Mnemonic = 903,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VAES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2678 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESENC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 903,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2679 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESENCLAST,
|
|
.Category = ND_CAT_VAES,
|
|
.IsaSet = ND_SET_VAES,
|
|
.Mnemonic = 904,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VAES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2680 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VAESENCLAST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 904,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2681 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VAESIMC,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 905,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2682 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VAESKEYGENASSIST,
|
|
.Category = ND_CAT_AES,
|
|
.IsaSet = ND_SET_AES,
|
|
.Mnemonic = 906,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2683 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VALIGND,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 907,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2684 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VALIGNQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 908,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2685 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VANDNPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 909,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2686 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VANDNPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 909,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2687 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VANDNPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 910,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2688 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VANDNPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 910,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2689 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VANDPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 911,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2690 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VANDPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 911,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2691 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VANDPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 912,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2692 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VANDPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 912,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2693 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBCSTNEBF162PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 913,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2694 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBCSTNESH2PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 914,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2695 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VBLENDMPD,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 915,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2696 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VBLENDMPS,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 916,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2697 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VBLENDPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 917,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2698 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VBLENDPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 918,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2699 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VBLENDVPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 919,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2700 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VBLENDVPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 920,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2701 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF128,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 921,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2702 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF32X2,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 922,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2703 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF32X4,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 923,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2704 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF32X8,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 924,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2705 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF64X2,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 925,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2706 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTF64X4,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 926,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2707 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI128,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 927,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2708 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI32X2,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 928,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2709 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI32X4,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 929,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2710 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI32X8,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 930,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2711 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI64X2,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 931,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2712 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTI64X4,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 932,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2713 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTSD,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 933,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2714 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTSD,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 933,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2715 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTSS,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 934,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2716 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VBROADCASTSS,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 934,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2717 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 935,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2718 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 935,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2719 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 936,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2720 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 937,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2721 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 937,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2722 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 938,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2723 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 938,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2724 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 939,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2725 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 940,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2726 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VCMPSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 940,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2727 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCOMISD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 941,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2728 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCOMISD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 941,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2729 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCOMISH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 942,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2730 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCOMISS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 943,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2731 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCOMISS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 943,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2732 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VCOMPRESSPD,
|
|
.Category = ND_CAT_COMPRESS,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 944,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2733 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VCOMPRESSPS,
|
|
.Category = ND_CAT_COMPRESS,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 945,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2734 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 946,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2735 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 946,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2736 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 946,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2737 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 947,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2738 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 948,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2739 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTDQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 948,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2740 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNE2PS2BF16,
|
|
.Category = ND_CAT_AVX512BF16,
|
|
.IsaSet = ND_SET_AVX512BF16,
|
|
.Mnemonic = 949,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BF16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2741 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEEBF162PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 950,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2742 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEEPH2PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 951,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2743 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEOBF162PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 952,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2744 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEOPH2PS,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 953,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2745 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEPS2BF16,
|
|
.Category = ND_CAT_AVX512BF16,
|
|
.IsaSet = ND_SET_AVX512BF16,
|
|
.Mnemonic = 954,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BF16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2746 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTNEPS2BF16,
|
|
.Category = ND_CAT_AVXNECONVERT,
|
|
.IsaSet = ND_SET_AVXNECONVERT,
|
|
.Mnemonic = 954,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVXNECONVERT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2747 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 955,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2748 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 955,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2749 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 956,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2750 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 957,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2751 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 957,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2752 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 957,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2753 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2QQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 958,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2754 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2UDQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 959,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2755 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPD2UQQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 960,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2756 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2DQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 961,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2757 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2PD,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 962,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2758 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 963,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2759 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_F16C,
|
|
.Mnemonic = 963,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_F16C,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2760 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_F16C,
|
|
.Mnemonic = 963,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_F16C,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2761 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2PSX,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 964,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2762 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2QQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 965,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2763 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2UDQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 966,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2764 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2UQQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 967,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2765 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2UW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 968,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2766 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPH2W,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 969,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2767 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 970,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2768 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 970,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2769 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 971,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2770 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 971,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2771 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 971,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2772 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PH,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 972,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2773 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PH,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_F16C,
|
|
.Mnemonic = 972,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_F16C,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2774 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PH,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_F16C,
|
|
.Mnemonic = 972,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_11,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_F16C,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2775 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2PHX,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 973,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2776 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2QQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 974,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2777 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2UDQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 975,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2778 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTPS2UQQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 976,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2779 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTQQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 977,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2780 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTQQ2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 978,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2781 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTQQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 979,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2782 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 980,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2783 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 981,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2784 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 981,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2785 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 982,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2786 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 982,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2787 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSD2USI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 983,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2788 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSH2SD,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 984,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2789 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSH2SI,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 985,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2790 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSH2SS,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 986,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2791 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSH2USI,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 987,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2792 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 988,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2793 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 988,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2794 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 988,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2795 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 989,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2796 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 990,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2797 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSI2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 990,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2798 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 991,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2799 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 991,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2800 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 992,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2801 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 993,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2802 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 993,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2803 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTSS2USI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 994,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2804 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 995,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2805 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPD2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 995,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2806 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPD2QQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 996,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2807 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPD2UDQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 997,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2808 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPD2UQQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 998,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2809 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2DQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 999,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2810 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2QQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1000,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2811 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2UDQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1001,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2812 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2UQQ,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1002,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2813 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2UW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1003,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2814 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPH2W,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1004,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2815 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1005,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2816 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPS2DQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1005,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2817 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPS2QQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1006,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2818 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPS2UDQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1007,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2819 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTPS2UQQ,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1008,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2820 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1009,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2821 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSD2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1009,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2822 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSD2USI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1010,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2823 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSH2SI,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1011,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2824 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSH2USI,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1012,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2825 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1013,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2826 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSS2SI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1013,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2827 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VCVTTSS2USI,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1014,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1F,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2828 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUDQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1015,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HV,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2829 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUDQ2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1016,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2830 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUDQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1017,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2831 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUQQ2PD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1018,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2832 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUQQ2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1019,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2833 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUQQ2PS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1020,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2834 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1021,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2835 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUSI2SD,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1021,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2836 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUSI2SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1022,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2837 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUSI2SS,
|
|
.Category = ND_CAT_CONVERT,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1023,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2838 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTUW2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1024,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2839 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VCVTW2PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1025,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2840 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VDBPSADBW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1026,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2841 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1027,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2842 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1027,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2843 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1028,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2844 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1029,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2845 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1029,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2846 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1030,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2847 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1030,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2848 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1031,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2849 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1032,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2850 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VDIVSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1032,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2851 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VDPBF16PS,
|
|
.Category = ND_CAT_AVX512BF16,
|
|
.IsaSet = ND_SET_AVX512BF16,
|
|
.Mnemonic = 1033,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BF16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2852 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VDPPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1034,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2853 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VDPPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1035,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2854 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
|
|
{
|
|
.Instruction = ND_INS_VERR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 1036,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2855 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
|
|
{
|
|
.Instruction = ND_INS_VERW,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I286PROT,
|
|
.Mnemonic = 1037,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2856 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VEXP2PD,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1038,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2857 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VEXP2PS,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1039,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2858 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VEXPANDPD,
|
|
.Category = ND_CAT_EXPAND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1040,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2859 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VEXPANDPS,
|
|
.Category = ND_CAT_EXPAND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1041,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2860 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTF128,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1042,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2861 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTF32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1043,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2862 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTF32X8,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1044,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2863 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTF64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1045,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2864 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTF64X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1046,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2865 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTI128,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1047,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2866 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTI32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1048,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2867 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTI32X8,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1049,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2868 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTI64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1050,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2869 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTI64X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1051,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2870 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1052,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2871 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1052,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2872 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1052,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2873 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VEXTRACTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1052,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2874 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFCMADDCPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1053,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2875 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFCMADDCSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1054,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2876 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFCMULCPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1055,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2877 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFCMULCSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1056,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2878 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VFIXUPIMMPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1057,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2879 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VFIXUPIMMPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1058,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2880 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VFIXUPIMMSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1059,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2881 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VFIXUPIMMSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1060,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2882 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1061,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2883 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1061,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2884 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1062,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2885 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1063,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2886 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1063,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2887 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1064,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2888 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1064,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2889 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1065,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2890 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1066,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2891 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1066,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2892 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1067,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2893 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1067,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2894 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1068,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2895 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1069,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2896 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1069,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2897 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1070,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2898 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1070,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2899 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1071,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2900 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1072,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2901 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1072,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2902 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1073,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2903 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1073,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2904 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1074,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2905 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1075,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2906 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1075,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2907 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1076,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2908 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1076,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2909 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1077,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2910 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1078,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2911 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADD231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1078,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2912 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDCPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1079,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2913 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDCSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1080,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2914 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1081,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2915 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1081,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2916 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1082,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2917 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1082,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2918 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1083,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2919 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1083,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2920 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1084,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2921 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1084,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2922 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1085,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2923 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1085,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2924 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1086,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2925 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1087,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2926 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1087,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2927 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1088,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2928 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1088,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2929 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1089,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2930 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1090,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2931 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1090,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2932 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1091,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2933 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1091,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2934 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1092,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2935 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1093,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2936 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1093,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2937 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1094,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2938 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1094,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2939 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1095,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2940 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMADDSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1095,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2941 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1096,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2942 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1096,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2943 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1097,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2944 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1098,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2945 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1098,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2946 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1099,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2947 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1099,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2948 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1100,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2949 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2950 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1101,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2951 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2952 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1102,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2953 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1103,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2954 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2955 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1104,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2956 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2957 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1105,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2958 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1106,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2959 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1107,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2960 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1107,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2961 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1108,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2962 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1108,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2963 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1109,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2964 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1110,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2965 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1110,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2966 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1111,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2967 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1111,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2968 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1112,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2969 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1113,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2970 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUB231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1113,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2971 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1114,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2972 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1114,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2973 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1115,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2974 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1116,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2975 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1116,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2976 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1117,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2977 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1117,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2978 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1118,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2979 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1119,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2980 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1119,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2981 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1120,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2982 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1120,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2983 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1121,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2984 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1122,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2985 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADD231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1122,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2986 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADDPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1123,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2987 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADDPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1123,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2988 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADDPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1124,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2989 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBADDPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1124,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2990 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1125,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2991 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1125,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2992 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1126,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2993 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1126,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2994 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1127,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2995 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1127,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2996 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1128,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2997 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFMSUBSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1128,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2998 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMULCPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1129,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:2999 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFMULCSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1130,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10S,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3000 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1131,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3001 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1131,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3002 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1132,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3003 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1133,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3004 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1133,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3005 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1134,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3006 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1134,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3007 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1135,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3008 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1136,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3009 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1136,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3010 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1137,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3011 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1137,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3012 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1138,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3013 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3014 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1139,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3015 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1140,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3016 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1140,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3017 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1141,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3018 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1142,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3019 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1142,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3020 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1143,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3021 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1143,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3022 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADD231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1144,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3023 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
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{
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.Instruction = ND_INS_VFNMADD231PS,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1145,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E2,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
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},
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},
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// Pos:3024 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
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{
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.Instruction = ND_INS_VFNMADD231PS,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_FMA,
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.Mnemonic = 1145,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_2,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3025 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
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{
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.Instruction = ND_INS_VFNMADD231SD,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1146,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
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},
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},
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// Pos:3026 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
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{
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.Instruction = ND_INS_VFNMADD231SD,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_FMA,
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.Mnemonic = 1146,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3027 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM"
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{
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.Instruction = ND_INS_VFNMADD231SH,
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.Category = ND_CAT_AVX512FP16,
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.IsaSet = ND_SET_AVX512FP16,
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.Mnemonic = 1147,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S16,
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.ExcType = ND_EXT_E3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512FP16,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
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},
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},
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// Pos:3028 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
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{
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.Instruction = ND_INS_VFNMADD231SS,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1148,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
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},
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},
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// Pos:3029 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
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{
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.Instruction = ND_INS_VFNMADD231SS,
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.Category = ND_CAT_VFMA,
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.IsaSet = ND_SET_FMA,
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.Mnemonic = 1148,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3030 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
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{
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.Instruction = ND_INS_VFNMADDPD,
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.Category = ND_CAT_FMA4,
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.IsaSet = ND_SET_FMA4,
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.Mnemonic = 1149,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA4,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3031 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
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{
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.Instruction = ND_INS_VFNMADDPD,
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.Category = ND_CAT_FMA4,
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.IsaSet = ND_SET_FMA4,
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.Mnemonic = 1149,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA4,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3032 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
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{
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.Instruction = ND_INS_VFNMADDPS,
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.Category = ND_CAT_FMA4,
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.IsaSet = ND_SET_FMA4,
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.Mnemonic = 1150,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA4,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3033 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
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{
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.Instruction = ND_INS_VFNMADDPS,
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.Category = ND_CAT_FMA4,
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.IsaSet = ND_SET_FMA4,
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.Mnemonic = 1150,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_FMA4,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3034 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
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{
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.Instruction = ND_INS_VFNMADDSD,
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.Category = ND_CAT_FMA4,
|
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.IsaSet = ND_SET_FMA4,
|
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.Mnemonic = 1151,
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.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3035 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADDSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1151,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3036 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFNMADDSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1152,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3037 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMADDSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1152,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3038 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1153,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3039 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1153,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3040 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1154,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3041 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1155,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3042 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1155,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3043 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1156,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3044 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1156,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3045 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1157,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3046 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1158,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3047 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB132SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1158,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3048 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1159,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3049 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1159,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3050 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1160,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3051 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1161,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3052 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1161,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3053 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1162,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3054 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1162,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3055 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1163,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3056 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1164,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3057 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB213SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1164,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3058 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1165,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3059 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231PD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1165,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3060 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231PH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1166,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3061 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1167,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3062 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231PS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1167,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3063 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1168,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3064 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231SD,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1168,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3065 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231SH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1169,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3066 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3067 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUB231SS,
|
|
.Category = ND_CAT_VFMA,
|
|
.IsaSet = ND_SET_FMA,
|
|
.Mnemonic = 1170,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3068 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3069 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBPD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1171,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3070 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3071 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBPS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1172,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3072 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3073 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBSD,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1173,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3074 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3075 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VFNMSUBSS,
|
|
.Category = ND_CAT_FMA4,
|
|
.IsaSet = ND_SET_FMA4,
|
|
.Mnemonic = 1174,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_FMA4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3076 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VFPCLASSPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1175,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3077 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VFPCLASSPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1176,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3078 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VFPCLASSPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1177,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3079 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
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{
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.Instruction = ND_INS_VFPCLASSSD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1178,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E6,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3080 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI"
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{
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.Instruction = ND_INS_VFPCLASSSH,
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.Category = ND_CAT_AVX512FP16,
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.IsaSet = ND_SET_AVX512FP16,
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.Mnemonic = 1179,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S16,
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.ExcType = ND_EXT_E10,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_AVX512FP16,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3081 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
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{
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.Instruction = ND_INS_VFPCLASSSS,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1180,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E6,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3082 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
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{
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.Instruction = ND_INS_VFRCZPD,
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.Category = ND_CAT_XOP,
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.IsaSet = ND_SET_XOP,
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.Mnemonic = 1181,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_XOP,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3083 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
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{
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.Instruction = ND_INS_VFRCZPS,
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.Category = ND_CAT_XOP,
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.IsaSet = ND_SET_XOP,
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.Mnemonic = 1182,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_XOP,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3084 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
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{
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.Instruction = ND_INS_VFRCZSD,
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.Category = ND_CAT_XOP,
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.IsaSet = ND_SET_XOP,
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.Mnemonic = 1183,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_XOP,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3085 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
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{
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.Instruction = ND_INS_VFRCZSS,
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.Category = ND_CAT_XOP,
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.IsaSet = ND_SET_XOP,
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.Mnemonic = 1184,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(2, 0),
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.TupleType = 0,
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.ExcType = 0,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_XOP,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3086 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
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{
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.Instruction = ND_INS_VGATHERDPD,
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.Category = ND_CAT_GATHER,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1185,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E12,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:3087 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
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{
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.Instruction = ND_INS_VGATHERDPD,
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.Category = ND_CAT_AVX2GATHER,
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.IsaSet = ND_SET_AVX2GATHER,
|
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.Mnemonic = 1185,
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
|
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.TupleType = 0,
|
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.ExcType = ND_EXT_12,
|
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.FpuFlags = 0,
|
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.EvexMode = 0,
|
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.TestedFlags = 0,
|
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.ModifiedFlags = 0,
|
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.SetFlags = 0,
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.ClearedFlags = 0,
|
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
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.CpuidFlag = 0,
|
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
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OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
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},
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},
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// Pos:3088 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
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{
|
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.Instruction = ND_INS_VGATHERDPS,
|
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.Category = ND_CAT_GATHER,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
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{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3089 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
|
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{
|
|
.Instruction = ND_INS_VGATHERDPS,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1186,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3090 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF0DPD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1187,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3091 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF0DPS,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1188,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3092 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF0QPD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1189,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3093 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF0QPS,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1190,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3094 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF1DPD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1191,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3095 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF1DPS,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1192,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3096 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF1QPD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1193,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3097 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VGATHERPF1QPS,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1194,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3098 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VGATHERQPD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1195,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3099 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VGATHERQPD,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1195,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3100 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VGATHERQPS,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1196,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3101 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VGATHERQPS,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1196,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3102 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1197,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3103 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1198,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3104 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1199,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3105 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1200,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3106 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1201,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3107 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VGETEXPSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1202,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3108 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VGETMANTPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1203,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3109 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VGETMANTPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1204,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3110 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VGETMANTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1205,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3111 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VGETMANTSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1206,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3112 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VGETMANTSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1207,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3113 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
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{
|
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.Instruction = ND_INS_VGETMANTSS,
|
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.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1208,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
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.OpsCount = ND_OPS_CNT(5, 0),
|
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.TupleType = ND_TUPLE_T1S,
|
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.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
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.EvexMode = 0,
|
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.TestedFlags = 0,
|
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.ModifiedFlags = 0,
|
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.SetFlags = 0,
|
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
|
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3114 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
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{
|
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.Instruction = ND_INS_VGF2P8AFFINEINVQB,
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.Category = ND_CAT_GFNI,
|
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.IsaSet = ND_SET_GFNI,
|
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.Mnemonic = 1209,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
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.OpsCount = ND_OPS_CNT(5, 0),
|
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.TupleType = ND_TUPLE_FV,
|
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.ExcType = ND_EXT_E4NF,
|
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.FpuFlags = 0,
|
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.EvexMode = 0,
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.TestedFlags = 0,
|
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.ModifiedFlags = 0,
|
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.SetFlags = 0,
|
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.ClearedFlags = 0,
|
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_GFNI,
|
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3115 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
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{
|
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.Instruction = ND_INS_VGF2P8AFFINEINVQB,
|
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.Category = ND_CAT_GFNI,
|
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.IsaSet = ND_SET_GFNI,
|
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.Mnemonic = 1209,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
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.OpsCount = ND_OPS_CNT(4, 0),
|
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.TupleType = 0,
|
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_GFNI,
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.Operands =
|
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3116 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
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{
|
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.Instruction = ND_INS_VGF2P8AFFINEQB,
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.Category = ND_CAT_GFNI,
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.IsaSet = ND_SET_GFNI,
|
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.Mnemonic = 1210,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(5, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_GFNI,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3117 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
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{
|
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.Instruction = ND_INS_VGF2P8AFFINEQB,
|
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.Category = ND_CAT_GFNI,
|
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.IsaSet = ND_SET_GFNI,
|
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.Mnemonic = 1210,
|
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_GFNI,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3118 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
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{
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.Instruction = ND_INS_VGF2P8MULB,
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.Category = ND_CAT_GFNI,
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.IsaSet = ND_SET_GFNI,
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.Mnemonic = 1211,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FVM,
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.ExcType = ND_EXT_E4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_GFNI,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3119 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
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{
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.Instruction = ND_INS_VGF2P8MULB,
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.Category = ND_CAT_GFNI,
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.IsaSet = ND_SET_GFNI,
|
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.Mnemonic = 1211,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_GFNI,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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|
},
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},
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// Pos:3120 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
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{
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.Instruction = ND_INS_VHADDPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1212,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
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|
|
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// Pos:3121 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
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{
|
|
.Instruction = ND_INS_VHADDPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1213,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3122 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VHSUBPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1214,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3123 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VHSUBPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1215,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3124 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTF128,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1216,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3125 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTF32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1217,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3126 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTF32X8,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1218,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3127 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTF64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1219,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3128 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTF64X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1220,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3129 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTI128,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1221,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3130 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTI32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1222,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3131 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTI32X8,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1223,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T8,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3132 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTI64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1224,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3133 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTI64X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1225,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T4,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3134 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3135 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3136 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3137 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VINSERTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1226,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3138 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VLDDQU,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1227,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3139 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_VLDMXCSR,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1228,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3140 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMASKMOVDQU,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1229,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3141 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMASKMOVPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1230,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3142 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VMASKMOVPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1230,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3143 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMASKMOVPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1231,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3144 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VMASKMOVPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1231,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3145 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1232,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3146 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1232,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3147 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1233,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3148 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1234,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3149 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1234,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3150 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1235,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3151 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1235,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3152 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1236,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3153 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1237,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3154 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMAXSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1237,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3155 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/""
|
|
{
|
|
.Instruction = ND_INS_VMCALL,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1238,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3156 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_VMCLEAR,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1239,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3157 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
|
|
{
|
|
.Instruction = ND_INS_VMFUNC,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1240,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3158 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
|
|
{
|
|
.Instruction = ND_INS_VMGEXIT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1241,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3159 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
|
|
{
|
|
.Instruction = ND_INS_VMGEXIT,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1241,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3160 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1242,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3161 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMINPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1242,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3162 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1243,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3163 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1244,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3164 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMINPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1244,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3165 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1245,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3166 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMINSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1245,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3167 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1246,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3168 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMINSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1247,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3169 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMINSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1247,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3170 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/""
|
|
{
|
|
.Instruction = ND_INS_VMLAUNCH,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1248,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3171 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
|
|
{
|
|
.Instruction = ND_INS_VMLOAD,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1249,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3172 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/""
|
|
{
|
|
.Instruction = ND_INS_VMMCALL,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1250,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3173 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
|
|
{
|
|
.Instruction = ND_INS_VMMCALL,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1250,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3174 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1251,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3175 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1251,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3176 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1251,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3177 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1251,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3178 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3179 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3180 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3181 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVAPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1252,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3182 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1253,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3183 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1253,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3184 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1253,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3185 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1253,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3186 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_DUP,
|
|
.ExcType = ND_EXT_E5NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3187 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_DUP,
|
|
.ExcType = ND_EXT_E5NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3188 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_DUP,
|
|
.ExcType = ND_EXT_E5NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3189 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3190 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1254,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3191 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3192 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1255,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3193 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA32,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1256,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3194 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA32,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1256,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3195 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA64,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1257,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3196 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQA64,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1257,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3197 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1258,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3198 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1258,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3199 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU16,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3200 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU16,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1259,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3201 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU32,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1260,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3202 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU32,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1260,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3203 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU64,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3204 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU64,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1261,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3205 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU8,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1262,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3206 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVDQU8,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1262,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3207 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1263,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3208 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHLPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1263,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3209 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1264,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3210 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1264,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3211 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1264,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3212 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1264,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3213 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1265,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3214 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1265,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3215 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1265,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3216 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1265,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3217 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLHPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1266,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3218 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLHPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1266,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3219 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3220 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3221 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3222 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1267,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3223 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3224 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T2,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3225 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3226 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVLPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1268,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3227 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVMSKPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1269,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3228 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVMSKPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1270,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3229 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTDQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1271,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3230 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1271,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3231 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTDQA,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1272,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3232 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTDQA,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1272,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3233 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1273,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3234 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1273,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3235 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1274,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E1NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3236 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVNTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1274,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_1,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3237 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3238 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3239 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3240 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3241 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3242 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3243 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3244 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1275,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3245 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3246 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3247 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3248 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3249 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3250 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3251 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3252 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1276,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3253 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3254 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3255 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3256 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1277,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3257 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSHDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1278,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3258 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSHDUP,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1278,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3259 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSLDUP,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3260 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSLDUP,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1279,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3261 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3262 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3263 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3264 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3265 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3266 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3267 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3268 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVSS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1280,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3269 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1281,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3270 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1281,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3271 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1281,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3272 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1281,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3273 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1282,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3274 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1282,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3275 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1282,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3276 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVUPS,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1282,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3277 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1283,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3278 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VMOVW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1283,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3279 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1283,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3280 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMOVW,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1283,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3281 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VMPSADBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1284,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3282 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_VMPTRLD,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1285,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3283 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_VMPTRST,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1286,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3284 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_VMREAD,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1287,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3285 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/""
|
|
{
|
|
.Instruction = ND_INS_VMRESUME,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1288,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3286 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
|
|
{
|
|
.Instruction = ND_INS_VMRUN,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1289,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3287 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
|
|
{
|
|
.Instruction = ND_INS_VMSAVE,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_SVM,
|
|
.Mnemonic = 1290,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_SVM,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3288 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMULPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1291,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3289 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VMULPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1291,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3290 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMULPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1292,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3291 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VMULPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1293,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3292 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
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{
|
|
.Instruction = ND_INS_VMULPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1293,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
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OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3293 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
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{
|
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.Instruction = ND_INS_VMULSD,
|
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.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1294,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
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.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
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},
|
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},
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// Pos:3294 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
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{
|
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.Instruction = ND_INS_VMULSD,
|
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.Category = ND_CAT_AVX,
|
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.IsaSet = ND_SET_AVX,
|
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.Mnemonic = 1294,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
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},
|
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},
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// Pos:3295 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM"
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{
|
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.Instruction = ND_INS_VMULSH,
|
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.Category = ND_CAT_AVX512FP16,
|
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.IsaSet = ND_SET_AVX512FP16,
|
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.Mnemonic = 1295,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
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},
|
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},
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// Pos:3296 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
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{
|
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.Instruction = ND_INS_VMULSS,
|
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.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1296,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
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},
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// Pos:3297 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
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{
|
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.Instruction = ND_INS_VMULSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
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.Mnemonic = 1296,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
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},
|
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},
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// Pos:3298 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
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{
|
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.Instruction = ND_INS_VMWRITE,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1297,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_F64|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
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{
|
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OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
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},
|
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},
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|
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// Pos:3299 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/""
|
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{
|
|
.Instruction = ND_INS_VMXOFF,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1298,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
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// Pos:3300 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
|
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{
|
|
.Instruction = ND_INS_VMXON,
|
|
.Category = ND_CAT_VTX,
|
|
.IsaSet = ND_SET_VTX,
|
|
.Mnemonic = 1299,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_VTX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3301 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1300,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3302 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1300,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3303 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1301,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3304 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1301,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3305 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VP2INTERSECTD,
|
|
.Category = ND_CAT_AVX512VP2INTERSECT,
|
|
.IsaSet = ND_SET_AVX512VP2INTERSECT,
|
|
.Mnemonic = 1302,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VP2INTERSECT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3306 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VP2INTERSECTQ,
|
|
.Category = ND_CAT_AVX512VP2INTERSECT,
|
|
.IsaSet = ND_SET_AVX512VP2INTERSECT,
|
|
.Mnemonic = 1303,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VP2INTERSECT,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3307 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VP4DPWSSD,
|
|
.Category = ND_CAT_VNNIW,
|
|
.IsaSet = ND_SET_AVX5124VNNIW,
|
|
.Mnemonic = 1304,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124VNNIW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3308 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VP4DPWSSDS,
|
|
.Category = ND_CAT_VNNIW,
|
|
.IsaSet = ND_SET_AVX5124VNNIW,
|
|
.Mnemonic = 1305,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1_4X,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX5124VNNIW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
|
|
OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3309 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPABSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1306,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3310 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPABSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1306,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3311 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPABSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1307,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3312 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPABSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1307,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3313 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPABSQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1308,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3314 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPABSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1309,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3315 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPABSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1309,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3316 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKSSDW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1310,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3317 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKSSDW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1310,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3318 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKSSWB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1311,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3319 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKSSWB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1311,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3320 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKUSDW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3321 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKUSDW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1312,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3322 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKUSWB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1313,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3323 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPACKUSWB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1313,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3324 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1314,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3325 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1314,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3326 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3327 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1315,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3328 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1316,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3329 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1316,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3330 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3331 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1317,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3332 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1318,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3333 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1318,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3334 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDUSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1319,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3335 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDUSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1319,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3336 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDUSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1320,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3337 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDUSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1320,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3338 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1321,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3339 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPADDW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1321,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3340 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPALIGNR,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1322,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3341 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPALIGNR,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1322,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3342 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPAND,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1323,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3343 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPANDD,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1324,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3344 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPANDN,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1325,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3345 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPANDND,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1326,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3346 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPANDNQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1327,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3347 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPANDQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1328,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3348 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPAVGB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1329,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3349 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPAVGB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1329,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3350 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPAVGW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1330,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3351 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPAVGW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1330,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3352 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1331,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3353 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDMB,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1332,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3354 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDMD,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1333,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3355 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDMQ,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1334,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3356 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDMW,
|
|
.Category = ND_CAT_BLEND,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1335,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3357 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDVB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1336,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3358 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPBLENDW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1337,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3359 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTB,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1338,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3360 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTB,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1338,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3361 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTB,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1338,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3362 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTD,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1339,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3363 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTD,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1339,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3364 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTD,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1339,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3365 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTMB2Q,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1340,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3366 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTMW2D,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1341,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E6NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3367 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTQ,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1342,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3368 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTQ,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1342,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3369 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTQ,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1342,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3370 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTW,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1343,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3371 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTW,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1343,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3372 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPBROADCASTW,
|
|
.Category = ND_CAT_BROADCAST,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1343,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3373 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCLMULQDQ,
|
|
.Category = ND_CAT_VPCLMULQDQ,
|
|
.IsaSet = ND_SET_VPCLMULQDQ,
|
|
.Mnemonic = 1344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VPCLMULQDQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3374 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCLMULQDQ,
|
|
.Category = ND_CAT_VPCLMULQDQ,
|
|
.IsaSet = ND_SET_VPCLMULQDQ,
|
|
.Mnemonic = 1344,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_VPCLMULQDQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3375 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPCMOV,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3376 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VPCMOV,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1345,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3377 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1346,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3378 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1347,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3379 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1348,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3380 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1348,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3381 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1349,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3382 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1349,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3383 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1350,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3384 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1350,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3385 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1351,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3386 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPEQW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1351,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3387 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPESTRI,
|
|
.Category = ND_CAT_STTNI,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1352,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3388 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPESTRM,
|
|
.Category = ND_CAT_STTNI,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1353,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 4),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3389 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1354,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3390 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1354,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3391 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1355,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3392 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1355,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3393 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1356,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3394 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1356,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3395 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1357,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3396 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPCMPGTW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1357,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3397 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPISTRI,
|
|
.Category = ND_CAT_STTNI,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1358,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3398 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPISTRM,
|
|
.Category = ND_CAT_STTNI,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1359,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 2),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3399 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1360,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3400 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPUB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1361,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3401 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPUD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1362,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3402 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPUQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1363,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3403 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPUW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1364,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3404 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCMPW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1365,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3405 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1366,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3406 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1367,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3407 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPCOMPRESSB,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1368,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3408 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPCOMPRESSD,
|
|
.Category = ND_CAT_COMPRESS,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1369,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3409 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPCOMPRESSQ,
|
|
.Category = ND_CAT_COMPRESS,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1370,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3410 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPCOMPRESSW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1371,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3411 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1372,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3412 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMUB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1373,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3413 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMUD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1374,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3414 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMUQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1375,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3415 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMUW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1376,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3416 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPCOMW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1377,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3417 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPCONFLICTD,
|
|
.Category = ND_CAT_CONFLICT,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1378,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3418 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPCONFLICTQ,
|
|
.Category = ND_CAT_CONFLICT,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1379,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3419 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBSSD,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1380,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3420 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBSSDS,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1381,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3421 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBSUD,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1382,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3422 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBSUDS,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1383,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3423 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUSD,
|
|
.Category = ND_CAT_VNNI,
|
|
.IsaSet = ND_SET_AVX512VNNI,
|
|
.Mnemonic = 1384,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3424 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUSD,
|
|
.Category = ND_CAT_AVXVNNI,
|
|
.IsaSet = ND_SET_AVXVNNI,
|
|
.Mnemonic = 1384,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3425 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUSDS,
|
|
.Category = ND_CAT_VNNI,
|
|
.IsaSet = ND_SET_AVX512VNNI,
|
|
.Mnemonic = 1385,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3426 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUSDS,
|
|
.Category = ND_CAT_AVXVNNI,
|
|
.IsaSet = ND_SET_AVXVNNI,
|
|
.Mnemonic = 1385,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3427 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUUD,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1386,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3428 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPBUUDS,
|
|
.Category = ND_CAT_AVXVNNIINT8,
|
|
.IsaSet = ND_SET_AVXVNNIINT8,
|
|
.Mnemonic = 1387,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT8,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3429 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSSD,
|
|
.Category = ND_CAT_VNNI,
|
|
.IsaSet = ND_SET_AVX512VNNI,
|
|
.Mnemonic = 1388,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3430 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSSD,
|
|
.Category = ND_CAT_AVXVNNI,
|
|
.IsaSet = ND_SET_AVXVNNI,
|
|
.Mnemonic = 1388,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3431 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSSDS,
|
|
.Category = ND_CAT_VNNI,
|
|
.IsaSet = ND_SET_AVX512VNNI,
|
|
.Mnemonic = 1389,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3432 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSSDS,
|
|
.Category = ND_CAT_AVXVNNI,
|
|
.IsaSet = ND_SET_AVXVNNI,
|
|
.Mnemonic = 1389,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3433 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSUD,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1390,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3434 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWSUDS,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1391,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3435 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWUSD,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1392,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3436 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWUSDS,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1393,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3437 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWUUD,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1394,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3438 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPDPWUUDS,
|
|
.Category = ND_CAT_AVXVNNIINT16,
|
|
.IsaSet = ND_SET_AVXVNNIINT16,
|
|
.Mnemonic = 1395,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXVNNIINT16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3439 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPERM2F128,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1396,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3440 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
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{
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.Instruction = ND_INS_VPERM2I128,
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.Category = ND_CAT_AVX2,
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.IsaSet = ND_SET_AVX2,
|
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.Mnemonic = 1397,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
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.OpsCount = ND_OPS_CNT(4, 0),
|
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.TupleType = 0,
|
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.ExcType = ND_EXT_6,
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.FpuFlags = 0,
|
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.EvexMode = 0,
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.TestedFlags = 0,
|
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.ModifiedFlags = 0,
|
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX2,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3441 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMB,
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.Category = ND_CAT_AVX512VBMI,
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.IsaSet = ND_SET_AVX512VBMI,
|
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.Mnemonic = 1398,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FVM,
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.ExcType = ND_EXT_E4NFnb,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512VBMI,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3442 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1399,
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
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},
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},
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// Pos:3443 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
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{
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.Instruction = ND_INS_VPERMD,
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.Category = ND_CAT_AVX2,
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.IsaSet = ND_SET_AVX2,
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.Mnemonic = 1399,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX2,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3444 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMI2B,
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.Category = ND_CAT_AVX512VBMI,
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.IsaSet = ND_SET_AVX512VBMI,
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.Mnemonic = 1400,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FVM,
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.ExcType = ND_EXT_E4NFnb,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512VBMI,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3445 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMI2D,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1401,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
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},
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},
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// Pos:3446 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMI2PD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1402,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
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},
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},
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// Pos:3447 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMI2PS,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1403,
|
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.ValidPrefixes = 0,
|
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
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.OpsCount = ND_OPS_CNT(4, 0),
|
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.TupleType = ND_TUPLE_FV,
|
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.ExcType = ND_EXT_E4NF,
|
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.FpuFlags = 0,
|
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.EvexMode = 0,
|
|
.TestedFlags = 0,
|
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.ModifiedFlags = 0,
|
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.SetFlags = 0,
|
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.ClearedFlags = 0,
|
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX512F,
|
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.Operands =
|
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{
|
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
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},
|
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},
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|
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// Pos:3448 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
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{
|
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.Instruction = ND_INS_VPERMI2Q,
|
|
.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1404,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3449 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
|
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{
|
|
.Instruction = ND_INS_VPERMI2W,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1405,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3450 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL"
|
|
{
|
|
.Instruction = ND_INS_VPERMIL2PD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3451 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML"
|
|
{
|
|
.Instruction = ND_INS_VPERMIL2PD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1406,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3452 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL"
|
|
{
|
|
.Instruction = ND_INS_VPERMIL2PS,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3453 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML"
|
|
{
|
|
.Instruction = ND_INS_VPERMIL2PS,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1407,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3454 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3455 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3456 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3457 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1408,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3458 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1409,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3459 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1409,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3460 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1409,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3461 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPERMILPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1409,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3462 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMPD,
|
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1410,
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.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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|
.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
|
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
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},
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},
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// Pos:3463 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMPD,
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.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1410,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
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},
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},
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// Pos:3464 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
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{
|
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.Instruction = ND_INS_VPERMPD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1410,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3465 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
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{
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.Instruction = ND_INS_VPERMPD,
|
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.Category = ND_CAT_AVX2,
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.IsaSet = ND_SET_AVX2,
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.Mnemonic = 1410,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
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.CpuidFlag = ND_CFF_AVX2,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3466 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMPS,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1411,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
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},
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},
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// Pos:3467 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPERMPS,
|
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1411,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4NF,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
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},
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},
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// Pos:3468 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
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{
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.Instruction = ND_INS_VPERMPS,
|
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.Category = ND_CAT_AVX2,
|
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.IsaSet = ND_SET_AVX2,
|
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.Mnemonic = 1411,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
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.ExcType = ND_EXT_4,
|
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.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
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.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
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{
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OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
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|
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// Pos:3469 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
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{
|
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.Instruction = ND_INS_VPERMQ,
|
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.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512F,
|
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.Mnemonic = 1412,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3470 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
|
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{
|
|
.Instruction = ND_INS_VPERMQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1412,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3471 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPERMQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1412,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3472 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2B,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI,
|
|
.Mnemonic = 1413,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3473 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2D,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1414,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3474 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2PD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1415,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3475 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2PS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1416,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3476 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2Q,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1417,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3477 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMT2W,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1418,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3478 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPERMW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1419,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3479 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPEXPANDB,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1420,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3480 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPEXPANDD,
|
|
.Category = ND_CAT_EXPAND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1421,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3481 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPEXPANDQ,
|
|
.Category = ND_CAT_EXPAND,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1422,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3482 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPEXPANDW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1423,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3483 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1424,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3484 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1424,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3485 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1424,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3486 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1424,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3487 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1425,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3488 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1425,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3489 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1425,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3490 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1425,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3491 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1426,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3492 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1426,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3493 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1426,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3494 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1426,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3495 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3496 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3497 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3498 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3499 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3500 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
|
|
{
|
|
.Instruction = ND_INS_VPEXTRW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1427,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3501 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERDD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1428,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3502 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERDD,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1428,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3503 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERDQ,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1429,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3504 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERDQ,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1429,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3505 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERQD,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1430,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3506 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERQD,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1430,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3507 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERQQ,
|
|
.Category = ND_CAT_GATHER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1431,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3508 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPGATHERQQ,
|
|
.Category = ND_CAT_AVX2GATHER,
|
|
.IsaSet = ND_SET_AVX2GATHER,
|
|
.Mnemonic = 1431,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3509 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDBD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1432,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3510 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDBQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1433,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3511 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDBW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1434,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3512 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1435,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3513 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDDQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1436,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3514 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1437,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3515 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUBD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1438,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3516 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUBQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1439,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3517 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUBW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1440,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3518 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUDQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1441,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3519 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1442,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3520 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDUWQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1443,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3521 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1444,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3522 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1445,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3523 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHADDWQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1446,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3524 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHMINPOSUW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1447,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3525 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBBW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1448,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3526 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1449,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3527 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBDQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1450,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3528 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1451,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3529 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1452,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3530 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPHSUBWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1453,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3531 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1454,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3532 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1454,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S8,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3533 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1454,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3534 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1454,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3535 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1455,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3536 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1455,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3537 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1456,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3538 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1456,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3539 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1457,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3540 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1457,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E9NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3541 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1457,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3542 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VPINSRW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1457,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3543 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPLZCNTD,
|
|
.Category = ND_CAT_CONFLICT,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1458,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3544 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPLZCNTQ,
|
|
.Category = ND_CAT_CONFLICT,
|
|
.IsaSet = ND_SET_AVX512CD,
|
|
.Mnemonic = 1459,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512CD,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3545 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSDD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1460,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3546 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSDQH,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1461,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3547 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSDQL,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1462,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3548 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSSDD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1463,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3549 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSSDQH,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1464,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3550 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSSDQL,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1465,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3551 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSSWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1466,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3552 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSSWW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1467,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3553 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1468,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3554 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMACSWW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1469,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3555 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMADCSSWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1470,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3556 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPMADCSWD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1471,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3557 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADD52HUQ,
|
|
.Category = ND_CAT_IFMA,
|
|
.IsaSet = ND_SET_AVX512IFMA,
|
|
.Mnemonic = 1472,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512IFMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3558 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADD52HUQ,
|
|
.Category = ND_CAT_AVXIFMA,
|
|
.IsaSet = ND_SET_AVXIFMA,
|
|
.Mnemonic = 1472,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXIFMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3559 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADD52LUQ,
|
|
.Category = ND_CAT_IFMA,
|
|
.IsaSet = ND_SET_AVX512IFMA,
|
|
.Mnemonic = 1473,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512IFMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3560 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADD52LUQ,
|
|
.Category = ND_CAT_AVXIFMA,
|
|
.IsaSet = ND_SET_AVXIFMA,
|
|
.Mnemonic = 1473,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVXIFMA,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3561 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADDUBSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1474,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3562 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADDUBSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1474,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3563 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADDWD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1475,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3564 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMADDWD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1475,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3565 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMASKMOVD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3566 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VPMASKMOVD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1476,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3567 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMASKMOVQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1477,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3568 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
|
|
{
|
|
.Instruction = ND_INS_VPMASKMOVQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1477,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3569 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1478,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3570 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1478,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3571 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1479,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3572 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1479,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3573 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1480,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3574 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1481,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3575 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1481,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3576 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1482,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3577 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1482,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3578 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1483,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3579 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1483,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3580 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1484,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3581 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1485,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3582 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMAXUW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1485,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3583 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1486,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3584 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1486,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3585 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1487,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3586 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1487,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3587 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1488,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3588 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1489,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3589 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1489,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3590 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1490,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3591 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1490,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3592 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3593 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1491,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3594 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1492,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3595 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1493,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3596 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMINUW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1493,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3597 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVB2M,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1494,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3598 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVD2M,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1495,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3599 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVDB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1496,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3600 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVDW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1497,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3601 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVM2B,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1498,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3602 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVM2D,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1499,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3603 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVM2Q,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1500,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3604 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVM2W,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1501,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3605 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVMSKB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1502,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3606 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVQ2M,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1503,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3607 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVQB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1504,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_OVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3608 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVQD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1505,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3609 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVQW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1506,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3610 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSDB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1507,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3611 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSDW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1508,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3612 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSQB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1509,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_OVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3613 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSQD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1510,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3614 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSQW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1511,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3615 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSWB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1512,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3616 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1513,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3617 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1513,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3618 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1513,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3619 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1514,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_OVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3620 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1514,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3621 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1514,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3622 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1515,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3623 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1515,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3624 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXBW,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1515,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3625 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXDQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1516,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3626 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1516,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3627 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXDQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1516,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3628 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1517,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3629 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1517,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3630 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1517,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3631 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3632 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3633 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVSXWQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1518,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3634 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSDB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1519,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3635 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSDW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1520,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3636 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSQB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1521,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_OVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3637 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSQD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1522,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3638 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSQW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1523,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3639 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVUSWB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1524,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3640 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVW2M,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1525,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_E7NM,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3641 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPMOVWB,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1526,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3642 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1527,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3643 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1527,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3644 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1527,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3645 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1528,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_OVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3646 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1528,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3647 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1528,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3648 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBW,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1529,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3649 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1529,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3650 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXBW,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1529,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3651 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXDQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1530,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3652 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1530,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3653 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXDQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1530,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3654 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWD,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1531,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_HVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3655 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1531,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3656 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1531,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3657 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWQ,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1532,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_QVM,
|
|
.ExcType = ND_EXT_E5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3658 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1532,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3659 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPMOVZXWQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1532,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3660 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3661 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1533,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3662 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHRSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1534,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3663 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHRSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1534,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3664 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHUW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1535,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3665 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHUW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1535,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3666 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1536,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3667 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULHW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1536,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3668 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1537,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3669 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULLD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1537,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3670 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1538,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3671 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1539,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3672 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1539,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3673 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULTISHIFTQB,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI,
|
|
.Mnemonic = 1540,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3674 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULUDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3675 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPMULUDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1541,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3676 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPOPCNTB,
|
|
.Category = ND_CAT_VPOPCNT,
|
|
.IsaSet = ND_SET_AVX512BITALG,
|
|
.Mnemonic = 1542,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BITALG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3677 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPOPCNTD,
|
|
.Category = ND_CAT_VPOPCNT,
|
|
.IsaSet = ND_SET_AVX512VPOPCNTDQ,
|
|
.Mnemonic = 1543,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VPOPCNTDQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3678 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPOPCNTQ,
|
|
.Category = ND_CAT_VPOPCNT,
|
|
.IsaSet = ND_SET_AVX512VPOPCNTDQ,
|
|
.Mnemonic = 1544,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512VPOPCNTDQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3679 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VPOPCNTW,
|
|
.Category = ND_CAT_VPOPCNT,
|
|
.IsaSet = ND_SET_AVX512BITALG,
|
|
.Mnemonic = 1545,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BITALG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3680 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPOR,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1546,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3681 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPORD,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1547,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3682 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPORQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1548,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3683 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
|
|
{
|
|
.Instruction = ND_INS_VPPERM,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1549,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3684 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
|
|
{
|
|
.Instruction = ND_INS_VPPERM,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1549,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3685 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPROLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1550,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3686 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPROLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1551,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3687 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPROLVD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1552,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3688 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPROLVQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1553,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3689 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPRORD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1554,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3690 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPRORQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1555,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3691 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPRORVD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1556,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3692 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPRORVQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1557,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3693 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPROTB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1558,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3694 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPROTB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1558,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3695 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPROTB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1558,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3696 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPROTD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1559,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3697 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPROTD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1559,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3698 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPROTD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1559,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3699 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPROTQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1560,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3700 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPROTQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1560,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3701 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPROTQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1560,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3702 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPROTW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1561,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3703 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPROTW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1561,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3704 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPROTW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1561,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3705 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSADBW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1562,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3706 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSADBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1562,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3707 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPSCATTERDD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1563,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3708 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPSCATTERDQ,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1564,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3709 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPSCATTERQD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1565,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3710 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VPSCATTERQQ,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1566,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3711 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHAB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1567,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3712 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHAB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1567,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3713 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHAD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1568,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3714 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHAD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1568,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3715 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHAQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1569,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3716 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHAQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1569,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3717 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHAW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1570,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3718 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHAW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1570,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3719 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHLB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1571,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3720 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1571,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3721 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1571,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3722 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLB,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1571,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3723 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHLD,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1572,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3724 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDD,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1573,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3725 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDQ,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1574,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3726 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDVD,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1575,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3727 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDVQ,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1576,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3728 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDVW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1577,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3729 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHLDW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1578,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3730 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHLQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1579,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3731 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHLQ,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1579,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3732 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
|
|
{
|
|
.Instruction = ND_INS_VPSHLW,
|
|
.Category = ND_CAT_XOP,
|
|
.IsaSet = ND_SET_XOP,
|
|
.Mnemonic = 1580,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_XOP,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3733 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDD,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1581,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3734 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDQ,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1582,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3735 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDVD,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1583,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3736 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDVQ,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1584,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3737 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDVW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1585,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3738 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHRDW,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512VBMI2,
|
|
.Mnemonic = 1586,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512VBMI2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3739 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1587,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3740 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1587,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3741 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFBITQMB,
|
|
.Category = ND_CAT_AVX512VBMI,
|
|
.IsaSet = ND_SET_AVX512BITALG,
|
|
.Mnemonic = 1588,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BITALG,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3742 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1589,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3743 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1589,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3744 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFHW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1590,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3745 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFHW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1590,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3746 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1591,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3747 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VPSHUFLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1591,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3748 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSIGNB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1592,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3749 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSIGND,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1593,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3750 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSIGNW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1594,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3751 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3752 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3753 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3754 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1595,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3755 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1596,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3756 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1596,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3757 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1597,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3758 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1597,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3759 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1597,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3760 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1597,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3761 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLVD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1598,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3762 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLVD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1598,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3763 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLVQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1599,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3764 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLVQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1599,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3765 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLVW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1600,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3766 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1601,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3767 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1601,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3768 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSLLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1601,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3769 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSLLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1601,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3770 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRAD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1602,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3771 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1602,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3772 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRAD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1602,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3773 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1602,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3774 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRAQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1603,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3775 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1603,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3776 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAVD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1604,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3777 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAVD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1604,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3778 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAVQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1605,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3779 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAVW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1606,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3780 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRAW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1607,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3781 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1607,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3782 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRAW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1607,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3783 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRAW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1607,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3784 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1608,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3785 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1608,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3786 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1608,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3787 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1608,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3788 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1609,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3789 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1609,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3790 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1610,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3791 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1610,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3792 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1610,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3793 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1610,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3794 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLVD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1611,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3795 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLVD,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1611,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3796 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLVQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1612,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3797 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLVQ,
|
|
.Category = ND_CAT_AVX2,
|
|
.IsaSet = ND_SET_AVX2,
|
|
.Mnemonic = 1612,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3798 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLVW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1613,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3799 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1614,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3800 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1614,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_M128,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3801 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_VPSRLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1614,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_7,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3802 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSRLW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1614,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3803 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1615,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3804 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1615,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3805 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1616,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3806 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1616,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3807 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1617,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3808 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1617,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3809 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1618,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3810 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1618,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3811 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1619,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3812 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1619,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3813 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBUSB,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1620,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3814 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBUSB,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1620,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3815 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBUSW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1621,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3816 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBUSW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1621,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3817 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1622,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3818 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPSUBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1622,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3819 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPTERNLOGD,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1623,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3820 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VPTERNLOGQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1624,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3821 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VPTEST,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1625,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3822 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTMB,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1626,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3823 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTMD,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1627,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3824 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTMQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1628,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3825 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTMW,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1629,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3826 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTNMB,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1630,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3827 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTNMD,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1631,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3828 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTNMQ,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1632,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3829 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPTESTNMW,
|
|
.Category = ND_CAT_LOGICAL,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1633,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4nb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3830 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHBW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1634,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3831 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1634,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3832 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1635,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3833 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1635,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3834 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHQDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1636,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3835 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHQDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1636,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3836 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHWD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1637,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3837 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKHWD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1637,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3838 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLBW,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512BW,
|
|
.Mnemonic = 1638,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FVM,
|
|
.ExcType = ND_EXT_E4NFnb,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512BW,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3839 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLBW,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1638,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3840 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1639,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3841 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1639,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3842 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLQDQ,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1640,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3843 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VPUNPCKLQDQ,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1640,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3844 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
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{
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.Instruction = ND_INS_VPUNPCKLWD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512BW,
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.Mnemonic = 1641,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FVM,
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.ExcType = ND_EXT_E4NFnb,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512BW,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3845 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
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{
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.Instruction = ND_INS_VPUNPCKLWD,
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.Category = ND_CAT_AVX,
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.IsaSet = ND_SET_AVX,
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.Mnemonic = 1641,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3846 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
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{
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.Instruction = ND_INS_VPXOR,
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.Category = ND_CAT_LOGICAL,
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.IsaSet = ND_SET_AVX,
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.Mnemonic = 1642,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = 0,
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.OpsCount = ND_OPS_CNT(3, 0),
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.TupleType = 0,
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.ExcType = ND_EXT_4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
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OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3847 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
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{
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.Instruction = ND_INS_VPXORD,
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.Category = ND_CAT_LOGICAL,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1643,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
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},
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},
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// Pos:3848 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
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{
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.Instruction = ND_INS_VPXORQ,
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.Category = ND_CAT_LOGICAL,
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.IsaSet = ND_SET_AVX512F,
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.Mnemonic = 1644,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(4, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E4,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512F,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
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},
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},
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// Pos:3849 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
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{
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.Instruction = ND_INS_VRANGEPD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1645,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(5, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E2,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3850 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
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{
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.Instruction = ND_INS_VRANGEPS,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1646,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
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.OpsCount = ND_OPS_CNT(5, 0),
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.TupleType = ND_TUPLE_FV,
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.ExcType = ND_EXT_E2,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3851 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
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{
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.Instruction = ND_INS_VRANGESD,
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.Category = ND_CAT_AVX512,
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1647,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
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.OpsCount = ND_OPS_CNT(5, 0),
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.TupleType = ND_TUPLE_T1S,
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.ExcType = ND_EXT_E3,
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.FpuFlags = 0,
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.EvexMode = 0,
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.TestedFlags = 0,
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.ModifiedFlags = 0,
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.SetFlags = 0,
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.ClearedFlags = 0,
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.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
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.CpuidFlag = ND_CFF_AVX512DQ,
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.Operands =
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{
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OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
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OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
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OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
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},
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},
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// Pos:3852 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
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{
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.Instruction = ND_INS_VRANGESS,
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.Category = ND_CAT_AVX512,
|
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.IsaSet = ND_SET_AVX512DQ,
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.Mnemonic = 1648,
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.ValidPrefixes = 0,
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.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
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.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
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.OpsCount = ND_OPS_CNT(5, 0),
|
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.TupleType = ND_TUPLE_T1S,
|
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.ExcType = ND_EXT_E3,
|
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.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
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{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
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OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
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OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3853 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
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{
|
|
.Instruction = ND_INS_VRCP14PD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1649,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3854 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRCP14PS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1650,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3855 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRCP14SD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1651,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3856 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRCP14SS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1652,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3857 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRCP28PD,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1653,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3858 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRCP28PS,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1654,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3859 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRCP28SD,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1655,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3860 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRCP28SS,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1656,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3861 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRCPPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1657,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3862 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VRCPPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1658,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3863 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRCPSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1659,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3864 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VRCPSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1660,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3865 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCEPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1661,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3866 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCEPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1662,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3867 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCEPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1663,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3868 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCESD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1664,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3869 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCESH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1665,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3870 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VREDUCESS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1666,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3871 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALEPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1667,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3872 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALEPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1668,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3873 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALEPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1669,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3874 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALESD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1670,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3875 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALESH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1671,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3876 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VRNDSCALESS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1672,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3877 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VROUNDPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1673,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3878 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
|
|
{
|
|
.Instruction = ND_INS_VROUNDPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1674,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3879 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VROUNDSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1675,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3880 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VROUNDSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1676,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3881 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT14PD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1677,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3882 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT14PS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1678,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3883 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT14SD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1679,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3884 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT14SS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1680,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3885 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT28PD,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1681,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3886 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT28PS,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1682,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3887 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT28SD,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1683,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3888 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRT28SS,
|
|
.Category = ND_CAT_KNL,
|
|
.IsaSet = ND_SET_AVX512ER,
|
|
.Mnemonic = 1684,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512ER,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3889 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRTPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1685,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3890 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1686,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3891 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRTSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1687,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E10,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3892 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VRSQRTSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1688,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3893 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1689,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3894 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1690,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3895 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1691,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3896 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1692,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3897 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1693,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3898 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSCALEFSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1694,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3899 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERDPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1695,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3900 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERDPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1696,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3901 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF0DPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1697,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3902 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF0DPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1698,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3903 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF0QPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1699,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3904 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF0QPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1700,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3905 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF1DPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1701,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3906 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF1DPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1702,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3907 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF1QPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1703,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3908 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERPF1QPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512PF,
|
|
.Mnemonic = 1704,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12NP,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512PF,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3909 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERQPD,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1705,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3910 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
|
|
{
|
|
.Instruction = ND_INS_VSCATTERQPS,
|
|
.Category = ND_CAT_SCATTER,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1706,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E12,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3911 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VSHA512MSG1,
|
|
.Category = ND_CAT_SHA512,
|
|
.IsaSet = ND_SET_SHA512,
|
|
.Mnemonic = 1707,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_SHA512,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3912 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VSHA512MSG2,
|
|
.Category = ND_CAT_SHA512,
|
|
.IsaSet = ND_SET_SHA512,
|
|
.Mnemonic = 1708,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_SHA512,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3913 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSHA512RNDS2,
|
|
.Category = ND_CAT_SHA512,
|
|
.IsaSet = ND_SET_SHA512,
|
|
.Mnemonic = 1709,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SHA512,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3914 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFF32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1710,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3915 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFF64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1711,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3916 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFI32X4,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1712,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3917 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFI64X2,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1713,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3918 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1714,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3919 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1714,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3920 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1715,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(5, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3921 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VSHUFPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1715,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3922 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSM3MSG1,
|
|
.Category = ND_CAT_SM3,
|
|
.IsaSet = ND_SET_SM3,
|
|
.Mnemonic = 1716,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SM3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3923 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSM3MSG2,
|
|
.Category = ND_CAT_SM3,
|
|
.IsaSet = ND_SET_SM3,
|
|
.Mnemonic = 1717,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SM3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3924 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI"
|
|
{
|
|
.Instruction = ND_INS_VSM3RNDS2,
|
|
.Category = ND_CAT_SM3,
|
|
.IsaSet = ND_SET_SM3,
|
|
.Mnemonic = 1718,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SM3,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3925 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSM4KEY4,
|
|
.Category = ND_CAT_SM4,
|
|
.IsaSet = ND_SET_SM4,
|
|
.Mnemonic = 1719,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SM4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3926 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSM4RNDS4,
|
|
.Category = ND_CAT_SM4,
|
|
.IsaSet = ND_SET_SM4,
|
|
.Mnemonic = 1720,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_6,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SM4,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3927 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1721,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3928 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1721,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3929 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1722,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3930 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1723,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3931 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1723,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3932 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1724,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3933 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1724,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3934 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1725,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3935 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3936 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSQRTSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1726,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3937 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_VSTMXCSR,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1727,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_5,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3938 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1728,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3939 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1728,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3940 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBPH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1729,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3941 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1730,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3942 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1730,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3943 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBSD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1731,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3944 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBSD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1731,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3945 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBSH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1732,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3946 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBSS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1733,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3947 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VSUBSS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1733,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_2,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3948 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VTESTPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1734,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3949 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VTESTPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1735,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3950 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VUCOMISD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1736,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3951 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VUCOMISD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1736,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3952 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VUCOMISH,
|
|
.Category = ND_CAT_AVX512FP16,
|
|
.IsaSet = ND_SET_AVX512FP16,
|
|
.Mnemonic = 1737,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S16,
|
|
.ExcType = ND_EXT_E3NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512FP16,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3953 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VUCOMISS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1738,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_SAE,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = ND_TUPLE_T1S,
|
|
.ExcType = ND_EXT_E3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3954 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_VUCOMISS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1738,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_3,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3955 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKHPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1739,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3956 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKHPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1739,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3957 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKHPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3958 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKHPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1740,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3959 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKLPD,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1741,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3960 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKLPD,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1741,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3961 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKLPS,
|
|
.Category = ND_CAT_AVX512,
|
|
.IsaSet = ND_SET_AVX512F,
|
|
.Mnemonic = 1742,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4NF,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3962 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VUNPCKLPS,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1742,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3963 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VXORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1743,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3964 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VXORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1743,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3965 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
|
|
{
|
|
.Instruction = ND_INS_VXORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX512DQ,
|
|
.Mnemonic = 1744,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
|
|
.OpsCount = ND_OPS_CNT(4, 0),
|
|
.TupleType = ND_TUPLE_FV,
|
|
.ExcType = ND_EXT_E4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX512DQ,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
|
|
OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3966 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
|
|
{
|
|
.Instruction = ND_INS_VXORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1744,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3967 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
|
|
{
|
|
.Instruction = ND_INS_VZEROALL,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1745,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_8,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3968 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
|
|
{
|
|
.Instruction = ND_INS_VZEROUPPER,
|
|
.Category = ND_CAT_AVX,
|
|
.IsaSet = ND_SET_AVX,
|
|
.Mnemonic = 1746,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_8,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOV,
|
|
.CpuidFlag = ND_CFF_AVX,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3969 Instruction:"WAIT" Encoding:"0x9B"/""
|
|
{
|
|
.Instruction = ND_INS_WAIT,
|
|
.Category = ND_CAT_X87_ALU,
|
|
.IsaSet = ND_SET_X87,
|
|
.Mnemonic = 1747,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0xff,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3970 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
|
|
{
|
|
.Instruction = ND_INS_WBINVD,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 1748,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3971 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/""
|
|
{
|
|
.Instruction = ND_INS_WBNOINVD,
|
|
.Category = ND_CAT_WBNOINVD,
|
|
.IsaSet = ND_SET_WBNOINVD,
|
|
.Mnemonic = 1749,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = ND_CFF_WBNOINVD,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:3972 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_WRFSBASE,
|
|
.Category = ND_CAT_RDWRFSGS,
|
|
.IsaSet = ND_SET_RDWRFSGS,
|
|
.Mnemonic = 1750,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_RDWRFSGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3973 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M"
|
|
{
|
|
.Instruction = ND_INS_WRGSBASE,
|
|
.Category = ND_CAT_RDWRFSGS,
|
|
.IsaSet = ND_SET_RDWRFSGS,
|
|
.Mnemonic = 1751,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_RDWRFSGS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3974 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
|
|
{
|
|
.Instruction = ND_INS_WRMSR,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_PENTIUMREAL,
|
|
.Mnemonic = 1752,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
|
|
.CpuidFlag = ND_CFF_MSR,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3975 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/""
|
|
{
|
|
.Instruction = ND_INS_WRMSRLIST,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_MSRLIST,
|
|
.Mnemonic = 1753,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 3),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
|
|
.CpuidFlag = ND_CFF_MSRLIST,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3976 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/""
|
|
{
|
|
.Instruction = ND_INS_WRMSRNS,
|
|
.Category = ND_CAT_SYSTEM,
|
|
.IsaSet = ND_SET_WRMSRNS,
|
|
.Mnemonic = 1754,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_WRMSRNS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3977 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
|
|
{
|
|
.Instruction = ND_INS_WRPKRU,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_PKU,
|
|
.Mnemonic = 1755,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_PKU,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3978 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1756,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_WRSS,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3979 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 1756,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3980 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1757,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_WRSS,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3981 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 1757,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3982 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRUSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1758,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_WRUSS,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3983 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRUSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 1758,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3984 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRUSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1759,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_WRUSS,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3985 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
|
{
|
|
.Instruction = ND_INS_WRUSS,
|
|
.Category = ND_CAT_CET,
|
|
.IsaSet = ND_SET_CET_SS,
|
|
.Mnemonic = 1759,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_CET_SS,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3986 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_XABORT,
|
|
.Category = ND_CAT_UNCOND_BR,
|
|
.IsaSet = ND_SET_TSX,
|
|
.Mnemonic = 1760,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RTM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3987 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XADD,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 1761,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3988 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XADD,
|
|
.Category = ND_CAT_SEMAPHORE,
|
|
.IsaSet = ND_SET_I486REAL,
|
|
.Mnemonic = 1761,
|
|
.ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3989 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
|
|
{
|
|
.Instruction = ND_INS_XBEGIN,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_TSX,
|
|
.Mnemonic = 1762,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RTM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3990 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3991 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3992 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3993 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3994 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3995 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3996 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3997 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3998 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:3999 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
|
|
{
|
|
.Instruction = ND_INS_XCHG,
|
|
.Category = ND_CAT_DATAXFER,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1763,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4000 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
|
|
{
|
|
.Instruction = ND_INS_XEND,
|
|
.Category = ND_CAT_COND_BR,
|
|
.IsaSet = ND_SET_TSX,
|
|
.Mnemonic = 1764,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RTM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4001 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
|
|
{
|
|
.Instruction = ND_INS_XGETBV,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1765,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4002 Instruction:"XLATB" Encoding:"0xD7"/""
|
|
{
|
|
.Instruction = ND_INS_XLATB,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1766,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 2),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_pBXAL, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4003 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4004 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4005 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4006 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4007 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4008 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4009 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4010 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4011 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4012 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4013 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4014 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4015 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4016 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4017 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4018 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4019 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4020 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4021 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4022 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4023 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4024 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4025 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4026 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4027 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4028 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4029 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4030 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4031 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4032 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4033 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4034 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4035 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND,
|
|
.OpsCount = ND_OPS_CNT(3, 1),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4036 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4037 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4038 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4039 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4040 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4041 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4042 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4043 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4044 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4045 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4046 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_APX_F,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
|
|
.ValidDecorators = ND_DECO_ND|ND_DECO_NF,
|
|
.OpsCount = ND_OPS_CNT(3, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_APX_EVEX_INT,
|
|
.FpuFlags = 0,
|
|
.EvexMode = ND_EVEXM_LEGACY,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_APX_F,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4047 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4048 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4049 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4050 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4051 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4052 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = 0,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4053 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4054 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4055 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4056 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
|
|
{
|
|
.Instruction = ND_INS_XOR,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_I86,
|
|
.Mnemonic = 1767,
|
|
.ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
|
|
.SetFlags = 0|NDR_RFLAG_AF,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = 0,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4057 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XORPD,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE2,
|
|
.Mnemonic = 1768,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE2,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4058 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
|
|
{
|
|
.Instruction = ND_INS_XORPS,
|
|
.Category = ND_CAT_LOGICAL_FP,
|
|
.IsaSet = ND_SET_SSE,
|
|
.Mnemonic = 1769,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(2, 0),
|
|
.TupleType = 0,
|
|
.ExcType = ND_EXT_4,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
|
|
.CpuidFlag = ND_CFF_SSE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
|
|
OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4059 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
|
|
{
|
|
.Instruction = ND_INS_XRESLDTRK,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_TSXLDTRK,
|
|
.Mnemonic = 1770,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TSXLDTRK,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:4060 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XRSTOR,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1771,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4061 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XRSTOR,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1772,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4062 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XRSTORS,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVES,
|
|
.Mnemonic = 1773,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4063 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XRSTORS,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVES,
|
|
.Mnemonic = 1774,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4064 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVE,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1775,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4065 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVE,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1776,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4066 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVEC,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVEC,
|
|
.Mnemonic = 1777,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVEC,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4067 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVEC,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVEC,
|
|
.Mnemonic = 1778,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVEC,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4068 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVEOPT,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1779,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4069 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVEOPT,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1780,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4070 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVES,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVES,
|
|
.Mnemonic = 1781,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4071 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
|
|
{
|
|
.Instruction = ND_INS_XSAVES,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVES,
|
|
.Mnemonic = 1782,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(1, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVES,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4072 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
|
|
{
|
|
.Instruction = ND_INS_XSETBV,
|
|
.Category = ND_CAT_XSAVE,
|
|
.IsaSet = ND_SET_XSAVE,
|
|
.Mnemonic = 1783,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 4),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_XSAVE,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
|
|
OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
// Pos:4073 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
|
|
{
|
|
.Instruction = ND_INS_XSUSLDTRK,
|
|
.Category = ND_CAT_MISC,
|
|
.IsaSet = ND_SET_TSXLDTRK,
|
|
.Mnemonic = 1784,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 0),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_TSXLDTRK,
|
|
.Operands =
|
|
{
|
|
0
|
|
},
|
|
},
|
|
|
|
// Pos:4074 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
|
|
{
|
|
.Instruction = ND_INS_XTEST,
|
|
.Category = ND_CAT_LOGIC,
|
|
.IsaSet = ND_SET_TSX,
|
|
.Mnemonic = 1785,
|
|
.ValidPrefixes = 0,
|
|
.ValidModes = ND_MOD_ANY,
|
|
.ValidDecorators = 0,
|
|
.OpsCount = ND_OPS_CNT(0, 1),
|
|
.TupleType = 0,
|
|
.ExcType = 0,
|
|
.FpuFlags = 0,
|
|
.EvexMode = 0,
|
|
.TestedFlags = 0,
|
|
.ModifiedFlags = 0|NDR_RFLAG_ZF,
|
|
.SetFlags = 0,
|
|
.ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
|
|
.Attributes = ND_FLAG_MODRM,
|
|
.CpuidFlag = ND_CFF_RTM,
|
|
.Operands =
|
|
{
|
|
OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
|
|
},
|
|
},
|
|
|
|
|
|
};
|
|
|
|
#endif
|