Commit Graph

28 Commits (76d92e73c29eaaf175f2c77465b1c6eacaef6f3c)

Author SHA1 Message Date
Andrei Vlad LUTAS 76d92e73c2 Multiple changes 2 years ago
Andrei Vlad LUTAS c3a6ea1c25 Updated SEAMCALL specs according to Intel® Trust Domain CPU Architectural Extensions 343754-002US May 2021. 2 years ago
Andrei Vlad LUTAS d053de409f Although not stated in the SDM, VMCALL, VMLAUNCH, VMRESUME and VMXOFF refuse any prefix (66, F3, F2). 2 years ago
Andrei Vlad LUTAS f7bf814bbc Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2 years ago
Andrei Vlad LUTAS fccf11915d Added support for Intel FRED and LKGS instructions. 2 years ago
Andrei Vlad LUTAS 1eb1c9d0d2 Fixed https://github.com/bitdefender/bddisasm/issues/38. 2 years ago
Andrei Vlad LUTAS 98ea9e1d9a Fixed https://github.com/bitdefender/bddisasm/issues/34, https://github.com/bitdefender/bddisasm/issues/35, https://github.com/bitdefender/bddisasm/issues/36 and https://github.com/bitdefender/bddisasm/issues/37. 2 years ago
Andrei Vlad LUTAS 58197cc518 Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode. 2 years ago
Andrei Vlad LUTAS bcf9a89d69 Fixed https://github.com/bitdefender/bddisasm/issues/22 and https://github.com/bitdefender/bddisasm/issues/23. 2 years ago
Andrei Vlad LUTAS e26971b4f0 Added missing Default 64 flag for the ENTER instruction. 2 years ago
Andrei Vlad LUTAS 7a0fa449bc Disassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register). 2 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020). 2 years ago
Andrei Vlad LUTAS 4f8b030ddd Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html. 2 years ago
Andrei Vlad LUTAS 33078e4670 Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2 years ago
Andrei Vlad LUTAS d61a6fa5dd * INC/DEC do not modify the CF. 3 years ago
Andrei Vlad LUTAS ed564dba32 Specifically flag multi-byte NOP operands as not-accessed. 3 years ago
Andrei Vlad LUTAS 144baa5140 Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES. 3 years ago
Ionel-Cristinel ANICHITEI b0b7a67c8e Add braces around the ND_INSTRUCTION.Operands initializer 3 years ago
Ionel-Cristinel ANICHITEI 11f1f548ff Regenerate autogenerated files 3 years ago
Ionel-Cristinel ANICHITEI 049ecc0ab7 Don't use reserved identifiers for include guards 3 years ago
Andrei Vlad LUTAS d622f56211 Added SERIAL flag to the SERIALIZE instruction. 3 years ago
Andrei Vlad LUTAS 4b2f2aee66 Added dedicated Prefetch operand access type. 3 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended. 3 years ago
Andrei Vlad LUTAS 94d7894fa5 Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions. 3 years ago
Andrei Vlad LUTAS 8392c97f97 Use the documented byte granularity for cache-line accesses. 3 years ago
Andrei Vlad LUTAS 9ff2543660 Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions. 3 years ago
Andrei Vlad LUTAS 811c3d0f7c Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them. 3 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit. 3 years ago