diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c
index d8ea637..3099ef6 100644
--- a/bddisasm/bddisasm.c
+++ b/bddisasm/bddisasm.c
@@ -13,7 +13,7 @@
 #endif
 
 
-static const uint16_t gOperandMap[] =
+static const ND_UINT16 gOperandMap[] =
 {
     ND_OPE_D,       // ND_OPT_A
     ND_OPE_V,       // ND_OPT_B
@@ -131,7 +131,7 @@ static const uint16_t gOperandMap[] =
 };
 
 
-static const uint8_t gDispsizemap16[4][8] =
+static const ND_UINT8 gDispsizemap16[4][8] =
 {
     { 0, 0, 0, 0, 0, 0, 2, 0 },
     { 1, 1, 1, 1, 1, 1, 1, 1 },
@@ -139,7 +139,7 @@ static const uint8_t gDispsizemap16[4][8] =
     { 0, 0, 0, 0, 0, 0, 0, 0 },
 };
 
-static const uint8_t gDispsizemap[4][8] =
+static const ND_UINT8 gDispsizemap[4][8] =
 {
     { 0, 0, 0, 0, 0, 4, 0, 0 },
     { 1, 1, 1, 1, 1, 1, 1, 1 },
@@ -153,24 +153,24 @@ static const uint8_t gDispsizemap[4][8] =
 //
 void
 NdGetVersion(
-    uint32_t *Major,
-    uint32_t *Minor,
-    uint32_t *Revision,
+    ND_UINT32 *Major,
+    ND_UINT32 *Minor,
+    ND_UINT32 *Revision,
     char **BuildDate,
     char **BuildTime
     )
 {
-    if (NULL != Major)
+    if (ND_NULL != Major)
     {
         *Major = DISASM_VERSION_MAJOR;
     }
 
-    if (NULL != Minor)
+    if (ND_NULL != Minor)
     {
         *Minor = DISASM_VERSION_MINOR;
     }
 
-    if (NULL != Revision)
+    if (ND_NULL != Revision)
     {
         *Revision = DISASM_VERSION_REVISION;
     }
@@ -180,24 +180,24 @@ NdGetVersion(
 //
 #if defined(__KERNEL__)
 
-    if (NULL != BuildDate)
+    if (ND_NULL != BuildDate)
     {
-        *BuildDate = NULL;
+        *BuildDate = ND_NULL;
     }
 
-    if (NULL != BuildTime)
+    if (ND_NULL != BuildTime)
     {
-        *BuildTime = NULL;
+        *BuildTime = ND_NULL;
     }
 
 #else
 
-    if (NULL != BuildDate)
+    if (ND_NULL != BuildDate)
     {
         *BuildDate = __DATE__;
     }
 
-    if (NULL != BuildTime)
+    if (ND_NULL != BuildTime)
     {
         *BuildTime = __TIME__;
     }
@@ -211,10 +211,10 @@ NdGetVersion(
 //
 // NdFetchData
 //
-static uint64_t
+static ND_UINT64
 NdFetchData(
-    const uint8_t *Buffer,
-    uint8_t Size
+    const ND_UINT8 *Buffer,
+    ND_UINT8 Size
     )
 {
     return (4 == Size) ? ND_FETCH_32(Buffer) :
@@ -231,19 +231,19 @@ NdFetchData(
 static NDSTATUS
 NdFetchXop(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // Offset points to the 0x8F XOP prefix.
     // One more byte has to follow, the modrm or the second XOP byte.
-    RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     if (((Code[Offset + 1] & 0x1F) >= 8))
     {
         // XOP found, make sure the third byte is here.
-        RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
+        RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
         // Make sure we don't have any other prefix.
         if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex)
@@ -252,7 +252,7 @@ NdFetchXop(
         }
 
         // Fill in XOP info.
-        Instrux->HasXop = true;
+        Instrux->HasXop = ND_TRUE;
         Instrux->EncMode = ND_ENCM_XOP;
         Instrux->Xop.Xop[0] = Code[Offset];
         Instrux->Xop.Xop[1] = Code[Offset + 1];
@@ -304,13 +304,13 @@ NdFetchXop(
 static NDSTATUS
 NdFetchVex2(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // One more byte has to follow, the modrm or the second VEX byte.
-    RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // VEX is available only in 32 & 64 bit mode.
     if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0))
@@ -324,7 +324,7 @@ NdFetchVex2(
 
         // Fill in VEX2 info.
         Instrux->VexMode = ND_VEXM_2B;
-        Instrux->HasVex = true;
+        Instrux->HasVex = ND_TRUE;
         Instrux->EncMode = ND_ENCM_VEX;
         Instrux->Vex2.Vex[0] = Code[Offset];
         Instrux->Vex2.Vex[1] = Code[Offset + 1];
@@ -353,19 +353,19 @@ NdFetchVex2(
 static NDSTATUS
 NdFetchVex3(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // One more byte has to follow, the modrm or the second VEX byte.
-    RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // VEX is available only in 32 & 64 bit mode.
     if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0))
     {
         // VEX found, make sure the third byte is here.
-        RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
+        RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
         // Make sure we don't have any other prefix.
         if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd ||
@@ -376,7 +376,7 @@ NdFetchVex3(
 
         // Fill in XOP info.
         Instrux->VexMode = ND_VEXM_3B;
-        Instrux->HasVex = true;
+        Instrux->HasVex = ND_TRUE;
         Instrux->EncMode = ND_ENCM_VEX;
         Instrux->Vex3.Vex[0] = Code[Offset];
         Instrux->Vex3.Vex[1] = Code[Offset + 1];
@@ -421,13 +421,13 @@ NdFetchVex3(
 static NDSTATUS
 NdFetchEvex(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // One more byte has to follow, the modrm or the second VEX byte.
-    RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     if ((ND_CODE_64 != Instrux->DefCode) && ((Code[Offset + 1] & 0xC0) != 0xC0))
     {
@@ -436,10 +436,10 @@ NdFetchEvex(
     }
 
     // EVEX found, make sure all the bytes are present. At least 4 bytes in total must be present.
-    RET_GT((size_t)Offset + 4, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 4, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // This is EVEX.
-    Instrux->HasEvex = true;
+    Instrux->HasEvex = ND_TRUE;
     Instrux->EncMode = ND_ENCM_EVEX;
     Instrux->Evex.Evex[0] = Code[Offset + 0];
     Instrux->Evex.Evex[1] = Code[Offset + 1];
@@ -514,22 +514,22 @@ NdFetchEvex(
 static NDSTATUS
 NdFetchPrefixes(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     NDSTATUS status;
-    bool morePrefixes;
-    uint8_t prefix;
+    ND_BOOL morePrefixes;
+    ND_UINT8 prefix;
 
-    morePrefixes = true;
+    morePrefixes = ND_TRUE;
 
     while (morePrefixes)
     {
-        morePrefixes = false;
+        morePrefixes = ND_FALSE;
 
-        RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+        RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
         prefix = Code[Offset];
 
@@ -545,18 +545,18 @@ NdFetchPrefixes(
             switch (prefix)
             {
             case ND_PREFIX_G0_LOCK:
-                Instrux->HasLock = true;
-                morePrefixes = true;
+                Instrux->HasLock = ND_TRUE;
+                morePrefixes = ND_TRUE;
                 break;
             case ND_PREFIX_G1_REPE_REPZ:
                 Instrux->Rep = ND_PREFIX_G1_REPE_REPZ;
-                Instrux->HasRepRepzXrelease = true;
-                morePrefixes = true;
+                Instrux->HasRepRepzXrelease = ND_TRUE;
+                morePrefixes = ND_TRUE;
                 break;
             case ND_PREFIX_G1_REPNE_REPNZ:
                 Instrux->Rep = ND_PREFIX_G1_REPNE_REPNZ;
-                Instrux->HasRepnzXacquireBnd = true;
-                morePrefixes = true;
+                Instrux->HasRepnzXacquireBnd = ND_TRUE;
+                morePrefixes = ND_TRUE;
                 break;
             case ND_PREFIX_G2_SEG_CS:
             case ND_PREFIX_G2_SEG_SS:
@@ -571,7 +571,7 @@ NdFetchPrefixes(
                     {
                         // The last FS/GS is always used, if present.
                         Instrux->Seg = prefix;
-                        Instrux->HasSeg = true;
+                        Instrux->HasSeg = ND_TRUE;
                     }
                     else if (prefix == ND_PREFIX_G2_NO_TRACK && 
                         Instrux->Seg != ND_PREFIX_G2_SEG_FS &&
@@ -579,7 +579,7 @@ NdFetchPrefixes(
                     {
                         // The Do Not Track prefix is considered only if there isn't a FS/GS prefix.
                         Instrux->Seg = prefix;
-                        Instrux->HasSeg = true;
+                        Instrux->HasSeg = ND_TRUE;
                     }
                     else if (Instrux->Seg != ND_PREFIX_G2_SEG_FS && 
                         Instrux->Seg != ND_PREFIX_G2_SEG_GS &&
@@ -587,23 +587,23 @@ NdFetchPrefixes(
                     {
                         // All other prefixes are considered if Do Not Track, FS, GS are not present.
                         Instrux->Seg = prefix;
-                        Instrux->HasSeg = true;
+                        Instrux->HasSeg = ND_TRUE;
                     }
                 }
                 else
                 {
                     Instrux->Seg = prefix;
-                    Instrux->HasSeg = true;
+                    Instrux->HasSeg = ND_TRUE;
                 }
-                morePrefixes = true;
+                morePrefixes = ND_TRUE;
                 break;
             case ND_PREFIX_G3_OPERAND_SIZE:
-                Instrux->HasOpSize = true;
-                morePrefixes = true;
+                Instrux->HasOpSize = ND_TRUE;
+                morePrefixes = ND_TRUE;
                 break;
             case ND_PREFIX_G4_ADDR_SIZE:
-                Instrux->HasAddrSize = true;
-                morePrefixes = true;
+                Instrux->HasAddrSize = ND_TRUE;
+                morePrefixes = ND_TRUE;
                 break;
             default:
                 break;
@@ -614,7 +614,7 @@ NdFetchPrefixes(
         // will still decode & execute properly, but REX will be ignored.
         if (morePrefixes && Instrux->HasRex)
         {
-            Instrux->HasRex = false;
+            Instrux->HasRex = ND_FALSE;
             Instrux->Rex.Rex = 0;
             Instrux->Exs.w = 0;
             Instrux->Exs.r = 0;
@@ -625,13 +625,13 @@ NdFetchPrefixes(
         // Check for REX.
         if ((ND_CODE_64 == Instrux->DefCode) && (ND_PREF_CODE_REX == gPrefixesMap[prefix]))
         {
-            Instrux->HasRex = true;
+            Instrux->HasRex = ND_TRUE;
             Instrux->Rex.Rex = prefix;
             Instrux->Exs.w = Instrux->Rex.w;
             Instrux->Exs.r = Instrux->Rex.r;
             Instrux->Exs.x = Instrux->Rex.x;
             Instrux->Exs.b = Instrux->Rex.b;
-            morePrefixes = true;
+            morePrefixes = ND_TRUE;
         }
 
         // We have found prefixes, update the instruction length and the current offset.
@@ -647,7 +647,7 @@ NdFetchPrefixes(
 
     // We must have at least one more free byte after the prefixes, which will be either the opcode, either
     // XOP/VEX/EVEX/MVEX prefix.
-    RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // Try to match a XOP/VEX/EVEX/MVEX prefix.
     if (ND_PREF_CODE_EX == gPrefixesMap[Code[Offset]])
@@ -709,13 +709,13 @@ done_prefixes:
 static NDSTATUS
 NdFetchOpcode(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // At least one byte must be available, for the fetched opcode.
-    RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     Instrux->OpCodeBytes[Instrux->OpLength++] = Code[Offset];
 
@@ -735,16 +735,16 @@ NdFetchOpcode(
 static NDSTATUS
 NdFetchModrm(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // At least one byte must be available, for the modrm byte.
-    RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // If we get called, we assume we have ModRM.
-    Instrux->HasModRm = true;
+    Instrux->HasModRm = ND_TRUE;
 
     // Fetch the ModRM byte & update the offset and the instruction length.
     Instrux->ModRm.ModRm = Code[Offset];
@@ -768,16 +768,16 @@ NdFetchModrm(
 static NDSTATUS
 NdFetchModrmAndSib(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 {
     // At least one byte must be available, for the modrm byte.
-    RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     // If we get called, we assume we have ModRM.
-    Instrux->HasModRm = true;
+    Instrux->HasModRm = ND_TRUE;
 
     // Fetch the ModRM byte & update the offset and the instruction length.
     Instrux->ModRm.ModRm = Code[Offset];
@@ -795,10 +795,10 @@ NdFetchModrmAndSib(
     if ((Instrux->ModRm.rm == NDR_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16))
     {
         // At least one more byte must be available, for the sib.
-        RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+        RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
         // SIB present.
-        Instrux->HasSib = true;
+        Instrux->HasSib = ND_TRUE;
 
         Instrux->Sib.Sib = Code[Offset];
         Instrux->Length++;
@@ -820,16 +820,16 @@ NdFetchModrmAndSib(
 static NDSTATUS
 NdFetchDisplacement(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size
     )
 //
 // Will decode the displacement from the instruction. Will fill in extracted information in Instrux,
 // and will update the instruction length.
 //
 {
-    uint8_t displSize;
+    ND_UINT8 displSize;
 
     displSize = 0;
 
@@ -844,16 +844,16 @@ NdFetchDisplacement(
 
     if (0 != displSize)
     {
-        static const uint32_t signMask[4] = { 0x80, 0x8000, 0, 0x80000000 };
+        static const ND_UINT32 signMask[4] = { 0x80, 0x8000, 0, 0x80000000 };
 
         // Make sure enough buffer space is available.
-        RET_GT((size_t)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+        RET_GT((ND_SIZET)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
         // If we get here, we have displacement.
-        Instrux->HasDisp = true;
+        Instrux->HasDisp = ND_TRUE;
 
-        Instrux->Displacement = (uint32_t)NdFetchData(Code + Offset, displSize);
-        Instrux->SignDisp = (Instrux->Displacement & signMask[displSize - 1]) ? true : false;
+        Instrux->Displacement = (ND_UINT32)NdFetchData(Code + Offset, displSize);
+        Instrux->SignDisp = (Instrux->Displacement & signMask[displSize - 1]) ? ND_TRUE : ND_FALSE;
 
         // Fill in displacement info.
         Instrux->DispLength = displSize;
@@ -875,21 +875,21 @@ NdFetchDisplacement(
 static NDSTATUS
 NdFetchAddress(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint8_t AddressSize
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT8 AddressSize
     )
 {
     //. Make sure the
-    RET_GT((size_t)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
-    Instrux->HasAddr = true;
+    Instrux->HasAddr = ND_TRUE;
     Instrux->AddrLength = AddressSize;
     Instrux->AddrOffset = Offset;
 
-    Instrux->Address.Ip = (uint32_t)NdFetchData(Code + Offset, Instrux->AddrLength - 2);
-    Instrux->Address.Cs = (uint16_t)NdFetchData(Code + Offset + Instrux->AddrLength - 2, 2);
+    Instrux->Address.Ip = (ND_UINT32)NdFetchData(Code + Offset, Instrux->AddrLength - 2);
+    Instrux->Address.Cs = (ND_UINT16)NdFetchData(Code + Offset + Instrux->AddrLength - 2, 2);
 
     Instrux->Length += Instrux->AddrLength;
     if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
@@ -907,35 +907,35 @@ NdFetchAddress(
 static NDSTATUS
 NdFetchImmediate(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint8_t ImmediateSize
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT8 ImmediateSize
     )
 {
-    uint64_t imm;
+    ND_UINT64 imm;
 
-    RET_GT((size_t)Offset + ImmediateSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + ImmediateSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
     imm = NdFetchData(Code + Offset, ImmediateSize);
 
     if (Instrux->HasImm2)
     {
-        Instrux->HasImm3 = true;
+        Instrux->HasImm3 = ND_TRUE;
         Instrux->Imm3Length = ImmediateSize;
         Instrux->Imm3Offset = Offset;
-        Instrux->Immediate3 = (uint8_t)imm;
+        Instrux->Immediate3 = (ND_UINT8)imm;
     }
     else if (Instrux->HasImm1)
     {
-        Instrux->HasImm2 = true;
+        Instrux->HasImm2 = ND_TRUE;
         Instrux->Imm2Length = ImmediateSize;
         Instrux->Imm2Offset = Offset;
-        Instrux->Immediate2 = (uint8_t)imm;
+        Instrux->Immediate2 = (ND_UINT8)imm;
     }
     else
     {
-        Instrux->HasImm1 = true;
+        Instrux->HasImm1 = ND_TRUE;
         Instrux->Imm1Length = ImmediateSize;
         Instrux->Imm1Offset = Offset;
         Instrux->Immediate1 = imm;
@@ -957,20 +957,20 @@ NdFetchImmediate(
 static NDSTATUS
 NdFetchRelativeOffset(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint8_t RelOffsetSize
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT8 RelOffsetSize
     )
 {
     // Make sure we don't outrun the buffer.
-    RET_GT((size_t)Offset + RelOffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + RelOffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
-    Instrux->HasRelOffs = true;
+    Instrux->HasRelOffs = ND_TRUE;
     Instrux->RelOffsLength = RelOffsetSize;
     Instrux->RelOffsOffset = Offset;
 
-    Instrux->RelativeOffset = (uint32_t)NdFetchData(Code + Offset, RelOffsetSize);
+    Instrux->RelativeOffset = (ND_UINT32)NdFetchData(Code + Offset, RelOffsetSize);
 
     Instrux->Length += RelOffsetSize;
     if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
@@ -988,15 +988,15 @@ NdFetchRelativeOffset(
 static NDSTATUS
 NdFetchMoffset(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint8_t MoffsetSize
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT8 MoffsetSize
     )
 {
-    RET_GT((size_t)Offset + MoffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + MoffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
-    Instrux->HasMoffset = true;
+    Instrux->HasMoffset = ND_TRUE;
     Instrux->MoffsetLength = MoffsetSize;
     Instrux->MoffsetOffset = Offset;
 
@@ -1018,15 +1018,15 @@ NdFetchMoffset(
 static NDSTATUS
 NdFetchSseImmediate(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint8_t SseImmSize
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT8 SseImmSize
     )
 {
-    RET_GT((size_t)Offset + SseImmSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+    RET_GT((ND_SIZET)Offset + SseImmSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
 
-    Instrux->HasSseImm = true;
+    Instrux->HasSseImm = ND_TRUE;
     Instrux->SseImmOffset = Offset;
     Instrux->SseImmediate = *(Code + Offset);
 
@@ -1043,10 +1043,10 @@ NdFetchSseImmediate(
 //
 // NdGetSegOverride
 //
-static uint8_t
+static ND_UINT8
 NdGetSegOverride(
     INSTRUX *Instrux,
-    uint8_t DefaultSeg
+    ND_UINT8 DefaultSeg
     )
 {
     // In 64 bit mode, the segment override is ignored, except for FS and GS.
@@ -1080,20 +1080,20 @@ NdGetSegOverride(
 //
 // NdGetCompDispSize
 //
-static uint8_t
+static ND_UINT8
 NdGetCompDispSize(
     const INSTRUX *Instrux,
-    uint32_t MemSize
+    ND_UINT32 MemSize
     )
 {
-    static const uint8_t fvszLut[4] = { 16, 32, 64, 0 };
-    static const uint8_t hvszLut[4] = { 8, 16, 32, 0 };
-    static const uint8_t qvszLut[4] = { 4, 8, 16, 0 };
-    static const uint8_t dupszLut[4] = { 8, 32, 64, 0 };
-    static const uint8_t fvmszLut[4] = { 16, 32, 64, 0 };
-    static const uint8_t hvmszLut[4] = { 8, 16, 32, 0 };
-    static const uint8_t qvmszLut[4] = { 4, 8, 16, 0 };
-    static const uint8_t ovmszLut[4] = { 2, 4, 8, 0 };
+    static const ND_UINT8 fvszLut[4] = { 16, 32, 64, 0 };
+    static const ND_UINT8 hvszLut[4] = { 8, 16, 32, 0 };
+    static const ND_UINT8 qvszLut[4] = { 4, 8, 16, 0 };
+    static const ND_UINT8 dupszLut[4] = { 8, 32, 64, 0 };
+    static const ND_UINT8 fvmszLut[4] = { 16, 32, 64, 0 };
+    static const ND_UINT8 hvmszLut[4] = { 8, 16, 32, 0 };
+    static const ND_UINT8 qvmszLut[4] = { 4, 8, 16, 0 };
+    static const ND_UINT8 ovmszLut[4] = { 2, 4, 8, 0 };
 
     if (Instrux->HasBroadcast)
     {
@@ -1101,7 +1101,7 @@ NdGetCompDispSize(
         // - 2 when broadcasting 16 bit
         // - 4 when broadcasting 32 bit
         // - 8 when broadcasting 64 bit
-        return (uint8_t)MemSize;
+        return (ND_UINT8)MemSize;
     }
 
     switch (Instrux->TupleType)
@@ -1131,7 +1131,7 @@ NdGetCompDispSize(
     case ND_TUPLE_T1S:
         return !!(Instrux->Attributes & ND_FLAG_WIG) ? 4 : Instrux->Exs.w ? 8 : 4;
     case ND_TUPLE_T1F:
-        return (uint8_t)MemSize;
+        return (ND_UINT8)MemSize;
     case ND_TUPLE_T2:
         return Instrux->Exs.w ? 16 : 8;
     case ND_TUPLE_T4:
@@ -1153,20 +1153,20 @@ NdGetCompDispSize(
 static NDSTATUS
 NdParseOperand(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
-    uint32_t Index,
-    uint64_t Specifier
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
+    ND_UINT32 Index,
+    ND_UINT64 Specifier
     )
 {
     NDSTATUS status;
     PND_OPERAND operand;
-    uint8_t opt, ops, opf, opa, opd, opb;
+    ND_UINT8 opt, ops, opf, opa, opd, opb;
     ND_REG_SIZE vsibRegSize;
-    uint8_t vsibIndexSize, vsibIndexCount;
+    ND_UINT8 vsibIndexSize, vsibIndexCount;
     ND_OPERAND_SIZE size, bcstSize;
-    bool width;
+    ND_BOOL width;
 
     // pre-init
     status = ND_STATUS_SUCCESS;
@@ -1298,7 +1298,7 @@ NdParseOperand(
     case ND_OPS_v:
         // Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
             size = szLut[Instrux->EfOpMode];
         }
@@ -1307,16 +1307,16 @@ NdParseOperand(
     case ND_OPS_y:
         // Doubleword or quadword (in 64-bit mode), depending on operand-size attribute.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
             size = szLut[Instrux->EfOpMode];
         }
         break;
 
     case ND_OPS_yf:
-        // Always uint64_t in 64 bit mode and uint32_t in 16/32 bit mode.
+        // Always ND_UINT64 in 64 bit mode and ND_UINT32 in 16/32 bit mode.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
             size = szLut[Instrux->DefCode];
         }
@@ -1325,7 +1325,7 @@ NdParseOperand(
     case ND_OPS_z:
         // Word for 16-bit operand-size or double word for 32 or 64-bit operand-size.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_32BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_32BIT };
 
             size = szLut[Instrux->EfOpMode];
         }
@@ -1335,7 +1335,7 @@ NdParseOperand(
         // Two one-word operands in memory or two double-word operands in memory,
         // depending on operand-size attribute (used only by the BOUND instruction).
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT * 2, ND_SIZE_32BIT * 2, 0 };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT * 2, ND_SIZE_32BIT * 2, 0 };
 
             if (Instrux->DefCode > ND_CODE_32)
             {
@@ -1367,7 +1367,7 @@ NdParseOperand(
     case ND_OPS_p:
         // 32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
 
             size = szLut[Instrux->EfOpMode];
         }
@@ -1376,7 +1376,7 @@ NdParseOperand(
     case ND_OPS_s:
         // 6-byte or 10-byte pseudo-descriptor.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_48BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_48BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
 
             size = szLut[Instrux->DefCode];
         }
@@ -1385,7 +1385,7 @@ NdParseOperand(
     case ND_OPS_l:
         // 64 bit in 16 or 32 bit mode, 128 bit in long mode. Used by BNDMOV instruction.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_64BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
 
             size = szLut[Instrux->DefCode];
         }
@@ -1394,7 +1394,7 @@ NdParseOperand(
     case ND_OPS_x:
         // dq, qq or oq based on the operand-size attribute.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1403,7 +1403,7 @@ NdParseOperand(
     case ND_OPS_n:
         // 128, 256 or 512 bit, depending on vector length.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1412,7 +1412,7 @@ NdParseOperand(
     case ND_OPS_u:
         // 256 or 512 bit, depending on vector length.
         {
-            static const uint8_t szLut[3] = { 0, ND_SIZE_256BIT, ND_SIZE_512BIT };
+            static const ND_UINT8 szLut[3] = { 0, ND_SIZE_256BIT, ND_SIZE_512BIT };
 
             if (ND_VECM_128 == Instrux->EfVecMode)
             {
@@ -1426,7 +1426,7 @@ NdParseOperand(
     case ND_OPS_e:
         // eighth = word or dword or qword
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1435,7 +1435,7 @@ NdParseOperand(
     case ND_OPS_f:
         // fourth = dword or qword or oword
         {
-            static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1444,7 +1444,7 @@ NdParseOperand(
     case ND_OPS_h:
         // half = qword or oword or yword
         {
-            static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_128BIT, ND_SIZE_256BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_64BIT, ND_SIZE_128BIT, ND_SIZE_256BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1455,7 +1455,7 @@ NdParseOperand(
     case ND_OPS_ph:
         // packed double or packed single or packed FP16 values.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
 
             size = szLut[Instrux->EfVecMode];
         }
@@ -1552,8 +1552,8 @@ NdParseOperand(
     case ND_OPS_v8:
         // Multiple words accessed.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
-            uint8_t scale = 1;
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            ND_UINT8 scale = 1;
 
             scale = (ops == ND_OPS_v2) ? 2 : 
                     (ops == ND_OPS_v3) ? 3 : 
@@ -1630,7 +1630,7 @@ NdParseOperand(
         operand->Info.Register.Type = ND_REG_GPR;
         operand->Info.Register.Size = ND_SIZE_8BIT;
         operand->Info.Register.Reg = NDR_AH;
-        operand->Info.Register.IsHigh8 = true;
+        operand->Info.Register.IsHigh8 = ND_TRUE;
         break;
 
     case ND_OPT_GPR_rCX:
@@ -2012,7 +2012,7 @@ NdParseOperand(
             operand->Info.Register.Size = Instrux->WordLength;
             operand->Info.Register.Reg = NDR_EAX;
             operand->Info.Register.Count = 8;
-            operand->Info.Register.IsBlock = true;
+            operand->Info.Register.IsBlock = ND_TRUE;
         }
         else
         {
@@ -2022,7 +2022,7 @@ NdParseOperand(
 
     case ND_OPT_A:
         // Fetch the address. NOTE: The size can't be larger than 8 bytes.
-        status = NdFetchAddress(Instrux, Code, Offset, Size, (uint8_t)size);
+        status = NdFetchAddress(Instrux, Code, Offset, Size, (ND_UINT8)size);
         if (!ND_SUCCESS(status))
         {
             return status;
@@ -2046,7 +2046,7 @@ NdParseOperand(
             return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
         }
 
-        operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v;
+        operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v;
         break;
 
     case ND_OPT_C:
@@ -2054,7 +2054,7 @@ NdParseOperand(
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_CR;
         operand->Info.Register.Size = (ND_REG_SIZE)size;
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
         // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing
         // higher 8 control registers.
         if ((ND_CODE_64 != Instrux->DefCode) && (Instrux->HasLock))
@@ -2079,7 +2079,7 @@ NdParseOperand(
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_DR;
         operand->Info.Register.Size = (ND_REG_SIZE)size;
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
 
         // Only DR0-DR7 valid.
         if (operand->Info.Register.Reg >= 8)
@@ -2094,7 +2094,7 @@ NdParseOperand(
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_TR;
         operand->Info.Register.Size = (ND_REG_SIZE)size;
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
 
         // Only TR0-TR7 valid, only on 486.
         if (operand->Info.Register.Reg >= 8)
@@ -2132,7 +2132,7 @@ NdParseOperand(
             operand->Type = ND_OP_REG;
             operand->Info.Register.Type = ND_REG_GPR;
             operand->Info.Register.Size = (ND_REG_SIZE)size;
-            operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+            operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
             operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
                                              (operand->Info.Register.Reg  >= 4) &&
                                              (ND_ENCM_LEGACY == Instrux->EncMode) &&
@@ -2156,17 +2156,17 @@ NdParseOperand(
     case ND_OPT_K:
         // The operand is the stack.
         {
-            static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+            static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
             Instrux->MemoryAccess |= operand->Access.Access;
             operand->Type = ND_OP_MEM;
-            operand->Info.Memory.IsStack = true;
-            operand->Info.Memory.HasBase = true;
+            operand->Info.Memory.IsStack = ND_TRUE;
+            operand->Info.Memory.HasBase = ND_TRUE;
             operand->Info.Memory.Base = NDR_RSP;
             operand->Info.Memory.BaseSize = szLut[Instrux->DefStack];
-            operand->Info.Memory.HasSeg = true;
+            operand->Info.Memory.HasSeg = ND_TRUE;
             operand->Info.Memory.Seg = NDR_SS;
-            Instrux->StackWords = (uint8_t)(operand->Size / Instrux->WordLength);
+            Instrux->StackWords = (ND_UINT8)(operand->Size / Instrux->WordLength);
             Instrux->StackAccess |= operand->Access.Access;
         }
         break;
@@ -2183,7 +2183,7 @@ NdParseOperand(
             return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
         }
 
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
         operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
                                          (operand->Info.Register.Reg >= 4) &&
                                          (ND_ENCM_LEGACY == Instrux->EncMode) &&
@@ -2197,7 +2197,7 @@ NdParseOperand(
             operand->Type = ND_OP_REG;
             operand->Info.Register.Type = ND_REG_GPR;
             operand->Info.Register.Size = (ND_REG_SIZE)size;
-            operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+            operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
             operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
                                              (operand->Info.Register.Reg >= 4) &&
                                              (ND_ENCM_LEGACY == Instrux->EncMode) &&
@@ -2212,10 +2212,10 @@ NdParseOperand(
     case ND_OPT_I:
         // Immediate, encoded in instructon bytes.
         {
-            uint64_t imm;
+            ND_UINT64 imm;
 
             // Fetch the immediate. NOTE: The size won't exceed 8 bytes.
-            status = NdFetchImmediate(Instrux, Code, Offset, Size, (uint8_t)size);
+            status = NdFetchImmediate(Instrux, Code, Offset, Size, (ND_UINT8)size);
             if (!ND_SUCCESS(status))
             {
                 return status;
@@ -2239,7 +2239,7 @@ NdParseOperand(
 
             if (operand->Flags.SignExtendedDws)
             {
-                static const uint8_t wszLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+                static const ND_UINT8 wszLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
 
                 // Get the default word size: the immediate is sign extended to the default word size.
                 operand->Size = wszLut[Instrux->EfOpMode];
@@ -2269,14 +2269,14 @@ NdParseOperand(
 
     case ND_OPT_J:
         // Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes.
-        status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (uint8_t)size);
+        status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (ND_UINT8)size);
         if (!ND_SUCCESS(status))
         {
             return status;
         }
 
         // The instruction is RIP relative.
-        Instrux->IsRipRelative = true;
+        Instrux->IsRipRelative = ND_TRUE;
 
         operand->Type = ND_OP_OFFS;
         // The relative offset is forced to the default word length. Care must be taken with the 32 bit
@@ -2337,11 +2337,11 @@ NdParseOperand(
             // operand info.
             Instrux->MemoryAccess |= operand->Access.Access;
             operand->Type = ND_OP_MEM;
-            operand->Info.Memory.HasDisp = true;
-            operand->Info.Memory.IsDirect = true;
+            operand->Info.Memory.HasDisp = ND_TRUE;
+            operand->Info.Memory.IsDirect = ND_TRUE;
             operand->Info.Memory.DispSize = Instrux->MoffsetLength;
             operand->Info.Memory.Disp = Instrux->Moffset;
-            operand->Info.Memory.HasSeg = true;
+            operand->Info.Memory.HasSeg = ND_TRUE;
             operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
         }
         break;
@@ -2356,7 +2356,7 @@ NdParseOperand(
 memory:
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
 
         if (ND_ADDR_16 == Instrux->AddrMode)
         {
@@ -2370,8 +2370,8 @@ memory:
             {
             case 0:
                 // [bx + si]
-                operand->Info.Memory.HasBase = true;
-                operand->Info.Memory.HasIndex = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
+                operand->Info.Memory.HasIndex = ND_TRUE;
                 operand->Info.Memory.Scale = 1;
                 operand->Info.Memory.Base = NDR_BX;
                 operand->Info.Memory.Index = NDR_SI;
@@ -2381,8 +2381,8 @@ memory:
                 break;
             case 1:
                 // [bx + di]
-                operand->Info.Memory.HasBase = true;
-                operand->Info.Memory.HasIndex = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
+                operand->Info.Memory.HasIndex = ND_TRUE;
                 operand->Info.Memory.Scale = 1;
                 operand->Info.Memory.Base = NDR_BX;
                 operand->Info.Memory.Index = NDR_DI;
@@ -2392,8 +2392,8 @@ memory:
                 break;
             case 2:
                 // [bp + si]
-                operand->Info.Memory.HasBase = true;
-                operand->Info.Memory.HasIndex = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
+                operand->Info.Memory.HasIndex = ND_TRUE;
                 operand->Info.Memory.Scale = 1;
                 operand->Info.Memory.Base = NDR_BP;
                 operand->Info.Memory.Index = NDR_SI;
@@ -2403,8 +2403,8 @@ memory:
                 break;
             case 3:
                 // [bp + di]
-                operand->Info.Memory.HasBase = true;
-                operand->Info.Memory.HasIndex = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
+                operand->Info.Memory.HasIndex = ND_TRUE;
                 operand->Info.Memory.Scale = 1;
                 operand->Info.Memory.Base = NDR_BP;
                 operand->Info.Memory.Index = NDR_DI;
@@ -2414,14 +2414,14 @@ memory:
                 break;
             case 4:
                 // [si]
-                operand->Info.Memory.HasBase = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
                 operand->Info.Memory.Base = NDR_SI;
                 operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
                 operand->Info.Memory.Seg = NDR_DS;
                 break;
             case 5:
                 // [di]
-                operand->Info.Memory.HasBase = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
                 operand->Info.Memory.Base = NDR_DI;
                 operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
                 operand->Info.Memory.Seg = NDR_DS;
@@ -2431,7 +2431,7 @@ memory:
                 if (Instrux->ModRm.mod != 0)
                 {
                     // If mod is not zero, than we have "[bp + displacement]".
-                    operand->Info.Memory.HasBase = true;
+                    operand->Info.Memory.HasBase = ND_TRUE;
                     operand->Info.Memory.Base = NDR_BP;
                     operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
                     operand->Info.Memory.Seg = NDR_SS;
@@ -2444,7 +2444,7 @@ memory:
                 break;
             case 7:
                 // [bx]
-                operand->Info.Memory.HasBase = true;
+                operand->Info.Memory.HasBase = ND_TRUE;
                 operand->Info.Memory.Base = NDR_BX;
                 operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
                 operand->Info.Memory.Seg = NDR_DS;
@@ -2458,7 +2458,7 @@ memory:
         }
         else
         {
-            uint8_t defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT);
+            ND_UINT8 defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT);
 
             // Implicit segment is DS.
             operand->Info.Memory.Seg = NDR_DS;
@@ -2473,9 +2473,9 @@ memory:
                 }
                 else
                 {
-                    operand->Info.Memory.HasBase = true;
+                    operand->Info.Memory.HasBase = ND_TRUE;
                     operand->Info.Memory.BaseSize = defsize;
-                    operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->Sib.base);
+                    operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->Sib.base);
 
                     if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP))
                     {
@@ -2487,9 +2487,9 @@ memory:
                 if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != NDR_RSP) || ND_HAS_VSIB(Instrux))
                 {
                     // Index * Scale is present.
-                    operand->Info.Memory.HasIndex = true;
+                    operand->Info.Memory.HasIndex = ND_TRUE;
                     operand->Info.Memory.IndexSize = defsize;
-                    operand->Info.Memory.Index = (uint8_t)((Instrux->Exs.x << 3) | Instrux->Sib.index);
+                    operand->Info.Memory.Index = (ND_UINT8)((Instrux->Exs.x << 3) | Instrux->Sib.index);
 
                     if (ND_HAS_VSIB(Instrux))
                     {
@@ -2521,9 +2521,9 @@ memory:
                 }
                 else
                 {
-                    operand->Info.Memory.HasBase = true;
+                    operand->Info.Memory.HasBase = ND_TRUE;
                     operand->Info.Memory.BaseSize = defsize;
-                    operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+                    operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
 
                     if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP))
                     {
@@ -2552,11 +2552,11 @@ memory:
                 return ND_STATUS_VSIB_WITHOUT_SIB;
             }
 
-            operand->Info.Memory.IsVsib = true;
+            operand->Info.Memory.IsVsib = ND_TRUE;
 
             operand->Info.Memory.Vsib.IndexSize = vsibIndexSize;
             operand->Info.Memory.Vsib.ElemCount = vsibIndexCount;
-            operand->Info.Memory.Vsib.ElemSize = (uint8_t)(size / vsibIndexCount);
+            operand->Info.Memory.Vsib.ElemSize = (ND_UINT8)(size / vsibIndexCount);
         }
 
         // Handle sibmem addressing, as used by Intel AMX instructions.
@@ -2568,7 +2568,7 @@ memory:
                 return ND_STATUS_SIBMEM_WITHOUT_SIB;
             }
 
-            operand->Info.Memory.IsSibMem = true;
+            operand->Info.Memory.IsSibMem = ND_TRUE;
         }
 
         // If we have broadcast, the operand size is fixed to either 16, 32 or 64 bit, depending on bcast size.
@@ -2577,7 +2577,7 @@ memory:
         // bcstSize / rawSize.
         if (Instrux->HasBroadcast)
         {
-            operand->Info.Memory.HasBroadcast = true;
+            operand->Info.Memory.HasBroadcast = ND_TRUE;
 
             if (opd & ND_OPD_B32)
             {
@@ -2604,7 +2604,7 @@ memory:
         // use compressed displacement addressing.
         if (Instrux->HasCompDisp)
         {
-            operand->Info.Memory.HasCompDisp = true;
+            operand->Info.Memory.HasCompDisp = ND_TRUE;
             operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
         }
 
@@ -2617,17 +2617,17 @@ memory:
         // AG, if this is the case.
         if (ND_HAS_AG(Instrux))
         {
-            operand->Info.Memory.IsAG = true;
+            operand->Info.Memory.IsAG = ND_TRUE;
 
             // Address generation instructions ignore the segment prefixes. Examples are LEA and MPX instructions.
-            operand->Info.Memory.HasSeg = false;
+            operand->Info.Memory.HasSeg = ND_FALSE;
             operand->Info.Memory.Seg = 0;
         }
 
         // Shadow Stack Access, if this is the case.
         if (ND_HAS_SHS(Instrux))
         {
-            operand->Info.Memory.IsShadowStack = true;
+            operand->Info.Memory.IsShadowStack = ND_TRUE;
             operand->Info.Memory.ShStkType = ND_SHSTK_EXPLICIT;
         }
 
@@ -2645,7 +2645,7 @@ memory:
             operand->Type = ND_OP_REG;
             operand->Info.Register.Type = ND_REG_SSE;
             operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
-            operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.vp << 4) | Instrux->Exs.v);
+            operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.vp << 4) | Instrux->Exs.v);
         }
         break;
 
@@ -2679,7 +2679,7 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_SSE;
         operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
         if (Instrux->HasEvex || Instrux->HasMvex)
         {
             operand->Info.Register.Reg |= Instrux->Exs.x << 4;
@@ -2691,7 +2691,7 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_SSE;
         operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
         if (Instrux->HasEvex || Instrux->HasMvex)
         {
             operand->Info.Register.Reg |= Instrux->Exs.rp << 4;
@@ -2705,7 +2705,7 @@ memory:
             operand->Type = ND_OP_REG;
             operand->Info.Register.Type = ND_REG_SSE;
             operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
-            operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+            operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
             if (Instrux->HasEvex || Instrux->HasMvex)
             {
                 operand->Info.Register.Reg |= Instrux->Exs.x << 4;
@@ -2723,10 +2723,10 @@ memory:
         // RSI/RDI based addressing, as used by string instructions.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
+        operand->Info.Memory.HasBase = ND_TRUE;
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
-        operand->Info.Memory.HasSeg = true;
-        operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? NDR_RSI : NDR_RDI));
+        operand->Info.Memory.HasSeg = ND_TRUE;
+        operand->Info.Memory.Base = (ND_UINT8)(((opt == ND_OPT_X) ? NDR_RSI : NDR_RDI));
         operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt);
         // DS:rSI supports segment overriding. ES:rDI does not.
         if (opt == ND_OPT_Y)
@@ -2743,14 +2743,14 @@ memory:
         // [rBX + AL], used by XLAT.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
-        operand->Info.Memory.HasIndex = true;
+        operand->Info.Memory.HasBase = ND_TRUE;
+        operand->Info.Memory.HasIndex = ND_TRUE;
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
         operand->Info.Memory.IndexSize = ND_SIZE_8BIT;  // Always 1 Byte.
         operand->Info.Memory.Base = NDR_RBX;            // Always rBX.
         operand->Info.Memory.Index = NDR_AL;            // Always AL.
         operand->Info.Memory.Scale = 1;                 // Always 1.
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
         operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
         break;
 
@@ -2758,10 +2758,10 @@ memory:
         // [rAX], used implicitly by MONITOR, MONITORX and RMPADJUST instructions.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
+        operand->Info.Memory.HasBase = ND_TRUE;
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
         operand->Info.Memory.Base = NDR_RAX;            // Always rAX.
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
         operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
         break;
 
@@ -2769,10 +2769,10 @@ memory:
         // [rCX], used implicitly by RMPUPDATE.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
+        operand->Info.Memory.HasBase = ND_TRUE;
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
         operand->Info.Memory.Base = NDR_RCX;            // Always rCX.
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
         operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
         break;
 
@@ -2780,7 +2780,7 @@ memory:
         // Shadow stack access using the current SSP.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.IsShadowStack = true;
+        operand->Info.Memory.IsShadowStack = ND_TRUE;
         operand->Info.Memory.ShStkType = ND_SHSTK_SSP_LD_ST;
         break;
 
@@ -2788,7 +2788,7 @@ memory:
         // Shadow stack access using the IA32_PL0_SSP.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.IsShadowStack = true;
+        operand->Info.Memory.IsShadowStack = ND_TRUE;
         operand->Info.Memory.ShStkType = ND_SHSTK_PL0_SSP;
         break;
 
@@ -2796,7 +2796,7 @@ memory:
         // Shadow stack push/pop access.
         Instrux->MemoryAccess |= operand->Access.Access;
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.IsShadowStack = true;
+        operand->Info.Memory.IsShadowStack = ND_TRUE;
         operand->Info.Memory.ShStkType = ND_SHSTK_SSP_PUSH_POP;
         break;
 
@@ -2805,7 +2805,7 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_GPR;
         operand->Info.Register.Size = (ND_REG_SIZE)size;
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7));
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7));
         operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
                                          (operand->Info.Register.Reg >= 4) &&
                                          (ND_ENCM_LEGACY == Instrux->EncMode) &&
@@ -2817,7 +2817,7 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_BND;
         operand->Info.Register.Size = (ND_REG_SIZE)size;
-        operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
         if (operand->Info.Register.Reg >= 4)
         {
             return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
@@ -2831,7 +2831,7 @@ memory:
             operand->Type = ND_OP_REG;
             operand->Info.Register.Type = ND_REG_BND;
             operand->Info.Register.Size = (ND_REG_SIZE)size;
-            operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+            operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
             if (operand->Info.Register.Reg >= 4)
             {
                 return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
@@ -2855,7 +2855,7 @@ memory:
         }
 
         operand->Info.Register.Size = ND_SIZE_64BIT;
-        operand->Info.Register.Reg = (uint8_t)(Instrux->ModRm.reg);
+        operand->Info.Register.Reg = (ND_UINT8)(Instrux->ModRm.reg);
 
         break;
 
@@ -2864,7 +2864,7 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_MSK;
         operand->Info.Register.Size = ND_SIZE_64BIT;
-        operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v;
+        operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v;
         if (operand->Info.Register.Reg >= 8)
         {
             return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
@@ -2902,20 +2902,20 @@ memory:
         // - The ES segment register cannot be overridden
         // - The size of the base register is selected by the address size, not the operand size.
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
-        operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+        operand->Info.Memory.HasBase = ND_TRUE;
+        operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
         operand->Info.Memory.Seg = NDR_ES;
         break;
 
     case ND_OPT_mM:
         // Sigh. rm field inside mod r/m encodes memory, even if mod is 3.
         operand->Type = ND_OP_MEM;
-        operand->Info.Memory.HasBase = true;
-        operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.m << 3) | Instrux->ModRm.rm);
+        operand->Info.Memory.HasBase = ND_TRUE;
+        operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.m << 3) | Instrux->ModRm.rm);
         operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
-        operand->Info.Memory.HasSeg = true;
+        operand->Info.Memory.HasSeg = ND_TRUE;
         operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
         break;
 
@@ -2978,7 +2978,7 @@ memory:
         {
             operand->Info.Register.Count = opb;
             operand->Info.Register.Reg &= ~(opb - 1);
-            operand->Info.Register.IsBlock = true;
+            operand->Info.Register.IsBlock = ND_TRUE;
         }
         else
         {
@@ -2998,8 +2998,8 @@ memory:
         // mask register is not k0 (which implies "no masking").
         if ((opd & ND_OPD_MASK) && (Instrux->HasMask))
         {
-            operand->Decorator.HasMask = true;
-            operand->Decorator.Mask.Msk = (uint8_t)Instrux->Exs.k;
+            operand->Decorator.HasMask = ND_TRUE;
+            operand->Decorator.Mask.Msk = (ND_UINT8)Instrux->Exs.k;
         }
 
         // Check for zeroing. The operand must support zeroing and the z bit inside evex3 must be set. Note that
@@ -3011,15 +3011,15 @@ memory:
                 return ND_STATUS_ZEROING_ON_MEMORY;
             }
 
-            operand->Decorator.HasZero = true;
+            operand->Decorator.HasZero = ND_TRUE;
         }
 
         // Check for broadcast again. We've already filled the broadcast size before parsing the op size.
         if ((opd & ND_OPD_BCAST) && (Instrux->HasBroadcast))
         {
-            operand->Decorator.HasBroadcast = true;
-            operand->Decorator.Broadcast.Size = (uint8_t)operand->Size;
-            operand->Decorator.Broadcast.Count = (uint8_t)(bcstSize / operand->Size);
+            operand->Decorator.HasBroadcast = ND_TRUE;
+            operand->Decorator.Broadcast.Size = (ND_UINT8)operand->Size;
+            operand->Decorator.Broadcast.Count = (ND_UINT8)(bcstSize / operand->Size);
         }
 
         if (opd & ND_OPD_SAE)
@@ -3043,26 +3043,26 @@ memory:
 static NDSTATUS
 NdFindInstruction(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t Offset,
-    size_t Size,
+    const ND_UINT8 *Code,
+    ND_UINT8 Offset,
+    ND_SIZET Size,
     ND_INSTRUCTION **InsDef
     )
 {
     NDSTATUS status;
     const ND_TABLE *pTable;
     ND_INSTRUCTION *pIns;
-    bool stop, redf2, redf3;
-    uint32_t nextOpcode, nextIndex;
+    ND_BOOL stop, redf2, redf3;
+    ND_UINT32 nextOpcode, nextIndex;
 
     UNREFERENCED_PARAMETER(Offset);
 
     // pre-init
     status = ND_STATUS_SUCCESS;
-    pIns = NULL;
-    stop = false;
+    pIns = (ND_INSTRUCTION *)ND_NULL;
+    stop = ND_FALSE;
     nextOpcode = 0;
-    redf2 = redf3 = false;
+    redf2 = redf3 = ND_FALSE;
 
     switch (Instrux->EncMode)
     {
@@ -3079,18 +3079,18 @@ NdFindInstruction(
         pTable = (const ND_TABLE *)gEvexTable;
         break;
     default:
-        pTable = (const ND_TABLE *)NULL;
+        pTable = (const ND_TABLE *)ND_NULL;
         break;
     }
 
-    while ((!stop) && (NULL != pTable))
+    while ((!stop) && (ND_NULL != pTable))
     {
         switch (pTable->Type)
         {
         case ND_ILUT_INSTRUCTION:
             // We've found the leaf entry, which is an instruction - we can leave.
             pIns = (ND_INSTRUCTION *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction);
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_ILUT_OPCODE:
@@ -3098,7 +3098,7 @@ NdFindInstruction(
             status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size);
             if (!ND_SUCCESS(status))
             {
-                stop = true;
+                stop = ND_TRUE;
                 break;
             }
             pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]];
@@ -3112,7 +3112,7 @@ NdFindInstruction(
                 status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
 
@@ -3120,7 +3120,7 @@ NdFindInstruction(
                 status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
             }
@@ -3129,7 +3129,7 @@ NdFindInstruction(
             status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size);
             if (!ND_SUCCESS(status))
             {
-                stop = true;
+                stop = ND_TRUE;
                 break;
             }
 
@@ -3144,7 +3144,7 @@ NdFindInstruction(
                 status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
 
@@ -3152,7 +3152,7 @@ NdFindInstruction(
                 status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
             }
@@ -3169,7 +3169,7 @@ NdFindInstruction(
                 status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
 
@@ -3177,7 +3177,7 @@ NdFindInstruction(
                 status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
             }
@@ -3194,7 +3194,7 @@ NdFindInstruction(
                 status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
 
@@ -3202,7 +3202,7 @@ NdFindInstruction(
                 status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
                 if (!ND_SUCCESS(status))
                 {
-                    stop = true;
+                    stop = ND_TRUE;
                     break;
                 }
             }
@@ -3217,20 +3217,20 @@ NdFindInstruction(
             {
                 // We can only redirect once through one mandatory prefix, otherwise we may
                 // enter an infinite loop (see CRC32 Gw Eb -> 0x66 0xF2 0x0F ...)
-                redf2 = true;
+                redf2 = ND_TRUE;
                 nextIndex = ND_ILUT_INDEX_MAN_PREF_F2;
-                Instrux->HasMandatoryF2 = true;
+                Instrux->HasMandatoryF2 = ND_TRUE;
             }
             else if ((Instrux->Rep == 0xF3) && !redf3)
             {
-                redf3 = true;
+                redf3 = ND_TRUE;
                 nextIndex = ND_ILUT_INDEX_MAN_PREF_F3;
-                Instrux->HasMandatoryF3 = true;
+                Instrux->HasMandatoryF3 = ND_TRUE;
             }
             else if (Instrux->HasOpSize)
             {
                 nextIndex = ND_ILUT_INDEX_MAN_PREF_66;
-                Instrux->HasMandatory66 = true;
+                Instrux->HasMandatory66 = ND_TRUE;
             }
             else
             {
@@ -3241,14 +3241,14 @@ NdFindInstruction(
 
         case ND_ILUT_MODE:
             {
-                static const uint8_t indexes[3] =
+                static const ND_UINT8 indexes[3] =
                 {
                     ND_ILUT_INDEX_MODE_16, ND_ILUT_INDEX_MODE_32, ND_ILUT_INDEX_MODE_64
                 };
 
                 nextIndex = ND_ILUT_INDEX_MODE_NONE;
 
-                if (NULL != pTable->Table[indexes[Instrux->DefCode]])
+                if (ND_NULL != pTable->Table[indexes[Instrux->DefCode]])
                 {
                     nextIndex = indexes[Instrux->DefCode];
                 }
@@ -3259,14 +3259,14 @@ NdFindInstruction(
 
         case ND_ILUT_DSIZE:
             {
-                static const uint8_t indexes[3] =
+                static const ND_UINT8 indexes[3] =
                 {
                     ND_ILUT_INDEX_DSIZE_16, ND_ILUT_INDEX_DSIZE_32, ND_ILUT_INDEX_DSIZE_64
                 };
 
                 nextIndex = ND_ILUT_INDEX_DSIZE_NONE;
 
-                if (NULL != pTable->Table[indexes[Instrux->OpMode]])
+                if (ND_NULL != pTable->Table[indexes[Instrux->OpMode]])
                 {
                     nextIndex = indexes[Instrux->OpMode];
                 }
@@ -3274,11 +3274,11 @@ NdFindInstruction(
                 // Handle default/forced redirections in 64 bit mode.
                 if (ND_CODE_64 == Instrux->DefCode)
                 {
-                    if ((NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w))
+                    if ((ND_NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w))
                     {
                         nextIndex = 4;
                     }
-                    else if (NULL != pTable->Table[5])
+                    else if (ND_NULL != pTable->Table[5])
                     {
                         nextIndex = 5;
                     }
@@ -3290,11 +3290,11 @@ NdFindInstruction(
 
         case ND_ILUT_ASIZE:
             {
-                static const uint8_t indexes[3] = {ND_ILUT_INDEX_ASIZE_16, ND_ILUT_INDEX_ASIZE_32, ND_ILUT_INDEX_ASIZE_64};
+                static const ND_UINT8 indexes[3] = {ND_ILUT_INDEX_ASIZE_16, ND_ILUT_INDEX_ASIZE_32, ND_ILUT_INDEX_ASIZE_64};
 
                 nextIndex = ND_ILUT_INDEX_ASIZE_NONE;
 
-                if (NULL != pTable->Table[indexes[Instrux->AddrMode]])
+                if (ND_NULL != pTable->Table[indexes[Instrux->AddrMode]])
                 {
                     nextIndex = indexes[Instrux->AddrMode];
                 }
@@ -3305,23 +3305,23 @@ NdFindInstruction(
 
         case ND_ILUT_AUXILIARY:
             // Auxiliary redirection. Default to table[0] if nothing matches.
-            if (Instrux->HasRex && Instrux->Rex.b && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB]))
+            if (Instrux->HasRex && Instrux->Rex.b && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB]))
             {
                 nextIndex = ND_ILUT_INDEX_AUX_REXB;
             }
-            else if (Instrux->HasRex && Instrux->Rex.w && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW]))
+            else if (Instrux->HasRex && Instrux->Rex.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW]))
             {
                 nextIndex = ND_ILUT_INDEX_AUX_REXW;
             }
-            else if ((Instrux->DefCode == ND_CODE_64) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_O64]))
+            else if ((Instrux->DefCode == ND_CODE_64) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_O64]))
             {
                 nextIndex = ND_ILUT_INDEX_AUX_O64;
             }
-            else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_F3]))
+            else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_F3]))
             {
                 nextIndex = ND_ILUT_INDEX_AUX_F3;
             }
-            else if ((Instrux->Rep != 0) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP]))
+            else if ((Instrux->Rep != 0) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP]))
             {
                 nextIndex = ND_ILUT_INDEX_AUX_REP;
             }
@@ -3334,7 +3334,7 @@ NdFindInstruction(
 
         case ND_ILUT_VENDOR:
             // Vendor redirection. Go to the vendor specific entry.
-            if (NULL != pTable->Table[Instrux->VendMode])
+            if (ND_NULL != pTable->Table[Instrux->VendMode])
             {
                 pTable = (const ND_TABLE *)pTable->Table[Instrux->VendMode];
             }
@@ -3346,15 +3346,15 @@ NdFindInstruction(
 
         case ND_ILUT_FEATURE:
             // Feature redirection. Normally NOP if feature is not set, but may be something else if feature is set.
-            if ((NULL != pTable->Table[ND_ILUT_FEATURE_MPX]) && !!(Instrux->FeatMode & ND_FEAT_MPX))
+            if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_MPX]) && !!(Instrux->FeatMode & ND_FEAT_MPX))
             {
                 pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_MPX];
             }
-            else if ((NULL != pTable->Table[ND_ILUT_FEATURE_CET]) && !!(Instrux->FeatMode & ND_FEAT_CET))
+            else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_CET]) && !!(Instrux->FeatMode & ND_FEAT_CET))
             {
                 pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_CET];
             }
-            else if ((NULL != pTable->Table[ND_ILUT_FEATURE_CLDEMOTE]) && !!(Instrux->FeatMode & ND_FEAT_CLDEMOTE))
+            else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_CLDEMOTE]) && !!(Instrux->FeatMode & ND_FEAT_CLDEMOTE))
             {
                 pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_CLDEMOTE];
             }
@@ -3385,7 +3385,7 @@ NdFindInstruction(
                     status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size);
                     if (!ND_SUCCESS(status))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
@@ -3393,7 +3393,7 @@ NdFindInstruction(
                     status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
                     if (!ND_SUCCESS(status))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
                 }
@@ -3402,11 +3402,11 @@ NdFindInstruction(
                 {
                     // We use the maximum vector length of the instruction. If the instruction does not support
                     // SAE or ER, a #UD would be generated. We check for this later.
-                    if (NULL != pTable->Table[2])
+                    if (ND_NULL != pTable->Table[2])
                     {
                         pTable = (const ND_TABLE *)pTable->Table[2];
                     }
-                    else if (NULL != pTable->Table[1])
+                    else if (ND_NULL != pTable->Table[1])
                     {
                         pTable = (const ND_TABLE *)pTable->Table[1];
                     }
@@ -3437,7 +3437,7 @@ NdFindInstruction(
 
         default:
             status = ND_STATUS_INTERNAL_ERROR;
-            stop = true;
+            stop = ND_TRUE;
             break;
         }
     }
@@ -3447,7 +3447,7 @@ NdFindInstruction(
         goto cleanup_and_exit;
     }
 
-    if (NULL != pIns)
+    if (ND_NULL != pIns)
     {
         // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now.
         if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm))
@@ -3604,8 +3604,8 @@ NdGetEffectiveOpMode(
     INSTRUX *Instrux
     )
 {
-    static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
-    bool width, f64, d64, has66;
+    static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+    ND_BOOL width, f64, d64, has66;
 
     if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64))
     {
@@ -3668,7 +3668,7 @@ NdPostProcessEvex(
             {
                 Instrux->HasEr = 1;
                 Instrux->HasSae = 1;
-                Instrux->RoundingMode = (uint8_t)Instrux->Exs.l;
+                Instrux->RoundingMode = (ND_UINT8)Instrux->Exs.l;
             }
             else if (Instrux->ValidDecorators.Sae)
             {
@@ -3745,7 +3745,7 @@ NdPostProcessEvex(
     // is scaled according to the data type accessed by the instruction.
     if (Instrux->HasDisp && Instrux->DispLength == 1)
     {
-        Instrux->HasCompDisp = true;
+        Instrux->HasCompDisp = ND_TRUE;
     }
 
     return ND_STATUS_SUCCESS;
@@ -3798,8 +3798,8 @@ NdValidateInstruction(
         // The exception is SCATTER*, which can use the VSIB reg as two sources.
         if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
         {
-            uint8_t usedVects[32] = { 0 };
-            uint32_t i;
+            ND_UINT8 usedVects[32] = { 0 };
+            ND_UINT32 i;
 
             for (i = 0; i < Instrux->OperandsCount; i++)
             {
@@ -3879,12 +3879,12 @@ NdValidateInstruction(
 NDSTATUS
 NdDecodeEx2(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    size_t Size,
-    uint8_t DefCode,
-    uint8_t DefData,
-    uint8_t DefStack,
-    uint8_t Vendor
+    const ND_UINT8 *Code,
+    ND_SIZET Size,
+    ND_UINT8 DefCode,
+    ND_UINT8 DefData,
+    ND_UINT8 DefStack,
+    ND_UINT8 Vendor
     )
 {
     ND_CONTEXT opt;
@@ -3904,28 +3904,28 @@ NdDecodeEx2(
 NDSTATUS
 NdDecodeWithContext(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    size_t Size,
+    const ND_UINT8 *Code,
+    ND_SIZET Size,
     ND_CONTEXT *Context
     )
 {
     NDSTATUS status;
     PND_INSTRUCTION pIns;
-    uint32_t opIndex;
-    size_t i;
+    ND_UINT32 opIndex;
+    ND_SIZET i;
 
     // pre-init
     status = ND_STATUS_SUCCESS;
-    pIns = NULL;
+    pIns = (PND_INSTRUCTION)ND_NULL;
     opIndex = 0;
 
     // validate
-    if (NULL == Instrux)
+    if (ND_NULL == Instrux)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == Code)
+    if (ND_NULL == Code)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -3935,7 +3935,7 @@ NdDecodeWithContext(
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == Context)
+    if (ND_NULL == Context)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -3958,11 +3958,11 @@ NdDecodeWithContext(
     // Initialize with zero.
     nd_memzero(Instrux, sizeof(INSTRUX));
 
-    Instrux->DefCode = (uint8_t)Context->DefCode;
-    Instrux->DefData = (uint8_t)Context->DefData;
-    Instrux->DefStack = (uint8_t)Context->DefStack;
-    Instrux->VendMode = (uint8_t)Context->VendMode;
-    Instrux->FeatMode = (uint8_t)Context->FeatMode;
+    Instrux->DefCode = (ND_UINT8)Context->DefCode;
+    Instrux->DefData = (ND_UINT8)Context->DefData;
+    Instrux->DefStack = (ND_UINT8)Context->DefStack;
+    Instrux->VendMode = (ND_UINT8)Context->VendMode;
+    Instrux->FeatMode = (ND_UINT8)Context->FeatMode;
 
     // Copy the instruction bytes.
     for (opIndex = 0; opIndex < ((Size < ND_MAX_INSTRUCTION_LENGTH) ? Size : ND_MAX_INSTRUCTION_LENGTH); opIndex++)
@@ -4008,14 +4008,14 @@ NdDecodeWithContext(
     Instrux->ValidModes.Raw = pIns->ValidModes;
     Instrux->ValidPrefixes.Raw = pIns->ValidPrefixes;
     Instrux->ValidDecorators.Raw = pIns->ValidDecorators;
-    *((uint8_t*)&Instrux->FpuFlagsAccess) = pIns->FpuFlags;
+    *((ND_UINT8*)&Instrux->FpuFlagsAccess) = pIns->FpuFlags;
     // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used.
     Instrux->ExceptionClass = pIns->ExcClass;
     Instrux->ExceptionType = pIns->ExcType;
     // Used only by EVEX instructions.
     Instrux->TupleType = pIns->TupleType;
 
-    // Copy the mnemonic, up until the NULL terminator.
+    // Copy the mnemonic, up until the ND_NULL terminator.
     for (i = 0; i < sizeof(Instrux->Mnemonic); i++)
     {
         Instrux->Mnemonic[i] = gMnemonics[pIns->Mnemonic][i];
@@ -4086,11 +4086,11 @@ NdDecodeWithContext(
     {
         if ((ND_XACQUIRE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XACQUIRE))
         {
-            Instrux->IsXacquireEnabled = true;
+            Instrux->IsXacquireEnabled = ND_TRUE;
         }
         else if ((ND_XRELEASE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XRELEASE))
         {
-            Instrux->IsXreleaseEnabled = true;
+            Instrux->IsXreleaseEnabled = ND_TRUE;
         }
     }
 
@@ -4133,10 +4133,10 @@ NdDecodeWithContext(
 NDSTATUS
 NdDecodeEx(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    size_t Size,
-    uint8_t DefCode,
-    uint8_t DefData
+    const ND_UINT8 *Code,
+    ND_SIZET Size,
+    ND_UINT8 DefCode,
+    ND_UINT8 DefData
     )
 {
     return NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY);
@@ -4149,9 +4149,9 @@ NdDecodeEx(
 NDSTATUS
 NdDecode(
     INSTRUX *Instrux,
-    const uint8_t *Code,
-    uint8_t DefCode,
-    uint8_t DefData
+    const ND_UINT8 *Code,
+    ND_UINT8 DefCode,
+    ND_UINT8 DefData
     )
 {
     return NdDecodeEx2(Instrux, Code, ND_MAX_INSTRUCTION_LENGTH, DefCode, DefData, DefCode, ND_VEND_ANY);
diff --git a/bddisasm/bddisasm.vcxproj b/bddisasm/bddisasm.vcxproj
index abcd197..062d6fb 100644
--- a/bddisasm/bddisasm.vcxproj
+++ b/bddisasm/bddisasm.vcxproj
@@ -1,6 +1,10 @@
 <?xml version="1.0" encoding="utf-8"?>
 <Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
   <ItemGroup Label="ProjectConfigurations">
+    <ProjectConfiguration Include="DebugKernel|ARM64">
+      <Configuration>DebugKernel</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="DebugKernel|Win32">
       <Configuration>DebugKernel</Configuration>
       <Platform>Win32</Platform>
@@ -9,6 +13,10 @@
       <Configuration>DebugKernel</Configuration>
       <Platform>x64</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="Debug|ARM64">
+      <Configuration>Debug</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Debug|Win32">
       <Configuration>Debug</Configuration>
       <Platform>Win32</Platform>
@@ -17,6 +25,10 @@
       <Configuration>Debug</Configuration>
       <Platform>x64</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="ReleaseKernel|ARM64">
+      <Configuration>ReleaseKernel</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="ReleaseKernel|Win32">
       <Configuration>ReleaseKernel</Configuration>
       <Platform>Win32</Platform>
@@ -25,6 +37,10 @@
       <Configuration>ReleaseKernel</Configuration>
       <Platform>x64</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="Release|ARM64">
+      <Configuration>Release</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Release|Win32">
       <Configuration>Release</Configuration>
       <Platform>Win32</Platform>
@@ -78,6 +94,12 @@
     <CharacterSet>Unicode</CharacterSet>
     <WholeProgramOptimization>true</WholeProgramOptimization>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <PlatformToolset>v142</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+    <WholeProgramOptimization>true</WholeProgramOptimization>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'" Label="Configuration">
     <ConfigurationType>StaticLibrary</ConfigurationType>
     <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
@@ -88,11 +110,26 @@
     <SupportsPackaging>false</SupportsPackaging>
     <ALLOW_DATE_TIME>1</ALLOW_DATE_TIME>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+    <WholeProgramOptimization>true</WholeProgramOptimization>
+    <TargetVersion></TargetVersion>
+    <DriverTargetPlatform>Desktop</DriverTargetPlatform>
+    <SupportsPackaging>false</SupportsPackaging>
+    <ALLOW_DATE_TIME>1</ALLOW_DATE_TIME>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'" Label="Configuration">
     <ConfigurationType>StaticLibrary</ConfigurationType>
     <PlatformToolset>v142</PlatformToolset>
     <CharacterSet>Unicode</CharacterSet>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <PlatformToolset>v142</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'" Label="Configuration">
     <ConfigurationType>StaticLibrary</ConfigurationType>
     <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
@@ -102,6 +139,15 @@
     <SupportsPackaging>false</SupportsPackaging>
     <ALLOW_DATE_TIME>1</ALLOW_DATE_TIME>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+    <TargetVersion></TargetVersion>
+    <DriverTargetPlatform>Desktop</DriverTargetPlatform>
+    <SupportsPackaging>false</SupportsPackaging>
+    <ALLOW_DATE_TIME>1</ALLOW_DATE_TIME>
+  </PropertyGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
   <ImportGroup Label="ExtensionSettings">
   </ImportGroup>
@@ -120,15 +166,27 @@
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <PropertyGroup Label="UserMacros" />
   <PropertyGroup>
     <_ProjectFileVersion>14.0.23107.0</_ProjectFileVersion>
@@ -145,10 +203,18 @@
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'">
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
@@ -161,10 +227,18 @@
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'">
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
     <PreBuildEvent>
       <Command>
@@ -250,6 +324,39 @@
       <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
     </Lib>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <PreBuildEvent>
+      <Command>
+      </Command>
+    </PreBuildEvent>
+    <Midl />
+    <ClCompile>
+      <AdditionalOptions>/D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <Optimization>Disabled</Optimization>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <AdditionalIncludeDirectories>include;..\inc;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <StringPooling>true</StringPooling>
+      <MinimalRebuild>true</MinimalRebuild>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <RuntimeLibrary>MultiThreadedDebugDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+    </ClCompile>
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+    <Lib>
+      <AdditionalLibraryDirectories>x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+      <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
+    </Lib>
+  </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'">
     <PreBuildEvent>
       <Command>
@@ -287,6 +394,42 @@
       <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
     </Lib>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'">
+    <PreBuildEvent>
+      <Command>
+      </Command>
+    </PreBuildEvent>
+    <Midl />
+    <ClCompile>
+      <AdditionalOptions>/kernel /D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <Optimization>Disabled</Optimization>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <AdditionalIncludeDirectories>include;..\inc;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <StringPooling>true</StringPooling>
+      <MinimalRebuild>true</MinimalRebuild>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <RuntimeLibrary>MultiThreadedDebugDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <ForcedIncludeFiles>
+      </ForcedIncludeFiles>
+    </ClCompile>
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+    <Lib>
+      <AdditionalLibraryDirectories>x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+      <SubSystem>Native</SubSystem>
+      <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
+    </Lib>
+  </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
     <PreBuildEvent>
       <Command>
@@ -367,6 +510,48 @@
       <TreatWarningAsError>true</TreatWarningAsError>
       <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
       <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <CompileAs>Default</CompileAs>
+    </ClCompile>
+    <ProjectReference>
+      <LinkLibraryDependencies>false</LinkLibraryDependencies>
+    </ProjectReference>
+    <Lib>
+      <IgnoreAllDefaultLibraries>true</IgnoreAllDefaultLibraries>
+      <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
+    </Lib>
+    <PostBuildEvent>
+      <Command>
+      </Command>
+    </PostBuildEvent>
+  </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <PreBuildEvent>
+      <Command>
+      </Command>
+    </PreBuildEvent>
+    <Midl />
+    <ClCompile>
+      <AdditionalOptions>/D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <Optimization>MaxSpeed</Optimization>
+      <InlineFunctionExpansion>AnySuitable</InlineFunctionExpansion>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <WholeProgramOptimization>false</WholeProgramOptimization>
+      <AdditionalIncludeDirectories>include;..\inc;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <StringPooling>true</StringPooling>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <FunctionLevelLinking>true</FunctionLevelLinking>
+      <PrecompiledHeader>
+      </PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <CompileAs>Default</CompileAs>
     </ClCompile>
     <ProjectReference>
       <LinkLibraryDependencies>false</LinkLibraryDependencies>
@@ -419,6 +604,44 @@
       <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
     </Lib>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">
+    <PreBuildEvent>
+      <Command>
+      </Command>
+    </PreBuildEvent>
+    <Midl />
+    <ClCompile>
+      <AdditionalOptions>/kernel /D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <Optimization>MaxSpeed</Optimization>
+      <InlineFunctionExpansion>AnySuitable</InlineFunctionExpansion>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <WholeProgramOptimization>false</WholeProgramOptimization>
+      <AdditionalIncludeDirectories>include;..\inc;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <StringPooling>true</StringPooling>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <FunctionLevelLinking>true</FunctionLevelLinking>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <ForcedIncludeFiles>
+      </ForcedIncludeFiles>
+    </ClCompile>
+    <ProjectReference>
+      <LinkLibraryDependencies>false</LinkLibraryDependencies>
+    </ProjectReference>
+    <Lib>
+      <IgnoreAllDefaultLibraries>true</IgnoreAllDefaultLibraries>
+      <SubSystem>Native</SubSystem>
+      <LinkTimeCodeGeneration>false</LinkTimeCodeGeneration>
+    </Lib>
+  </ItemDefinitionGroup>
   <ItemGroup>
     <ClCompile Include="bdformat.c" />
     <ClCompile Include="bdhelpers.c" />
@@ -426,14 +649,19 @@
     <ClCompile Include="bddisasm.c">
       <PrecompiledHeader Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|Win32'">NotUsing</PrecompiledHeader>
       <PrecompiledHeader Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'">NotUsing</PrecompiledHeader>
+      <PrecompiledHeader Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">NotUsing</PrecompiledHeader>
       <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='DebugKernel|Win32'">
       </ForcedIncludeFiles>
       <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'">
       </ForcedIncludeFiles>
+      <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'">
+      </ForcedIncludeFiles>
       <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|Win32'">
       </ForcedIncludeFiles>
       <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'">
       </ForcedIncludeFiles>
+      <ForcedIncludeFiles Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">
+      </ForcedIncludeFiles>
     </ClCompile>
   </ItemGroup>
   <ItemGroup>
diff --git a/bddisasm/bdformat.c b/bddisasm/bdformat.c
index fc5842c..1de15f9 100644
--- a/bddisasm/bdformat.c
+++ b/bddisasm/bdformat.c
@@ -113,7 +113,7 @@ static const char *gRegTile[] =
 static const char *gConditionCodes[] =
 {
     "EQ", "LT", "LE", "UNORD", "NEQ", "NLT", "NLE", "ORD",
-    "EQ_UQ", "NGE", "NGT", "false", "NEQ_OQ", "GE", "GT", "TRUE",
+    "EQ_UQ", "NGE", "NGT", "ND_FALSE", "NEQ_OQ", "GE", "GT", "TRUE",
     "EQ_OS", "LT_OQ", "LE_OQ", "UNORD_S", "NEQ_US", "NLT_UQ", "NLE_UQ", "ORD_S",
     "EQ_US", "NGE_UQ", "NGT_UQ", "FALSE_OS", "NEQ_OS", "GE_OQ", "GT_OQ", "TRUE_US",
 };
@@ -131,7 +131,7 @@ static const char *gEmbeddedRounding[] =
 static NDSTATUS
 NdSprintf(
     char *Destination,
-    size_t DestinationSize,
+    ND_SIZET DestinationSize,
     const char *Formatstring,
     ...
     )
@@ -142,12 +142,12 @@ NdSprintf(
     int res;
     va_list args;
 
-    if (NULL == Destination)
+    if (ND_NULL == Destination)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == Formatstring)
+    if (ND_NULL == Formatstring)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -162,7 +162,7 @@ NdSprintf(
 
     va_end(args);
 
-    if ((res < 0) || ((size_t)res >= DestinationSize - 1))
+    if ((res < 0) || ((ND_SIZET)res >= DestinationSize - 1))
     {
         return ND_STATUS_BUFFER_OVERFLOW;
     }
@@ -177,32 +177,32 @@ NdSprintf(
 NDSTATUS
 NdToText(
     const INSTRUX *Instrux,
-    uint64_t Rip,
-    uint32_t BufferSize,
+    ND_UINT64 Rip,
+    ND_UINT32 BufferSize,
     char *Buffer
     )
 {
     NDSTATUS status;
     char *res, temp[64];
-    uint32_t opIndex, opsStored;
+    ND_UINT32 opIndex, opsStored;
     const ND_OPERAND *pOp;
-    bool alignmentStored;
+    ND_BOOL alignmentStored;
 
     // pre-init
     status = ND_STATUS_SUCCESS;
-    res = NULL;
+    res = (char *)ND_NULL;
     opIndex = 0;
     opsStored = 0;
-    pOp = NULL;
-    alignmentStored = false;
+    pOp = (const ND_OPERAND *)ND_NULL;
+    alignmentStored = ND_FALSE;
 
     // Validate args.
-    if (NULL == Instrux)
+    if (ND_NULL == Instrux)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == Buffer)
+    if (ND_NULL == Buffer)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -225,12 +225,12 @@ NdToText(
             if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ)
             {
                 res = nd_strcat_s(Buffer, BufferSize, "REPZ ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ)
             {
                 res = nd_strcat_s(Buffer, BufferSize, "REPNZ ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
         }
 
@@ -240,24 +240,24 @@ NdToText(
             if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ)
             {
                 res = nd_strcat_s(Buffer, BufferSize, "REP ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ)
             {
                 res = nd_strcat_s(Buffer, BufferSize, "REPNZ ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
         }
 
         if (Instrux->IsXreleaseEnabled)
         {
             res = nd_strcat_s(Buffer, BufferSize, "XRELEASE ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         else if (Instrux->IsXacquireEnabled)
         {
             res = nd_strcat_s(Buffer, BufferSize, "XACQUIRE ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
     }
 
@@ -266,7 +266,7 @@ NdToText(
         if (ND_LOCK_SUPPORT(Instrux))
         {
             res = nd_strcat_s(Buffer, BufferSize, "LOCK ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
     }
 
@@ -275,7 +275,7 @@ NdToText(
         if (ND_BND_SUPPORT(Instrux))
         {
             res = nd_strcat_s(Buffer, BufferSize, "BND ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
     }
 
@@ -285,17 +285,17 @@ NdToText(
         {
         case ND_PREFIX_G2_BR_TAKEN:
             res = nd_strcat_s(Buffer, BufferSize, "BHT ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             break;
 
         case ND_PREFIX_G2_BR_NOT_TAKEN:
             res = nd_strcat_s(Buffer, BufferSize, "BHNT ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             break;
 
         case ND_PREFIX_G2_BR_ALT:
             res = nd_strcat_s(Buffer, BufferSize, "BHALT ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             break;
 
         default:
@@ -308,19 +308,19 @@ NdToText(
         if (!Instrux->IsCetTracked)
         {
             res = nd_strcat_s(Buffer, BufferSize, "DNT ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
     }
 
     // Store the mnemonic.
     res = nd_strcat_s(Buffer, BufferSize, Instrux->Mnemonic);
-    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
 
     // Store condition code, if any.
     if (ND_HAS_SSE_CONDITION(Instrux))
     {
         res = nd_strcat_s(Buffer, BufferSize, gConditionCodes[Instrux->SseCondition]);
-        RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+        RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
     }
 
     // If there are no explicit operands, we can leave.
@@ -358,7 +358,7 @@ NdToText(
         // Store alignment.
         if (!alignmentStored)
         {
-            size_t idx = 0;
+            ND_SIZET idx = 0;
 
             while ((idx < BufferSize) && (Buffer[idx]))
             {
@@ -377,14 +377,14 @@ NdToText(
 
             Buffer[idx] = 0;
 
-            alignmentStored = true;
+            alignmentStored = ND_TRUE;
         }
 
         // Store the comma, if this isn't the first operand.
         if (opsStored > 0)
         {
             res = nd_strcat_s(Buffer, BufferSize, ", ");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
 
         opsStored++;
@@ -409,31 +409,31 @@ NdToText(
                     if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex)
                     {
                         res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Register.Reg]);
-                        RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                        RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     }
                     else
                     {
                         res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Register.Reg]);
-                        RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                        RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     }
                     break;
 
                 case ND_SIZE_16BIT:
                     // 16 bit register.
                     res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
 
                 case ND_SIZE_32BIT:
                     // 32 bit register.
                     res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
 
                 case ND_SIZE_64BIT:
                     // 64 bit register.
                     res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
 
                 default:
@@ -450,7 +450,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -462,7 +462,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegFpu[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -474,7 +474,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegMmx[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -489,15 +489,15 @@ NdToText(
                 {
                 case ND_SIZE_128BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_256BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_512BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Register.Reg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 default:
                     return ND_STATUS_INVALID_INSTRUX;
@@ -513,7 +513,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegControl[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -525,7 +525,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegDebug[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -537,7 +537,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegTest[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -550,7 +550,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegBound[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -563,7 +563,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegMask[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -576,7 +576,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, gRegTile[pOp->Info.Register.Reg]);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
             break;
 
@@ -593,7 +593,7 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, temp);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
 
             break;
@@ -612,7 +612,7 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         break;
 
@@ -621,16 +621,16 @@ NdToText(
             switch (pOp->Size)
             {
             case 1:
-                status = NdSprintf(temp, sizeof(temp), "0x%02x", (uint8_t)pOp->Info.Immediate.Imm);
+                status = NdSprintf(temp, sizeof(temp), "0x%02x", (ND_UINT8)pOp->Info.Immediate.Imm);
                 break;
             case 2:
-                status = NdSprintf(temp, sizeof(temp), "0x%04x", (uint16_t)pOp->Info.Immediate.Imm);
+                status = NdSprintf(temp, sizeof(temp), "0x%04x", (ND_UINT16)pOp->Info.Immediate.Imm);
                 break;
             case 4:
-                status = NdSprintf(temp, sizeof(temp), "0x%08x", (uint32_t)pOp->Info.Immediate.Imm);
+                status = NdSprintf(temp, sizeof(temp), "0x%08x", (ND_UINT32)pOp->Info.Immediate.Imm);
                 break;
             case 8:
-                status = NdSprintf(temp, sizeof(temp), "0x%016llx", (uint64_t)pOp->Info.Immediate.Imm);
+                status = NdSprintf(temp, sizeof(temp), "0x%016llx", (ND_UINT64)pOp->Info.Immediate.Imm);
                 break;
             }
             if (!ND_SUCCESS(status))
@@ -639,13 +639,13 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         break;
 
         case ND_OP_OFFS:
         {
-            uint64_t dest = Rip + Instrux->Length + pOp->Info.RelativeOffset.Rel;
+            ND_UINT64 dest = Rip + Instrux->Length + pOp->Info.RelativeOffset.Rel;
 
             // Truncate to the actual word length.
             switch (Instrux->WordLength)
@@ -667,7 +667,7 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         break;
 
@@ -677,15 +677,15 @@ NdToText(
             {
             case 4:
                 status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%04x",
-                    pOp->Info.Address.BaseSeg, (uint16_t)pOp->Info.Address.Offset);
+                    pOp->Info.Address.BaseSeg, (ND_UINT16)pOp->Info.Address.Offset);
                 break;
             case 6:
                 status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%08x",
-                    pOp->Info.Address.BaseSeg, (uint32_t)pOp->Info.Address.Offset);
+                    pOp->Info.Address.BaseSeg, (ND_UINT32)pOp->Info.Address.Offset);
                 break;
             case 10:
                 status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%016llx",
-                    pOp->Info.Address.BaseSeg, (uint64_t)pOp->Info.Address.Offset);
+                    pOp->Info.Address.BaseSeg, (ND_UINT64)pOp->Info.Address.Offset);
                 break;
             default:
                 return ND_STATUS_INVALID_INSTRUX;
@@ -697,7 +697,7 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         break;
 
@@ -710,43 +710,43 @@ NdToText(
             {
             case 1:
                 res = nd_strcat_s(Buffer, BufferSize, "byte ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 2:
                 res = nd_strcat_s(Buffer, BufferSize, "word ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 4:
                 res = nd_strcat_s(Buffer, BufferSize, "dword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 6:
                 res = nd_strcat_s(Buffer, BufferSize, "fword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 8:
                 res = nd_strcat_s(Buffer, BufferSize, "qword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 10:
                 res = nd_strcat_s(Buffer, BufferSize, "tbyte ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 16:
                 res = nd_strcat_s(Buffer, BufferSize, "xmmword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 32:
                 res = nd_strcat_s(Buffer, BufferSize, "ymmword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 48:
                 res = nd_strcat_s(Buffer, BufferSize, "m384 ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             case 64:
                 res = nd_strcat_s(Buffer, BufferSize, "zmmword ptr ");
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 break;
             default:
                 break;
@@ -764,16 +764,16 @@ NdToText(
                     (NDR_GS == pOp->Info.Memory.Seg))
                 {
                     res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Memory.Seg]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
 
                     res = nd_strcat_s(Buffer, BufferSize, ":");
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 }
             }
 
             // Prepend the "["
             res = nd_strcat_s(Buffer, BufferSize, "[");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
 
             // Base, if any.
             if (pOp->Info.Memory.HasBase)
@@ -787,19 +787,19 @@ NdToText(
                 {
                 case ND_SIZE_8BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Base]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_16BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Base]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_32BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Base]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_64BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Base]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 default:
                     return ND_STATUS_INVALID_INSTRUX;
@@ -817,38 +817,38 @@ NdToText(
                 if (pOp->Info.Memory.HasBase)
                 {
                     res = nd_strcat_s(Buffer, BufferSize, "+");
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 }
 
                 switch (pOp->Info.Memory.IndexSize)
                 {
                 case ND_SIZE_8BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_16BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_32BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_64BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_128BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_256BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 case ND_SIZE_512BIT:
                     res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Memory.Index]);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
                 default:
                     return ND_STATUS_INVALID_INSTRUX;
@@ -864,14 +864,14 @@ NdToText(
                     }
 
                     res = nd_strcat_s(Buffer, BufferSize, temp);
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 }
             }
 
             // Handle displacement.
             if (pOp->Info.Memory.HasDisp)
             {
-                uint64_t normDisp, disp;
+                ND_UINT64 normDisp, disp;
 
                 disp = pOp->Info.Memory.Disp;
 
@@ -900,12 +900,12 @@ NdToText(
                         break;
                     }
 
-                    // Handle compressed displacement. It is fine to cast the normDisp to uint32_t, as the
-                    // compressed displacement only works with uint8_t displacements. Also, in this phase,
+                    // Handle compressed displacement. It is fine to cast the normDisp to ND_UINT32, as the
+                    // compressed displacement only works with ND_UINT8 displacements. Also, in this phase,
                     // the normDisp is converted to a positive quantity, so no sign-extension is needed.
                     if (pOp->Info.Memory.HasCompDisp)
                     {
-                        normDisp = (uint64_t)(uint32_t)normDisp * pOp->Info.Memory.CompDispSize;
+                        normDisp = (ND_UINT64)(ND_UINT32)normDisp * pOp->Info.Memory.CompDispSize;
                     }
                 }
 
@@ -914,12 +914,12 @@ NdToText(
                 if (pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex)
                 {
                     res = nd_strcat_s(Buffer, BufferSize, Instrux->SignDisp ? "-" : "+");
-                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
                 }
 
                 if (pOp->Info.Memory.IsRipRel)
                 {
-                    uint64_t target = disp + Rip + Instrux->Length;
+                    ND_UINT64 target = disp + Rip + Instrux->Length;
 
                     if (Instrux->AddrMode == ND_ADDR_32)
                     {
@@ -930,7 +930,7 @@ NdToText(
                 }
                 else
                 {
-                    uint8_t trimSize;
+                    ND_UINT8 trimSize;
 
                     trimSize = (Instrux->AddrMode == ND_ADDR_16) ? 2 : ((Instrux->AddrMode == ND_ADDR_32) ? 4 : 8);
 
@@ -945,12 +945,12 @@ NdToText(
                 }
 
                 res = nd_strcat_s(Buffer, BufferSize, temp);
-                RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
             }
 
             // And the ending "]"
             res = nd_strcat_s(Buffer, BufferSize, "]");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
         break;
 
@@ -968,7 +968,7 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
 
         // Handle masking.
@@ -986,14 +986,14 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
 
         // Handle zeroing. Note that zeroing without masking is ignored.
         if (pOp->Decorator.HasZero && pOp->Decorator.HasMask)
         {
             res = nd_strcat_s(Buffer, BufferSize, "{z}");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
 
         // Append Suppress All Exceptions decorator.
@@ -1001,7 +1001,7 @@ NdToText(
         {
             // ER implies SAE, so if we have ER, we will list that.
             res = nd_strcat_s(Buffer, BufferSize, ", {sae}");
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
 
         // Append Embedded Rounding decorator.
@@ -1019,7 +1019,7 @@ NdToText(
             }
 
             res = nd_strcat_s(Buffer, BufferSize, temp);
-            RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+            RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW);
         }
     }
 
@@ -1029,18 +1029,18 @@ NdToText(
 NDSTATUS
 NdToText(
     const INSTRUX *Instrux,
-    uint64_t Rip,
-    uint32_t BufferSize,
+    ND_UINT64 Rip,
+    ND_UINT32 BufferSize,
     char *Buffer
     )
 {
     UNREFERENCED_PARAMETER(Instrux);
     UNREFERENCED_PARAMETER(Rip);
 
-    // At least make sure the buffer is NULL-terminated so integrators can use NdToText without checking if the
+    // At least make sure the buffer is ND_NULL-terminated so integrators can use NdToText without checking if the
     // BDDISASM_NO_FORMAT macro is defined. This makes switching between versions with formatting and versions without
     // formatting easier.
-    if (Buffer != NULL && BufferSize >= 1)
+    if (Buffer != ND_NULL && BufferSize >= 1)
     {
         *Buffer = '\0';
     }
diff --git a/bddisasm/bdhelpers.c b/bddisasm/bdhelpers.c
index 449a46a..2ec0565 100644
--- a/bddisasm/bdhelpers.c
+++ b/bddisasm/bdhelpers.c
@@ -5,7 +5,7 @@
 //
 // NdIsInstruxRipRelative
 //
-bool
+ND_BOOL
 NdIsInstruxRipRelative(
     const INSTRUX *Instrux
     )
@@ -13,9 +13,9 @@ NdIsInstruxRipRelative(
 // Provided for backwards compatibility with existing code that uses disasm 1.0
 //
 {
-    if (NULL == Instrux)
+    if (ND_NULL == Instrux)
     {
-        return false;
+        return ND_FALSE;
     }
     else
     {
@@ -33,20 +33,20 @@ NdGetFullAccessMap(
     ND_ACCESS_MAP *AccessMap
     )
 {
-    uint32_t i;
+    ND_UINT32 i;
     const ND_OPERAND *pOp;
 
     // pre-init
     i = 0;
-    pOp = NULL;
+    pOp = (const ND_OPERAND *)ND_NULL;
 
     // validate
-    if (NULL == Instrux)
+    if (ND_NULL == Instrux)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == AccessMap)
+    if (ND_NULL == AccessMap)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -96,7 +96,7 @@ NdGetFullAccessMap(
             {
             case ND_REG_GPR:
                 {
-                    uint32_t k;
+                    ND_UINT32 k;
 
                     for (k = 0; k < pOp->Info.Register.Count; k++)
                     {
@@ -122,7 +122,7 @@ NdGetFullAccessMap(
                 break;
             case ND_REG_SSE:
                 {
-                    uint32_t k;
+                    ND_UINT32 k;
 
                     for (k = 0; k < pOp->Info.Register.Count; k++)
                     {
@@ -175,7 +175,7 @@ NdGetFullAccessMap(
         }
         else if (ND_OP_BANK == Instrux->Operands[i].Type)
         {
-            uint8_t j;
+            ND_UINT8 j;
 
             // Bank registers access. This needs special handling. Note that LOADALL/LOADALLD is not supported, as
             // it is too old and it's not valid since the good old 486.
@@ -225,12 +225,12 @@ NdGetOperandRlut(
     ND_OPERAND_RLUT *Rlut
     )
 {
-    if (NULL == Instrux)
+    if (ND_NULL == Instrux)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
 
-    if (NULL == Rlut)
+    if (ND_NULL == Rlut)
     {
         return ND_STATUS_INVALID_PARAMETER;
     }
@@ -238,16 +238,16 @@ NdGetOperandRlut(
     // Initialize the RLUT. 
     nd_memset(Rlut, 0, sizeof(*Rlut));
 
-    for (uint8_t i = 0; i < Instrux->OperandsCount; i++)
+    for (ND_UINT8 i = 0; i < Instrux->OperandsCount; i++)
     {
         if (!!(Instrux->Operands[i].Access.Access & ND_ACCESS_ANY_WRITE))
         {
             // We only care about the first 2 destination operands.
-            if (Rlut->Dst1 == NULL)
+            if (Rlut->Dst1 == ND_NULL)
             {
                 Rlut->Dst1 = (PND_OPERAND)&Instrux->Operands[i];
             }
-            else if (Rlut->Dst2 == NULL)
+            else if (Rlut->Dst2 == ND_NULL)
             {
                 Rlut->Dst2 = (PND_OPERAND)&Instrux->Operands[i];
             }
@@ -256,19 +256,19 @@ NdGetOperandRlut(
         if (!!(Instrux->Operands[i].Access.Access & ND_ACCESS_ANY_READ))
         {
             // We only care about the first 4 source operands.
-            if (Rlut->Src1 == NULL)
+            if (Rlut->Src1 == ND_NULL)
             {
                 Rlut->Src1 = (PND_OPERAND)&Instrux->Operands[i];
             }
-            else if (Rlut->Src2 == NULL)
+            else if (Rlut->Src2 == ND_NULL)
             {
                 Rlut->Src2 = (PND_OPERAND)&Instrux->Operands[i];
             }
-            else if (Rlut->Src3 == NULL)
+            else if (Rlut->Src3 == ND_NULL)
             {
                 Rlut->Src3 = (PND_OPERAND)&Instrux->Operands[i];
             }
-            else if (Rlut->Src4 == NULL)
+            else if (Rlut->Src4 == ND_NULL)
             {
                 Rlut->Src4 = (PND_OPERAND)&Instrux->Operands[i];
             }
@@ -277,11 +277,11 @@ NdGetOperandRlut(
         if (Instrux->Operands[i].Type == ND_OP_MEM)
         {
             // We only care about the first 2 memory operands.
-            if (Rlut->Mem1 == NULL)
+            if (Rlut->Mem1 == ND_NULL)
             {
                 Rlut->Mem1 = (PND_OPERAND)&Instrux->Operands[i];
             }
-            else if (Rlut->Mem2 == NULL)
+            else if (Rlut->Mem2 == ND_NULL)
             {
                 Rlut->Mem2 = (PND_OPERAND)&Instrux->Operands[i];
             }
diff --git a/bddisasm/crt.c b/bddisasm/crt.c
index cb2272d..2a07d7b 100644
--- a/bddisasm/crt.c
+++ b/bddisasm/crt.c
@@ -10,12 +10,12 @@
 char *
 nd_strcat_s(
     char *dst,
-    size_t dst_size,
+    ND_SIZET dst_size,
     const char *src
     )
 {
     char *p;
-    size_t available;
+    ND_SIZET available;
 
     p = dst;
     available = dst_size;
@@ -28,7 +28,7 @@ nd_strcat_s(
     if (available == 0)
     {
         nd_memzero(dst, dst_size);
-        return NULL;
+        return (char *)ND_NULL;
     }
 
     while ((*p++ = *src++) != 0 && --available > 0);
@@ -36,7 +36,7 @@ nd_strcat_s(
     if (available == 0)
     {
         nd_memzero(dst, dst_size);
-        return NULL;
+        return (char *)ND_NULL;
     }
 
     return dst;
@@ -45,18 +45,18 @@ nd_strcat_s(
 #if !defined(BDDISASM_NO_FORMAT) && defined(BDDISASM_HAS_VSNPRINTF)
 #include <stdio.h>
 
-int nd_vsnprintf_s(char *buffer, size_t sizeOfBuffer, size_t count, const char *format, va_list argptr)
+int nd_vsnprintf_s(char *buffer, ND_SIZET sizeOfBuffer, ND_SIZET count, const char *format, va_list argptr)
 {
     UNREFERENCED_PARAMETER(count);
     return vsnprintf(buffer, sizeOfBuffer, format, argptr);
 }
 #endif // !defined(BDDISASM_NO_FORMAT) && defined(BDDISASM_HAS_VSNPRINTF)
 
-#if !defined(BDDISASM_NO_FORMAT) && defined(BDDISASM_HAS_MEMSET)
+#if defined(BDDISASM_HAS_MEMSET)
 #include <string.h>
 
-void *nd_memset(void *s, int c, size_t n)
+void *nd_memset(void *s, int c, ND_SIZET n)
 {
     return memset(s, c, n);
 }
-#endif // !defined(BDDISASM_NO_FORMAT) && defined(BDDISASM_HAS_MEMSET)
\ No newline at end of file
+#endif // defined(BDDISASM_HAS_MEMSET)
diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
index 5b41a93..2e958dc 100644
--- a/bddisasm/include/instructions.h
+++ b/bddisasm/include/instructions.h
@@ -44711,7 +44711,7 @@ const ND_INSTRUCTION gInstructions[2701] =
     {
         ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1659, 
         0, 
-        ND_MOD_ANY, 
+        ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
         0,
@@ -44727,7 +44727,7 @@ const ND_INSTRUCTION gInstructions[2701] =
     {
         ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1660, 
         0, 
-        ND_MOD_ANY, 
+        ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
         0,
@@ -44743,7 +44743,7 @@ const ND_INSTRUCTION gInstructions[2701] =
     {
         ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1661, 
         0, 
-        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
+        ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
         0,
         0,
diff --git a/bddisasm/include/nd_crt.h b/bddisasm/include/nd_crt.h
index 6ed5015..774aedc 100644
--- a/bddisasm/include/nd_crt.h
+++ b/bddisasm/include/nd_crt.h
@@ -11,54 +11,8 @@
 #define UNREFERENCED_PARAMETER(P)       ((void)(P))
 #endif
 
-#if defined(_MSC_VER)
-#include <vadefs.h>
-
-# ifndef _ADDRESSOF
-#  ifdef  __cplusplus
-#   define _ADDRESSOF(v)           ( &reinterpret_cast<const char &>(v) )
-#  else
-#   define _ADDRESSOF(v)           ( &(v) )
-#  endif  // __cplusplus
-# endif // !_ADDRESSOF
-
-# ifndef _KERNEL_MODE
-
-#  if defined(AMD64) || defined(WIN64)
-
-#   define _crt_va_start(ap, x)    ( __va_start(&ap, x) )
-#   define _crt_va_arg(ap, t)      ( ( sizeof(t) > sizeof(QWORD) || ( sizeof(t) & (sizeof(t) - 1) ) != 0 ) \
-                                    ? **(t **)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) \
-                                    :  *(t  *)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) )
-#   define _crt_va_end(ap)         ( ap = (va_list)0 )
-
-#  else
-
-// a guess at the proper definitions for other platforms
-
-#   ifndef _INTSIZEOF
-#    define _INTSIZEOF(n)           ( (sizeof(n) + sizeof(int) - 1) & ~(sizeof(int) - 1) )
-#   endif // !_INTSIZEOF
-
-
-#   define _crt_va_start(ap,v)     ( ap = (va_list)_ADDRESSOF(v) + _INTSIZEOF(v) )
-#   define _crt_va_arg(ap,t)       ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
-#   define _crt_va_end(ap)         ( ap = (va_list)0 )
-
-#  endif // AMD64 || WIN64
-
-# define va_start _crt_va_start
-# define va_arg _crt_va_arg
-# define va_end _crt_va_end
-
-#endif // _KERNEL_MODE
-
-#else
-
-# include <stdarg.h>
-
+#if !defined(_MSC_VER)
 # define __forceinline       inline __attribute__((always_inline))
-
 #endif // _MSC_VER
 
 // By default, an integrator is expected to provide nd_vsnprintf_s and nd_strcat_s.
@@ -66,10 +20,12 @@
 // If BDDISASM_NO_FORMAT is defined at compile time these requirements are removed. Instruction formatting will no
 // longer be available in bddisasm and emulation tracing will no longer be available in bdshemu.
 #ifndef BDDISASM_NO_FORMAT
+#include <stdarg.h>
+
 extern int nd_vsnprintf_s(
     char *buffer,
-    size_t sizeOfBuffer,
-    size_t count,
+    ND_SIZET sizeOfBuffer,
+    ND_SIZET count,
     const char *format,
     va_list argptr
     );
@@ -77,13 +33,13 @@ extern int nd_vsnprintf_s(
 char *
 nd_strcat_s(
     char *dst,
-    size_t dst_size,
+    ND_SIZET dst_size,
     const char *src
     );
 #endif // !BDDISASM_NO_FORMAT
 
 // Declared here only. Expecting it to be defined in the integrator.
-extern void *nd_memset(void *s, int c, size_t n);
+extern void *nd_memset(void *s, int c, ND_SIZET n);
 
 #define nd_memzero(Dest, Size)         nd_memset((Dest), 0, (Size))
 
diff --git a/bddisasm/include/prefixes.h b/bddisasm/include/prefixes.h
index 60f5efb..c803535 100644
--- a/bddisasm/include/prefixes.h
+++ b/bddisasm/include/prefixes.h
@@ -10,7 +10,7 @@
 #define ND_PREF_CODE_EX             2
 #define ND_PREF_CODE_REX            3
 
-static const uint8_t gPrefixesMap[256] = 
+static const ND_UINT8 gPrefixesMap[256] = 
 {
 //  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
index ca3876e..868b43c 100644
--- a/bddisasm/include/table_evex.h
+++ b/bddisasm/include/table_evex.h
@@ -12,7 +12,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -20,10 +20,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_9a_03_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -32,7 +32,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -61,9 +61,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9a_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_9a_03_modrmmod,
     }
 };
@@ -79,7 +79,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -88,7 +88,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -117,9 +117,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9b_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_9b_03_modrmmod,
     }
 };
@@ -135,7 +135,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -143,10 +143,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_aa_03_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -155,7 +155,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -184,9 +184,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_aa_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_aa_03_modrmmod,
     }
 };
@@ -202,7 +202,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -211,7 +211,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -240,9 +240,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ab_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_ab_03_modrmmod,
     }
 };
@@ -257,10 +257,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_de_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -274,10 +274,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_df_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -291,10 +291,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_dc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -308,10 +308,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_dd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -340,10 +340,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_65_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -372,10 +372,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_19_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -405,7 +405,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_1a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_1a_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -413,10 +413,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -445,10 +445,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_1b_01_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -457,7 +457,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_1b_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_1b_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -465,10 +465,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -497,10 +497,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_59_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -530,7 +530,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_5a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_5a_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -538,10 +538,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_5a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -570,10 +570,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_5b_01_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -582,7 +582,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_5b_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_5b_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -590,10 +590,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_5b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -608,7 +608,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_18_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -616,10 +616,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_18_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -648,10 +648,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_8a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -666,7 +666,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_72_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -681,7 +681,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_72_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -695,7 +695,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_72_01_01_leaf,
     }
 };
@@ -704,7 +704,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_72_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_72_02_w,
         /* 03 */ (const void *)&gEvexTable_root_02_72_03_w,
@@ -722,7 +722,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_13_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -737,7 +737,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_13_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -745,10 +745,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_13_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_13_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -763,7 +763,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_52_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -778,7 +778,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -786,10 +786,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_52_03_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_52_03_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -798,7 +798,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -813,7 +813,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_52_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -821,7 +821,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_52_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_52_02_w,
         /* 03 */ (const void *)&gEvexTable_root_02_52_03_modrmmod,
@@ -853,10 +853,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c8_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c8_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -864,10 +864,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c8_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -896,10 +896,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_88_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -928,10 +928,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_98_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -960,10 +960,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_99_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -992,10 +992,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1024,10 +1024,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1056,10 +1056,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1088,10 +1088,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1120,10 +1120,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_96_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1152,10 +1152,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1184,10 +1184,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1216,10 +1216,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ba_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1248,10 +1248,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_bb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1280,10 +1280,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_97_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1312,10 +1312,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1344,10 +1344,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1376,10 +1376,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1408,10 +1408,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1440,10 +1440,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ac_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1472,10 +1472,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ad_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1504,10 +1504,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_bc_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1536,10 +1536,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_bd_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1568,10 +1568,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1600,10 +1600,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_9f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1632,10 +1632,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ae_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1664,10 +1664,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_af_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1696,10 +1696,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_be_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1728,10 +1728,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_bf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1761,7 +1761,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_92_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_92_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1769,10 +1769,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_92_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1801,10 +1801,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1833,10 +1833,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1865,10 +1865,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1897,10 +1897,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_06_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1908,14 +1908,14 @@ const ND_TABLE_MODRM_REG gEvexTable_root_02_c6_01_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_l,
         /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_l,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_l,
         /* 06 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_l,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -1924,7 +1924,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_c6_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_modrmreg,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1932,10 +1932,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c6_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1964,10 +1964,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1996,10 +1996,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2028,10 +2028,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2060,10 +2060,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_06_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2071,14 +2071,14 @@ const ND_TABLE_MODRM_REG gEvexTable_root_02_c7_01_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_l,
         /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_l,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_l,
         /* 06 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_l,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -2087,7 +2087,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_c7_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_modrmreg,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2095,10 +2095,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c7_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2128,7 +2128,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_93_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_93_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2136,10 +2136,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_93_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2168,10 +2168,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_42_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2200,10 +2200,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_43_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2218,7 +2218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_cf_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2226,10 +2226,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_cf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2244,7 +2244,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2253,7 +2253,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2267,7 +2267,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_01_leaf,
     }
 };
@@ -2276,7 +2276,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_w,
     }
 };
@@ -2285,10 +2285,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2a_01_modrmmod,
         /* 02 */ (const void *)&gEvexTable_root_02_2a_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2317,9 +2317,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_68_03_w,
     }
 };
@@ -2335,7 +2335,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2343,10 +2343,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_53_03_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_53_03_mem_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2355,7 +2355,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2370,7 +2370,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_53_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2378,9 +2378,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_53_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_02_53_03_modrmmod,
     }
 };
@@ -2395,10 +2395,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2413,7 +2413,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_1e_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2421,10 +2421,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2438,7 +2438,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1f_01_01_leaf,
     }
 };
@@ -2447,10 +2447,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2464,10 +2464,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_1d_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2482,7 +2482,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_2b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2490,10 +2490,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2522,10 +2522,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_66_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2554,10 +2554,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_64_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2572,7 +2572,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_78_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2580,10 +2580,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_78_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2598,7 +2598,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_7a_01_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2606,7 +2606,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_7a_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7a_01_reg_w,
     }
 };
@@ -2615,10 +2615,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2633,7 +2633,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_58_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2641,10 +2641,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_58_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2673,7 +2673,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_7c_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7c_01_reg_wi,
     }
 };
@@ -2682,10 +2682,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7c_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2700,7 +2700,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_3a_02_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2708,7 +2708,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3a_02_reg_w,
     }
 };
@@ -2723,10 +2723,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3a_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_3a_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2741,7 +2741,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_79_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2749,10 +2749,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_79_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2767,7 +2767,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_7b_01_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2775,7 +2775,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_7b_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7b_01_reg_w,
     }
 };
@@ -2784,10 +2784,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2801,7 +2801,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_29_01_01_leaf,
     }
 };
@@ -2831,7 +2831,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_29_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_29_02_reg_w,
     }
 };
@@ -2840,10 +2840,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_29_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_29_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2857,7 +2857,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_37_01_01_leaf,
     }
 };
@@ -2866,10 +2866,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_37_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2898,10 +2898,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_63_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2930,10 +2930,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_8b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2962,10 +2962,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_c4_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2980,7 +2980,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_50_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2988,10 +2988,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_50_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3006,7 +3006,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_51_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3014,10 +3014,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_51_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3046,10 +3046,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_8d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3078,10 +3078,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_36_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3110,10 +3110,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_75_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3142,10 +3142,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_76_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3174,10 +3174,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_77_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3191,7 +3191,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_0d_01_01_leaf,
     }
 };
@@ -3200,10 +3200,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_0d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3218,7 +3218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_0c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3226,10 +3226,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_0c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3279,10 +3279,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_16_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_16_01_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_16_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3290,10 +3290,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_16_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3322,10 +3322,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3354,10 +3354,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3386,10 +3386,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_7f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3418,10 +3418,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_62_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3450,10 +3450,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_89_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3483,7 +3483,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_90_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_90_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3491,10 +3491,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_90_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3524,7 +3524,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_91_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_91_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3532,10 +3532,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_91_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3564,10 +3564,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_44_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3581,7 +3581,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b5_01_01_leaf,
     }
 };
@@ -3590,10 +3590,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b5_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3607,7 +3607,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b4_01_01_leaf,
     }
 };
@@ -3616,10 +3616,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_b4_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3633,10 +3633,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_04_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3650,10 +3650,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3682,10 +3682,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3714,10 +3714,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3731,10 +3731,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3e_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3769,7 +3769,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_38_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_38_02_reg_w,
     }
 };
@@ -3778,10 +3778,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_38_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_38_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3831,7 +3831,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_39_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_39_02_reg_w,
     }
 };
@@ -3840,10 +3840,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_39_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_39_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3872,10 +3872,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_3b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3890,7 +3890,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_31_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3904,10 +3904,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_31_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_31_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3922,7 +3922,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_33_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3936,10 +3936,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_33_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_33_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3968,7 +3968,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_28_02_reg_w,
     }
 };
@@ -3983,7 +3983,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_28_01_01_leaf,
     }
 };
@@ -3992,10 +3992,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_28_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_28_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4010,7 +4010,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_32_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4024,10 +4024,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_32_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_32_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4042,7 +4042,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_35_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4057,7 +4057,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_35_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4065,10 +4065,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_35_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_35_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4083,7 +4083,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_34_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4097,10 +4097,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_34_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_34_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4115,7 +4115,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_21_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4129,10 +4129,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_21_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_21_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4147,7 +4147,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_23_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4161,10 +4161,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_23_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_23_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4179,7 +4179,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_22_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4193,10 +4193,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_22_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_22_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4211,7 +4211,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_25_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4226,7 +4226,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_25_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4234,10 +4234,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_25_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_25_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4252,7 +4252,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_24_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4266,10 +4266,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_24_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_24_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4284,7 +4284,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_20_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4298,10 +4298,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_20_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_20_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4316,7 +4316,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_11_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4330,7 +4330,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_11_01_01_leaf,
     }
 };
@@ -4339,10 +4339,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_11_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_11_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4357,7 +4357,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_12_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4371,7 +4371,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_12_01_01_leaf,
     }
 };
@@ -4380,10 +4380,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_12_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_12_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4398,7 +4398,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_15_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4427,10 +4427,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_15_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_15_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4445,7 +4445,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_14_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4474,10 +4474,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_14_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_14_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4492,7 +4492,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_10_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4506,7 +4506,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_10_01_01_leaf,
     }
 };
@@ -4515,10 +4515,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_10_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_10_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4533,7 +4533,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_30_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4547,10 +4547,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_30_01_leaf,
         /* 02 */ (const void *)&gEvexTable_root_02_30_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4564,10 +4564,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_0b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4596,10 +4596,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_40_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4613,7 +4613,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_83_01_01_leaf,
     }
 };
@@ -4622,10 +4622,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_83_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4654,10 +4654,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_54_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4686,10 +4686,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_55_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4719,7 +4719,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_a0_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_a0_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4727,10 +4727,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a0_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4760,7 +4760,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_a1_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_a1_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4768,10 +4768,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a1_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4800,10 +4800,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_71_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4817,7 +4817,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_70_01_01_leaf,
     }
 };
@@ -4826,10 +4826,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_70_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4858,10 +4858,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_73_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4875,10 +4875,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_00_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4893,7 +4893,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_8f_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4901,10 +4901,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_8f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4933,10 +4933,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_47_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4965,10 +4965,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_46_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4997,10 +4997,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_45_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5050,10 +5050,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_26_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_26_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5103,10 +5103,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_27_01_w,
         /* 02 */ (const void *)&gEvexTable_root_02_27_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5135,10 +5135,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_4c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5167,10 +5167,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_4d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5199,10 +5199,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_ca_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_ca_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5210,10 +5210,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_ca_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5242,10 +5242,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_cb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5274,10 +5274,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_4e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5306,10 +5306,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_4f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5338,10 +5338,10 @@ const ND_TABLE_VEX_L gEvexTable_root_02_cc_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_02_cc_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5349,10 +5349,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_cc_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5381,10 +5381,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_cd_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5413,10 +5413,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5445,10 +5445,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_2d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5478,7 +5478,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_a2_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_a2_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5486,10 +5486,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a2_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5519,7 +5519,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_a3_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_a3_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5527,10 +5527,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_02_a3_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5539,21 +5539,21 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
     ND_ILUT_OPCODE,
     { 
         /* 00 */ (const void *)&gEvexTable_root_02_00_pp,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gEvexTable_root_02_04_pp,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
         /* 0b */ (const void *)&gEvexTable_root_02_0b_pp,
         /* 0c */ (const void *)&gEvexTable_root_02_0c_pp,
         /* 0d */ (const void *)&gEvexTable_root_02_0d_pp,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gEvexTable_root_02_10_pp,
         /* 11 */ (const void *)&gEvexTable_root_02_11_pp,
         /* 12 */ (const void *)&gEvexTable_root_02_12_pp,
@@ -5561,7 +5561,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* 14 */ (const void *)&gEvexTable_root_02_14_pp,
         /* 15 */ (const void *)&gEvexTable_root_02_15_pp,
         /* 16 */ (const void *)&gEvexTable_root_02_16_pp,
-        /* 17 */ NULL,
+        /* 17 */ ND_NULL,
         /* 18 */ (const void *)&gEvexTable_root_02_18_pp,
         /* 19 */ (const void *)&gEvexTable_root_02_19_pp,
         /* 1a */ (const void *)&gEvexTable_root_02_1a_pp,
@@ -5584,8 +5584,8 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* 2b */ (const void *)&gEvexTable_root_02_2b_pp,
         /* 2c */ (const void *)&gEvexTable_root_02_2c_pp,
         /* 2d */ (const void *)&gEvexTable_root_02_2d_pp,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
         /* 30 */ (const void *)&gEvexTable_root_02_30_pp,
         /* 31 */ (const void *)&gEvexTable_root_02_31_pp,
         /* 32 */ (const void *)&gEvexTable_root_02_32_pp,
@@ -5603,17 +5603,17 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* 3e */ (const void *)&gEvexTable_root_02_3e_pp,
         /* 3f */ (const void *)&gEvexTable_root_02_3f_pp,
         /* 40 */ (const void *)&gEvexTable_root_02_40_pp,
-        /* 41 */ NULL,
+        /* 41 */ ND_NULL,
         /* 42 */ (const void *)&gEvexTable_root_02_42_pp,
         /* 43 */ (const void *)&gEvexTable_root_02_43_pp,
         /* 44 */ (const void *)&gEvexTable_root_02_44_pp,
         /* 45 */ (const void *)&gEvexTable_root_02_45_pp,
         /* 46 */ (const void *)&gEvexTable_root_02_46_pp,
         /* 47 */ (const void *)&gEvexTable_root_02_47_pp,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
         /* 4c */ (const void *)&gEvexTable_root_02_4c_pp,
         /* 4d */ (const void *)&gEvexTable_root_02_4d_pp,
         /* 4e */ (const void *)&gEvexTable_root_02_4e_pp,
@@ -5624,37 +5624,37 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* 53 */ (const void *)&gEvexTable_root_02_53_pp,
         /* 54 */ (const void *)&gEvexTable_root_02_54_pp,
         /* 55 */ (const void *)&gEvexTable_root_02_55_pp,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
         /* 58 */ (const void *)&gEvexTable_root_02_58_pp,
         /* 59 */ (const void *)&gEvexTable_root_02_59_pp,
         /* 5a */ (const void *)&gEvexTable_root_02_5a_pp,
         /* 5b */ (const void *)&gEvexTable_root_02_5b_pp,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
         /* 62 */ (const void *)&gEvexTable_root_02_62_pp,
         /* 63 */ (const void *)&gEvexTable_root_02_63_pp,
         /* 64 */ (const void *)&gEvexTable_root_02_64_pp,
         /* 65 */ (const void *)&gEvexTable_root_02_65_pp,
         /* 66 */ (const void *)&gEvexTable_root_02_66_pp,
-        /* 67 */ NULL,
+        /* 67 */ ND_NULL,
         /* 68 */ (const void *)&gEvexTable_root_02_68_pp,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
         /* 70 */ (const void *)&gEvexTable_root_02_70_pp,
         /* 71 */ (const void *)&gEvexTable_root_02_71_pp,
         /* 72 */ (const void *)&gEvexTable_root_02_72_pp,
         /* 73 */ (const void *)&gEvexTable_root_02_73_pp,
-        /* 74 */ NULL,
+        /* 74 */ ND_NULL,
         /* 75 */ (const void *)&gEvexTable_root_02_75_pp,
         /* 76 */ (const void *)&gEvexTable_root_02_76_pp,
         /* 77 */ (const void *)&gEvexTable_root_02_77_pp,
@@ -5666,28 +5666,28 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* 7d */ (const void *)&gEvexTable_root_02_7d_pp,
         /* 7e */ (const void *)&gEvexTable_root_02_7e_pp,
         /* 7f */ (const void *)&gEvexTable_root_02_7f_pp,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
         /* 83 */ (const void *)&gEvexTable_root_02_83_pp,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
         /* 88 */ (const void *)&gEvexTable_root_02_88_pp,
         /* 89 */ (const void *)&gEvexTable_root_02_89_pp,
         /* 8a */ (const void *)&gEvexTable_root_02_8a_pp,
         /* 8b */ (const void *)&gEvexTable_root_02_8b_pp,
-        /* 8c */ NULL,
+        /* 8c */ ND_NULL,
         /* 8d */ (const void *)&gEvexTable_root_02_8d_pp,
-        /* 8e */ NULL,
+        /* 8e */ ND_NULL,
         /* 8f */ (const void *)&gEvexTable_root_02_8f_pp,
         /* 90 */ (const void *)&gEvexTable_root_02_90_pp,
         /* 91 */ (const void *)&gEvexTable_root_02_91_pp,
         /* 92 */ (const void *)&gEvexTable_root_02_92_pp,
         /* 93 */ (const void *)&gEvexTable_root_02_93_pp,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
         /* 96 */ (const void *)&gEvexTable_root_02_96_pp,
         /* 97 */ (const void *)&gEvexTable_root_02_97_pp,
         /* 98 */ (const void *)&gEvexTable_root_02_98_pp,
@@ -5702,8 +5702,8 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* a1 */ (const void *)&gEvexTable_root_02_a1_pp,
         /* a2 */ (const void *)&gEvexTable_root_02_a2_pp,
         /* a3 */ (const void *)&gEvexTable_root_02_a3_pp,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
         /* a6 */ (const void *)&gEvexTable_root_02_a6_pp,
         /* a7 */ (const void *)&gEvexTable_root_02_a7_pp,
         /* a8 */ (const void *)&gEvexTable_root_02_a8_pp,
@@ -5714,10 +5714,10 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* ad */ (const void *)&gEvexTable_root_02_ad_pp,
         /* ae */ (const void *)&gEvexTable_root_02_ae_pp,
         /* af */ (const void *)&gEvexTable_root_02_af_pp,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
         /* b4 */ (const void *)&gEvexTable_root_02_b4_pp,
         /* b5 */ (const void *)&gEvexTable_root_02_b5_pp,
         /* b6 */ (const void *)&gEvexTable_root_02_b6_pp,
@@ -5730,70 +5730,70 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
         /* bd */ (const void *)&gEvexTable_root_02_bd_pp,
         /* be */ (const void *)&gEvexTable_root_02_be_pp,
         /* bf */ (const void *)&gEvexTable_root_02_bf_pp,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
         /* c4 */ (const void *)&gEvexTable_root_02_c4_pp,
-        /* c5 */ NULL,
+        /* c5 */ ND_NULL,
         /* c6 */ (const void *)&gEvexTable_root_02_c6_pp,
         /* c7 */ (const void *)&gEvexTable_root_02_c7_pp,
         /* c8 */ (const void *)&gEvexTable_root_02_c8_pp,
-        /* c9 */ NULL,
+        /* c9 */ ND_NULL,
         /* ca */ (const void *)&gEvexTable_root_02_ca_pp,
         /* cb */ (const void *)&gEvexTable_root_02_cb_pp,
         /* cc */ (const void *)&gEvexTable_root_02_cc_pp,
         /* cd */ (const void *)&gEvexTable_root_02_cd_pp,
-        /* ce */ NULL,
+        /* ce */ ND_NULL,
         /* cf */ (const void *)&gEvexTable_root_02_cf_pp,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
         /* dc */ (const void *)&gEvexTable_root_02_dc_pp,
         /* dd */ (const void *)&gEvexTable_root_02_dd_pp,
         /* de */ (const void *)&gEvexTable_root_02_de_pp,
         /* df */ (const void *)&gEvexTable_root_02_df_pp,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -5807,7 +5807,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_58_01_01_leaf,
     }
 };
@@ -5823,7 +5823,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_58_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5837,7 +5837,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_58_03_01_leaf,
     }
 };
@@ -5853,7 +5853,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_58_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5878,7 +5878,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_55_01_01_leaf,
     }
 };
@@ -5894,7 +5894,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_55_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5904,8 +5904,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_55_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_55_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5919,7 +5919,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_54_01_01_leaf,
     }
 };
@@ -5935,7 +5935,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_54_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5945,8 +5945,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_54_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_54_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5960,7 +5960,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c2_01_01_leaf,
     }
 };
@@ -5976,7 +5976,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c2_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5990,7 +5990,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c2_03_01_leaf,
     }
 };
@@ -6006,7 +6006,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c2_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6031,7 +6031,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_2f_01_01_leaf,
     }
 };
@@ -6047,7 +6047,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2f_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6057,8 +6057,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2f_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_2f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6093,7 +6093,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e6_03_01_leaf,
     }
 };
@@ -6108,7 +6108,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e6_01_01_leaf,
     }
 };
@@ -6117,7 +6117,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e6_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_e6_02_w,
         /* 03 */ (const void *)&gEvexTable_root_01_e6_03_w,
@@ -6156,7 +6156,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6171,7 +6171,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5b_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6182,7 +6182,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp =
         /* 00 */ (const void *)&gEvexTable_root_01_5b_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_5b_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_5b_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6196,7 +6196,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5a_01_01_leaf,
     }
 };
@@ -6212,7 +6212,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5a_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6226,7 +6226,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5a_03_01_leaf,
     }
 };
@@ -6242,7 +6242,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5a_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6309,7 +6309,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_7b_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_7b_02_leaf,
         /* 03 */ (const void *)&gEvexTable_root_01_7b_03_wi,
@@ -6397,8 +6397,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_01_2d_02_leaf,
         /* 03 */ (const void *)&gEvexTable_root_01_2d_03_leaf,
     }
@@ -6435,8 +6435,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_01_2a_02_leaf,
         /* 03 */ (const void *)&gEvexTable_root_01_2a_03_wi,
     }
@@ -6509,7 +6509,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_7a_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_7a_02_w,
         /* 03 */ (const void *)&gEvexTable_root_01_7a_03_w,
@@ -6597,8 +6597,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_01_2c_02_leaf,
         /* 03 */ (const void *)&gEvexTable_root_01_2c_03_leaf,
     }
@@ -6614,7 +6614,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5e_01_01_leaf,
     }
 };
@@ -6630,7 +6630,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5e_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6644,7 +6644,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5e_03_01_leaf,
     }
 };
@@ -6660,7 +6660,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5e_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6685,7 +6685,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5f_01_01_leaf,
     }
 };
@@ -6701,7 +6701,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5f_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6715,7 +6715,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5f_03_01_leaf,
     }
 };
@@ -6731,7 +6731,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5f_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6756,7 +6756,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5d_01_01_leaf,
     }
 };
@@ -6772,7 +6772,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5d_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6786,7 +6786,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5d_03_01_leaf,
     }
 };
@@ -6802,7 +6802,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5d_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6827,7 +6827,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_28_01_01_leaf,
     }
 };
@@ -6843,7 +6843,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_28_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6853,8 +6853,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_28_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_28_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6868,7 +6868,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_29_01_01_leaf,
     }
 };
@@ -6884,7 +6884,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_29_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6894,8 +6894,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_29_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_29_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6925,9 +6925,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_6e_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_6e_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6935,10 +6935,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6e_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6968,9 +6968,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_7e_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6984,7 +6984,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_7e_02_00_01_leaf,
     }
 };
@@ -6994,9 +6994,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_02_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_7e_02_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7004,10 +7004,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_7e_01_l,
         /* 02 */ (const void *)&gEvexTable_root_01_7e_02_l,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7021,7 +7021,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_12_03_00_01_leaf,
     }
 };
@@ -7036,7 +7036,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_01_leaf,
     }
 };
@@ -7051,7 +7051,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_12_03_02_01_leaf,
     }
 };
@@ -7063,7 +7063,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l =
         /* 00 */ (const void *)&gEvexTable_root_01_12_03_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_12_03_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7078,7 +7078,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7087,9 +7087,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7104,7 +7104,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7113,9 +7113,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7138,7 +7138,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_12_01_mem_00_01_leaf,
     }
 };
@@ -7148,9 +7148,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7159,7 +7159,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7174,7 +7174,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_12_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7256,7 +7256,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6f_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_6f_02_w,
         /* 03 */ (const void *)&gEvexTable_root_01_6f_03_w,
@@ -7330,7 +7330,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_7f_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_7f_02_w,
         /* 03 */ (const void *)&gEvexTable_root_01_7f_03_w,
@@ -7347,7 +7347,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_16_01_mem_00_01_leaf,
     }
 };
@@ -7357,9 +7357,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7368,7 +7368,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7383,7 +7383,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7392,9 +7392,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7409,7 +7409,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7418,9 +7418,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7444,7 +7444,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_16_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7455,7 +7455,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp =
         /* 00 */ (const void *)&gEvexTable_root_01_16_00_modrmmod,
         /* 01 */ (const void *)&gEvexTable_root_01_16_01_modrmmod,
         /* 02 */ (const void *)&gEvexTable_root_01_16_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7469,7 +7469,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_17_01_mem_00_01_leaf,
     }
 };
@@ -7479,9 +7479,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_17_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7490,7 +7490,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7505,7 +7505,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7514,9 +7514,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_17_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7525,7 +7525,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7535,8 +7535,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_17_00_modrmmod,
         /* 01 */ (const void *)&gEvexTable_root_01_17_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7550,7 +7550,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_13_01_mem_00_01_leaf,
     }
 };
@@ -7560,9 +7560,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_13_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7571,7 +7571,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7586,7 +7586,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7595,9 +7595,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_13_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7606,7 +7606,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7616,8 +7616,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_13_00_modrmmod,
         /* 01 */ (const void *)&gEvexTable_root_01_13_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7632,7 +7632,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7641,7 +7641,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_e7_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7649,10 +7649,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e7_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7666,7 +7666,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_2b_01_mem_01_leaf,
     }
 };
@@ -7676,7 +7676,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2b_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7691,7 +7691,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7700,7 +7700,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7710,8 +7710,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2b_00_modrmmod,
         /* 01 */ (const void *)&gEvexTable_root_01_2b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7725,7 +7725,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d6_01_00_01_leaf,
     }
 };
@@ -7735,9 +7735,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_d6_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_d6_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7745,10 +7745,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d6_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7762,7 +7762,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_10_03_mem_01_leaf,
     }
 };
@@ -7777,7 +7777,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_10_03_reg_01_leaf,
     }
 };
@@ -7802,7 +7802,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_10_02_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7817,7 +7817,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_10_02_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7840,7 +7840,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_10_01_01_leaf,
     }
 };
@@ -7856,7 +7856,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_10_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7881,7 +7881,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_11_03_mem_01_leaf,
     }
 };
@@ -7896,7 +7896,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_11_03_reg_01_leaf,
     }
 };
@@ -7921,7 +7921,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_11_02_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7936,7 +7936,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_11_02_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7959,7 +7959,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_11_01_01_leaf,
     }
 };
@@ -7975,7 +7975,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_11_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8000,7 +8000,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_59_01_01_leaf,
     }
 };
@@ -8016,7 +8016,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_59_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8030,7 +8030,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_59_03_01_leaf,
     }
 };
@@ -8046,7 +8046,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_59_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8071,7 +8071,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_56_01_01_leaf,
     }
 };
@@ -8087,7 +8087,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_56_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8097,8 +8097,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_56_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_56_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8113,7 +8113,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_6b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8121,10 +8121,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8138,10 +8138,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_63_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8155,10 +8155,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_67_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8172,10 +8172,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8190,7 +8190,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_fe_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8198,10 +8198,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fe_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8215,7 +8215,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d4_01_01_leaf,
     }
 };
@@ -8224,10 +8224,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d4_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8241,10 +8241,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_ec_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8258,10 +8258,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_ed_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8275,10 +8275,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_dc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8292,10 +8292,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_dd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8309,10 +8309,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8341,10 +8341,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_db_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8373,10 +8373,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_df_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8390,10 +8390,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e0_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8407,10 +8407,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e3_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8424,10 +8424,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_74_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8441,10 +8441,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_76_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8458,10 +8458,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_75_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8475,10 +8475,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_64_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8493,7 +8493,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_66_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8501,10 +8501,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_66_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8518,10 +8518,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_65_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8536,9 +8536,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c5_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8546,7 +8546,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_c5_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c5_01_reg_l,
     }
 };
@@ -8555,10 +8555,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c5_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8573,9 +8573,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c4_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8590,9 +8590,9 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c4_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8609,10 +8609,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c4_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8626,10 +8626,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8643,10 +8643,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_ee_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8660,10 +8660,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_de_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8677,10 +8677,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_ea_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8694,10 +8694,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_da_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8711,10 +8711,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e4_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8728,10 +8728,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8745,10 +8745,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8762,7 +8762,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f4_01_01_leaf,
     }
 };
@@ -8771,10 +8771,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f4_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8803,10 +8803,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_eb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8863,7 +8863,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_72_01_06_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8899,7 +8899,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_72_01_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8910,11 +8910,11 @@ const ND_TABLE_MODRM_REG gEvexTable_root_01_72_01_modrmreg =
         /* 00 */ (const void *)&gEvexTable_root_01_72_01_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_72_01_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_72_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gEvexTable_root_01_72_01_04_w,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gEvexTable_root_01_72_01_06_w,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -8922,10 +8922,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_72_01_modrmreg,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8939,10 +8939,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f6_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8957,7 +8957,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_70_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8977,7 +8977,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_70_01_w,
         /* 02 */ (const void *)&gEvexTable_root_01_70_02_leaf,
         /* 03 */ (const void *)&gEvexTable_root_01_70_03_leaf,
@@ -8995,7 +8995,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_f2_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9003,10 +9003,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f2_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9026,7 +9026,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_73_01_06_01_leaf,
     }
 };
@@ -9047,7 +9047,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_73_01_02_01_leaf,
     }
 };
@@ -9056,12 +9056,12 @@ const ND_TABLE_MODRM_REG gEvexTable_root_01_73_01_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_01_73_01_02_w,
         /* 03 */ (const void *)&gEvexTable_root_01_73_01_03_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gEvexTable_root_01_73_01_06_w,
         /* 07 */ (const void *)&gEvexTable_root_01_73_01_07_leaf,
     }
@@ -9071,10 +9071,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_73_01_modrmreg,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9088,7 +9088,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f3_01_01_leaf,
     }
 };
@@ -9097,10 +9097,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f3_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9126,14 +9126,14 @@ const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_01_71_01_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gEvexTable_root_01_71_01_04_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gEvexTable_root_01_71_01_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -9141,10 +9141,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_71_01_modrmreg,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9158,10 +9158,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9190,10 +9190,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e2_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9207,10 +9207,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9225,7 +9225,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_d2_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9233,10 +9233,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d2_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9250,7 +9250,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d3_01_01_leaf,
     }
 };
@@ -9259,10 +9259,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d3_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9276,10 +9276,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9293,10 +9293,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9311,7 +9311,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_fa_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9319,10 +9319,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fa_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9336,7 +9336,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fb_01_01_leaf,
     }
 };
@@ -9345,10 +9345,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_fb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9362,10 +9362,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9379,10 +9379,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_e9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9396,10 +9396,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9413,10 +9413,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_d9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9430,10 +9430,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_f9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9447,10 +9447,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_68_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9465,7 +9465,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_6a_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9473,10 +9473,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9490,7 +9490,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6d_01_01_leaf,
     }
 };
@@ -9499,10 +9499,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9516,10 +9516,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_69_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9533,10 +9533,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_60_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9551,7 +9551,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_62_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9559,10 +9559,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_62_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9576,7 +9576,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6c_01_01_leaf,
     }
 };
@@ -9585,10 +9585,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_6c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9602,10 +9602,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_61_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9634,10 +9634,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_ef_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9651,7 +9651,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_c6_01_01_leaf,
     }
 };
@@ -9667,7 +9667,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c6_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9677,8 +9677,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_c6_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_c6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9692,7 +9692,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_51_01_01_leaf,
     }
 };
@@ -9708,7 +9708,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_51_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9722,7 +9722,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_51_03_01_leaf,
     }
 };
@@ -9738,7 +9738,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_51_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9763,7 +9763,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5c_01_01_leaf,
     }
 };
@@ -9779,7 +9779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5c_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9793,7 +9793,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_5c_03_01_leaf,
     }
 };
@@ -9809,7 +9809,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_5c_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9834,7 +9834,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_2e_01_01_leaf,
     }
 };
@@ -9850,7 +9850,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2e_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9860,8 +9860,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_2e_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_2e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9875,7 +9875,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_15_01_01_leaf,
     }
 };
@@ -9891,7 +9891,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_15_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9901,8 +9901,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_15_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_15_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9916,7 +9916,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_14_01_01_leaf,
     }
 };
@@ -9932,7 +9932,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_14_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9942,8 +9942,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_14_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_14_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9957,7 +9957,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_57_01_01_leaf,
     }
 };
@@ -9973,7 +9973,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_57_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9983,8 +9983,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_57_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_01_57_00_w,
         /* 01 */ (const void *)&gEvexTable_root_01_57_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9992,22 +9992,22 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gEvexTable_root_01_10_pp,
         /* 11 */ (const void *)&gEvexTable_root_01_11_pp,
         /* 12 */ (const void *)&gEvexTable_root_01_12_pp,
@@ -10016,22 +10016,22 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
         /* 15 */ (const void *)&gEvexTable_root_01_15_pp,
         /* 16 */ (const void *)&gEvexTable_root_01_16_pp,
         /* 17 */ (const void *)&gEvexTable_root_01_17_pp,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
         /* 28 */ (const void *)&gEvexTable_root_01_28_pp,
         /* 29 */ (const void *)&gEvexTable_root_01_29_pp,
         /* 2a */ (const void *)&gEvexTable_root_01_2a_pp,
@@ -10040,42 +10040,42 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
         /* 2d */ (const void *)&gEvexTable_root_01_2d_pp,
         /* 2e */ (const void *)&gEvexTable_root_01_2e_pp,
         /* 2f */ (const void *)&gEvexTable_root_01_2f_pp,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
         /* 51 */ (const void *)&gEvexTable_root_01_51_pp,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
         /* 54 */ (const void *)&gEvexTable_root_01_54_pp,
         /* 55 */ (const void *)&gEvexTable_root_01_55_pp,
         /* 56 */ (const void *)&gEvexTable_root_01_56_pp,
@@ -10111,103 +10111,103 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
         /* 74 */ (const void *)&gEvexTable_root_01_74_pp,
         /* 75 */ (const void *)&gEvexTable_root_01_75_pp,
         /* 76 */ (const void *)&gEvexTable_root_01_76_pp,
-        /* 77 */ NULL,
+        /* 77 */ ND_NULL,
         /* 78 */ (const void *)&gEvexTable_root_01_78_pp,
         /* 79 */ (const void *)&gEvexTable_root_01_79_pp,
         /* 7a */ (const void *)&gEvexTable_root_01_7a_pp,
         /* 7b */ (const void *)&gEvexTable_root_01_7b_pp,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
         /* 7e */ (const void *)&gEvexTable_root_01_7e_pp,
         /* 7f */ (const void *)&gEvexTable_root_01_7f_pp,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
         /* c2 */ (const void *)&gEvexTable_root_01_c2_pp,
-        /* c3 */ NULL,
+        /* c3 */ ND_NULL,
         /* c4 */ (const void *)&gEvexTable_root_01_c4_pp,
         /* c5 */ (const void *)&gEvexTable_root_01_c5_pp,
         /* c6 */ (const void *)&gEvexTable_root_01_c6_pp,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
         /* d1 */ (const void *)&gEvexTable_root_01_d1_pp,
         /* d2 */ (const void *)&gEvexTable_root_01_d2_pp,
         /* d3 */ (const void *)&gEvexTable_root_01_d3_pp,
         /* d4 */ (const void *)&gEvexTable_root_01_d4_pp,
         /* d5 */ (const void *)&gEvexTable_root_01_d5_pp,
         /* d6 */ (const void *)&gEvexTable_root_01_d6_pp,
-        /* d7 */ NULL,
+        /* d7 */ ND_NULL,
         /* d8 */ (const void *)&gEvexTable_root_01_d8_pp,
         /* d9 */ (const void *)&gEvexTable_root_01_d9_pp,
         /* da */ (const void *)&gEvexTable_root_01_da_pp,
@@ -10232,14 +10232,14 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
         /* ed */ (const void *)&gEvexTable_root_01_ed_pp,
         /* ee */ (const void *)&gEvexTable_root_01_ee_pp,
         /* ef */ (const void *)&gEvexTable_root_01_ef_pp,
-        /* f0 */ NULL,
+        /* f0 */ ND_NULL,
         /* f1 */ (const void *)&gEvexTable_root_01_f1_pp,
         /* f2 */ (const void *)&gEvexTable_root_01_f2_pp,
         /* f3 */ (const void *)&gEvexTable_root_01_f3_pp,
         /* f4 */ (const void *)&gEvexTable_root_01_f4_pp,
         /* f5 */ (const void *)&gEvexTable_root_01_f5_pp,
         /* f6 */ (const void *)&gEvexTable_root_01_f6_pp,
-        /* f7 */ NULL,
+        /* f7 */ ND_NULL,
         /* f8 */ (const void *)&gEvexTable_root_01_f8_pp,
         /* f9 */ (const void *)&gEvexTable_root_01_f9_pp,
         /* fa */ (const void *)&gEvexTable_root_01_fa_pp,
@@ -10247,7 +10247,7 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
         /* fc */ (const void *)&gEvexTable_root_01_fc_pp,
         /* fd */ (const void *)&gEvexTable_root_01_fd_pp,
         /* fe */ (const void *)&gEvexTable_root_01_fe_pp,
-        /* ff */ NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -10262,7 +10262,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_58_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10277,7 +10277,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_58_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_58_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10286,9 +10286,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_58_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_58_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_58_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10303,7 +10303,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_2f_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_2f_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10312,9 +10312,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2f_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_2f_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10350,7 +10350,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10365,7 +10365,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5b_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10376,7 +10376,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5b_pp =
         /* 00 */ (const void *)&gEvexTable_root_05_5b_00_w,
         /* 01 */ (const void *)&gEvexTable_root_05_5b_01_w,
         /* 02 */ (const void *)&gEvexTable_root_05_5b_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10390,7 +10390,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_5a_01_01_leaf,
     }
 };
@@ -10406,7 +10406,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5a_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10420,7 +10420,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_5a_03_01_leaf,
     }
 };
@@ -10436,7 +10436,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5a_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10462,7 +10462,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10476,10 +10476,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_7b_01_w,
         /* 02 */ (const void *)&gEvexTable_root_05_7b_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10494,7 +10494,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_79_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10509,7 +10509,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_79_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10526,7 +10526,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp =
         /* 00 */ (const void *)&gEvexTable_root_05_79_00_w,
         /* 01 */ (const void *)&gEvexTable_root_05_79_01_w,
         /* 02 */ (const void *)&gEvexTable_root_05_79_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10541,7 +10541,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7d_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10556,7 +10556,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10571,7 +10571,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7d_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10586,7 +10586,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7d_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10612,7 +10612,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_1d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10627,7 +10627,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_1d_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_1d_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10637,8 +10637,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_1d_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_1d_00_w,
         /* 01 */ (const void *)&gEvexTable_root_05_1d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10652,10 +10652,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_2d_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10669,10 +10669,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_2a_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10687,7 +10687,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7a_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10716,9 +10716,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_7a_01_w,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_05_7a_03_w,
     }
 };
@@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_78_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10749,7 +10749,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_78_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10764,7 +10764,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_02_wi =
     ND_ILUT_VEX_WI,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_78_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10775,7 +10775,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_78_pp =
         /* 00 */ (const void *)&gEvexTable_root_05_78_00_w,
         /* 01 */ (const void *)&gEvexTable_root_05_78_01_w,
         /* 02 */ (const void *)&gEvexTable_root_05_78_02_wi,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10790,7 +10790,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7c_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10805,7 +10805,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10815,8 +10815,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7c_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7c_00_w,
         /* 01 */ (const void *)&gEvexTable_root_05_7c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10830,10 +10830,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_2c_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10848,7 +10848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5e_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10863,7 +10863,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5e_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5e_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10872,9 +10872,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5e_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5e_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_5e_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10889,7 +10889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5f_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10904,7 +10904,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5f_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5f_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10913,9 +10913,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5f_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5f_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_5f_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10930,7 +10930,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5d_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10945,7 +10945,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5d_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5d_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10954,9 +10954,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5d_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5d_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_5d_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10971,7 +10971,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_10_02_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10986,7 +10986,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_10_02_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_10_02_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11003,10 +11003,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_10_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_10_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11021,7 +11021,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_11_02_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11036,7 +11036,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_11_02_reg_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_11_02_reg_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11053,10 +11053,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_11_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_11_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11071,9 +11071,9 @@ const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_6e_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11088,9 +11088,9 @@ const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_6e_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11107,10 +11107,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_6e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_6e_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11125,9 +11125,9 @@ const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7e_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11142,9 +11142,9 @@ const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_7e_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11161,10 +11161,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_05_7e_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11179,7 +11179,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_59_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11194,7 +11194,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_59_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_59_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11203,9 +11203,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_59_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_59_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_59_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11220,7 +11220,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_51_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11235,7 +11235,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_51_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_51_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11244,9 +11244,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_51_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_51_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_51_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11261,7 +11261,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5c_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11276,7 +11276,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5c_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5c_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11285,9 +11285,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5c_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_5c_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_05_5c_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11302,7 +11302,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_2e_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_2e_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11311,9 +11311,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2e_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_05_2e_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11321,94 +11321,94 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gEvexTable_root_05_10_pp,
         /* 11 */ (const void *)&gEvexTable_root_05_11_pp,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
         /* 1d */ (const void *)&gEvexTable_root_05_1d_pp,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
         /* 2a */ (const void *)&gEvexTable_root_05_2a_pp,
-        /* 2b */ NULL,
+        /* 2b */ ND_NULL,
         /* 2c */ (const void *)&gEvexTable_root_05_2c_pp,
         /* 2d */ (const void *)&gEvexTable_root_05_2d_pp,
         /* 2e */ (const void *)&gEvexTable_root_05_2e_pp,
         /* 2f */ (const void *)&gEvexTable_root_05_2f_pp,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
         /* 51 */ (const void *)&gEvexTable_root_05_51_pp,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
         /* 58 */ (const void *)&gEvexTable_root_05_58_pp,
         /* 59 */ (const void *)&gEvexTable_root_05_59_pp,
         /* 5a */ (const void *)&gEvexTable_root_05_5a_pp,
@@ -11417,30 +11417,30 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode =
         /* 5d */ (const void *)&gEvexTable_root_05_5d_pp,
         /* 5e */ (const void *)&gEvexTable_root_05_5e_pp,
         /* 5f */ (const void *)&gEvexTable_root_05_5f_pp,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
         /* 6e */ (const void *)&gEvexTable_root_05_6e_pp,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
         /* 78 */ (const void *)&gEvexTable_root_05_78_pp,
         /* 79 */ (const void *)&gEvexTable_root_05_79_pp,
         /* 7a */ (const void *)&gEvexTable_root_05_7a_pp,
@@ -11448,135 +11448,135 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode =
         /* 7c */ (const void *)&gEvexTable_root_05_7c_pp,
         /* 7d */ (const void *)&gEvexTable_root_05_7d_pp,
         /* 7e */ (const void *)&gEvexTable_root_05_7e_pp,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -11605,10 +11605,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_03_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11623,7 +11623,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_c2_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11638,7 +11638,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_c2_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_c2_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11647,9 +11647,9 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_c2_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_c2_00_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_03_c2_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11664,7 +11664,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_1d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11672,10 +11672,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_1d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11690,7 +11690,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_42_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11698,10 +11698,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_42_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11730,10 +11730,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_19_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11762,10 +11762,10 @@ const ND_TABLE_VEX_L gEvexTable_root_03_1b_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_03_1b_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11773,10 +11773,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_1b_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11805,10 +11805,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_39_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11837,10 +11837,10 @@ const ND_TABLE_VEX_L gEvexTable_root_03_3b_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_03_3b_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11848,10 +11848,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_3b_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11866,9 +11866,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_17_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11883,9 +11883,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_17_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11902,10 +11902,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_17_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11934,10 +11934,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_54_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11966,10 +11966,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_55_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12005,7 +12005,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_66_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_66_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -12015,8 +12015,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_66_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_66_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12052,7 +12052,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_67_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_67_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -12062,8 +12062,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_67_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_67_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12099,7 +12099,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_26_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_26_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -12109,8 +12109,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_26_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_26_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12146,7 +12146,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_27_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_27_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -12156,8 +12156,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_27_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_27_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12171,7 +12171,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_cf_01_01_leaf,
     }
 };
@@ -12180,10 +12180,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_cf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12197,7 +12197,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_ce_01_01_leaf,
     }
 };
@@ -12206,10 +12206,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_ce_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12238,10 +12238,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_18_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12270,10 +12270,10 @@ const ND_TABLE_VEX_L gEvexTable_root_03_1a_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_03_1a_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12281,10 +12281,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_1a_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12313,10 +12313,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_38_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12345,10 +12345,10 @@ const ND_TABLE_VEX_L gEvexTable_root_03_3a_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_03_3a_01_02_w,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12356,10 +12356,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_3a_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12374,9 +12374,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_21_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12391,9 +12391,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_21_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12410,10 +12410,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_21_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12427,10 +12427,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_0f_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12444,10 +12444,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_44_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12476,10 +12476,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_3f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12508,10 +12508,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_1f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12540,10 +12540,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_3e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12572,10 +12572,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_1e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12589,7 +12589,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_05_01_01_leaf,
     }
 };
@@ -12598,10 +12598,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_05_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12616,7 +12616,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_04_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -12624,10 +12624,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_04_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12641,7 +12641,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_01_01_01_leaf,
     }
 };
@@ -12650,10 +12650,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12667,7 +12667,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_00_01_01_leaf,
     }
 };
@@ -12676,10 +12676,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_00_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12694,9 +12694,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_14_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12711,9 +12711,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_14_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12730,10 +12730,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_14_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12763,9 +12763,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_16_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_16_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12773,10 +12773,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_16_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12791,9 +12791,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_15_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12808,9 +12808,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_15_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12827,10 +12827,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_15_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12845,9 +12845,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_20_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12862,9 +12862,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_20_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12881,10 +12881,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_20_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12914,9 +12914,9 @@ const ND_TABLE_VEX_L gEvexTable_root_03_22_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_22_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12924,10 +12924,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_22_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12956,10 +12956,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_71_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -12973,7 +12973,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_70_01_01_leaf,
     }
 };
@@ -12982,10 +12982,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_70_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13014,10 +13014,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_73_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13031,7 +13031,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_72_01_01_leaf,
     }
 };
@@ -13040,10 +13040,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_72_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13072,10 +13072,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_25_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13104,10 +13104,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_50_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13136,10 +13136,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_51_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13175,7 +13175,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_56_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_56_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13185,8 +13185,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_56_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_56_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13222,7 +13222,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_57_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_57_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13232,8 +13232,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_57_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_57_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13247,7 +13247,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_09_01_01_leaf,
     }
 };
@@ -13256,10 +13256,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_09_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13274,7 +13274,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_08_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13289,7 +13289,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_08_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13299,8 +13299,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_08_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_08_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13314,7 +13314,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_0b_01_01_leaf,
     }
 };
@@ -13323,10 +13323,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_0b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13341,7 +13341,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_0a_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13356,7 +13356,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_0a_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13366,8 +13366,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_0a_00_w,
         /* 01 */ (const void *)&gEvexTable_root_03_0a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13396,10 +13396,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_23_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13428,10 +13428,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_43_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_03_43_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13441,24 +13441,24 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode =
     { 
         /* 00 */ (const void *)&gEvexTable_root_03_00_pp,
         /* 01 */ (const void *)&gEvexTable_root_03_01_pp,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gEvexTable_root_03_03_pp,
         /* 04 */ (const void *)&gEvexTable_root_03_04_pp,
         /* 05 */ (const void *)&gEvexTable_root_03_05_pp,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
         /* 08 */ (const void *)&gEvexTable_root_03_08_pp,
         /* 09 */ (const void *)&gEvexTable_root_03_09_pp,
         /* 0a */ (const void *)&gEvexTable_root_03_0a_pp,
         /* 0b */ (const void *)&gEvexTable_root_03_0b_pp,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
         /* 0f */ (const void *)&gEvexTable_root_03_0f_pp,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
         /* 14 */ (const void *)&gEvexTable_root_03_14_pp,
         /* 15 */ (const void *)&gEvexTable_root_03_15_pp,
         /* 16 */ (const void *)&gEvexTable_root_03_16_pp,
@@ -13467,7 +13467,7 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode =
         /* 19 */ (const void *)&gEvexTable_root_03_19_pp,
         /* 1a */ (const void *)&gEvexTable_root_03_1a_pp,
         /* 1b */ (const void *)&gEvexTable_root_03_1b_pp,
-        /* 1c */ NULL,
+        /* 1c */ ND_NULL,
         /* 1d */ (const void *)&gEvexTable_root_03_1d_pp,
         /* 1e */ (const void *)&gEvexTable_root_03_1e_pp,
         /* 1f */ (const void *)&gEvexTable_root_03_1f_pp,
@@ -13475,226 +13475,226 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode =
         /* 21 */ (const void *)&gEvexTable_root_03_21_pp,
         /* 22 */ (const void *)&gEvexTable_root_03_22_pp,
         /* 23 */ (const void *)&gEvexTable_root_03_23_pp,
-        /* 24 */ NULL,
+        /* 24 */ ND_NULL,
         /* 25 */ (const void *)&gEvexTable_root_03_25_pp,
         /* 26 */ (const void *)&gEvexTable_root_03_26_pp,
         /* 27 */ (const void *)&gEvexTable_root_03_27_pp,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
         /* 38 */ (const void *)&gEvexTable_root_03_38_pp,
         /* 39 */ (const void *)&gEvexTable_root_03_39_pp,
         /* 3a */ (const void *)&gEvexTable_root_03_3a_pp,
         /* 3b */ (const void *)&gEvexTable_root_03_3b_pp,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
         /* 3e */ (const void *)&gEvexTable_root_03_3e_pp,
         /* 3f */ (const void *)&gEvexTable_root_03_3f_pp,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
         /* 42 */ (const void *)&gEvexTable_root_03_42_pp,
         /* 43 */ (const void *)&gEvexTable_root_03_43_pp,
         /* 44 */ (const void *)&gEvexTable_root_03_44_pp,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
         /* 50 */ (const void *)&gEvexTable_root_03_50_pp,
         /* 51 */ (const void *)&gEvexTable_root_03_51_pp,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
         /* 54 */ (const void *)&gEvexTable_root_03_54_pp,
         /* 55 */ (const void *)&gEvexTable_root_03_55_pp,
         /* 56 */ (const void *)&gEvexTable_root_03_56_pp,
         /* 57 */ (const void *)&gEvexTable_root_03_57_pp,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
         /* 66 */ (const void *)&gEvexTable_root_03_66_pp,
         /* 67 */ (const void *)&gEvexTable_root_03_67_pp,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
         /* 70 */ (const void *)&gEvexTable_root_03_70_pp,
         /* 71 */ (const void *)&gEvexTable_root_03_71_pp,
         /* 72 */ (const void *)&gEvexTable_root_03_72_pp,
         /* 73 */ (const void *)&gEvexTable_root_03_73_pp,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
         /* c2 */ (const void *)&gEvexTable_root_03_c2_pp,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
         /* ce */ (const void *)&gEvexTable_root_03_ce_pp,
         /* cf */ (const void *)&gEvexTable_root_03_cf_pp,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -13709,7 +13709,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_13_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13724,7 +13724,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_13_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_13_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13734,8 +13734,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_13_pp =
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_13_00_w,
         /* 01 */ (const void *)&gEvexTable_root_06_13_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13750,7 +13750,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_56_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13765,7 +13765,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_56_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_56_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13773,8 +13773,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_56_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_06_56_02_w,
         /* 03 */ (const void *)&gEvexTable_root_06_56_03_w,
     }
@@ -13791,7 +13791,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_57_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13806,7 +13806,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_57_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_57_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13814,8 +13814,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_57_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_06_57_02_w,
         /* 03 */ (const void *)&gEvexTable_root_06_57_03_w,
     }
@@ -13832,7 +13832,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_d6_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13847,7 +13847,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d6_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_d6_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13855,8 +13855,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_06_d6_02_w,
         /* 03 */ (const void *)&gEvexTable_root_06_d6_03_w,
     }
@@ -13873,7 +13873,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_d7_03_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13888,7 +13888,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d7_02_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_d7_02_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13896,8 +13896,8 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gEvexTable_root_06_d7_02_w,
         /* 03 */ (const void *)&gEvexTable_root_06_d7_03_w,
     }
@@ -13914,7 +13914,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_98_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_98_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13922,10 +13922,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_98_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_98_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13940,7 +13940,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_99_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_99_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13948,10 +13948,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_99_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_99_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13966,7 +13966,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_a8_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_a8_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -13974,10 +13974,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_a8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -13992,7 +13992,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_a9_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_a9_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14000,10 +14000,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_a9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14018,7 +14018,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_b8_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_b8_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14026,10 +14026,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_b8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14044,7 +14044,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_b9_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_b9_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14052,10 +14052,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_b9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14070,7 +14070,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_96_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_96_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14078,10 +14078,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_96_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_96_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14096,7 +14096,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_a6_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_a6_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14104,10 +14104,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_a6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14122,7 +14122,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_b6_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_b6_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14130,10 +14130,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_b6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14148,7 +14148,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9a_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9a_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14156,10 +14156,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14174,7 +14174,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14182,10 +14182,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14200,7 +14200,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_aa_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_aa_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14208,10 +14208,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_aa_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_aa_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14226,7 +14226,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_ab_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_ab_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14234,10 +14234,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ab_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_ab_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14252,7 +14252,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_ba_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_ba_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14260,10 +14260,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ba_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_ba_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14278,7 +14278,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_bb_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_bb_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14286,10 +14286,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_bb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14304,7 +14304,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_97_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_97_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14312,10 +14312,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_97_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_97_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14330,7 +14330,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_a7_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_a7_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14338,10 +14338,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_a7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14356,7 +14356,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_b7_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_b7_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14364,10 +14364,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_b7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14382,7 +14382,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14390,10 +14390,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14408,7 +14408,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14416,10 +14416,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14434,7 +14434,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_ac_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_ac_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14442,10 +14442,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ac_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_ac_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14460,7 +14460,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_ad_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_ad_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14468,10 +14468,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ad_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_ad_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14486,7 +14486,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_bc_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_bc_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14494,10 +14494,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_bc_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14512,7 +14512,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_bd_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_bd_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14520,10 +14520,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_bd_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14538,7 +14538,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9e_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9e_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14546,10 +14546,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14564,7 +14564,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_9f_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_9f_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14572,10 +14572,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_9f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14590,7 +14590,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_ae_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_ae_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14598,10 +14598,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ae_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_ae_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14616,7 +14616,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_af_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_af_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14624,10 +14624,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_af_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_af_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14642,7 +14642,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_be_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_be_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14650,10 +14650,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_be_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_be_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14668,7 +14668,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_bf_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_bf_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14676,10 +14676,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_bf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14694,7 +14694,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_42_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_42_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14702,10 +14702,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_42_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_42_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14720,7 +14720,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_43_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_43_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14728,10 +14728,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_43_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_43_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14746,7 +14746,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_4c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_4c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14754,10 +14754,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_4c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14772,7 +14772,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_4d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_4d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14780,10 +14780,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_4d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14798,7 +14798,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_4e_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_4e_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14806,10 +14806,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_4e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14824,7 +14824,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_4f_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_4f_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14832,10 +14832,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_4f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14850,7 +14850,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_2c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_2c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14858,10 +14858,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_2c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14876,7 +14876,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_2d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gEvexTable_root_06_2d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14884,10 +14884,10 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_06_2d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -14895,156 +14895,156 @@ const ND_TABLE_OPCODE gEvexTable_root_06_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
         /* 13 */ (const void *)&gEvexTable_root_06_13_pp,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
         /* 2c */ (const void *)&gEvexTable_root_06_2c_pp,
         /* 2d */ (const void *)&gEvexTable_root_06_2d_pp,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
         /* 42 */ (const void *)&gEvexTable_root_06_42_pp,
         /* 43 */ (const void *)&gEvexTable_root_06_43_pp,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
         /* 4c */ (const void *)&gEvexTable_root_06_4c_pp,
         /* 4d */ (const void *)&gEvexTable_root_06_4d_pp,
         /* 4e */ (const void *)&gEvexTable_root_06_4e_pp,
         /* 4f */ (const void *)&gEvexTable_root_06_4f_pp,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
         /* 56 */ (const void *)&gEvexTable_root_06_56_pp,
         /* 57 */ (const void *)&gEvexTable_root_06_57_pp,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
         /* 96 */ (const void *)&gEvexTable_root_06_96_pp,
         /* 97 */ (const void *)&gEvexTable_root_06_97_pp,
         /* 98 */ (const void *)&gEvexTable_root_06_98_pp,
@@ -15055,12 +15055,12 @@ const ND_TABLE_OPCODE gEvexTable_root_06_opcode =
         /* 9d */ (const void *)&gEvexTable_root_06_9d_pp,
         /* 9e */ (const void *)&gEvexTable_root_06_9e_pp,
         /* 9f */ (const void *)&gEvexTable_root_06_9f_pp,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
         /* a6 */ (const void *)&gEvexTable_root_06_a6_pp,
         /* a7 */ (const void *)&gEvexTable_root_06_a7_pp,
         /* a8 */ (const void *)&gEvexTable_root_06_a8_pp,
@@ -15071,12 +15071,12 @@ const ND_TABLE_OPCODE gEvexTable_root_06_opcode =
         /* ad */ (const void *)&gEvexTable_root_06_ad_pp,
         /* ae */ (const void *)&gEvexTable_root_06_ae_pp,
         /* af */ (const void *)&gEvexTable_root_06_af_pp,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
         /* b6 */ (const void *)&gEvexTable_root_06_b6_pp,
         /* b7 */ (const void *)&gEvexTable_root_06_b7_pp,
         /* b8 */ (const void *)&gEvexTable_root_06_b8_pp,
@@ -15087,70 +15087,70 @@ const ND_TABLE_OPCODE gEvexTable_root_06_opcode =
         /* bd */ (const void *)&gEvexTable_root_06_bd_pp,
         /* be */ (const void *)&gEvexTable_root_06_be_pp,
         /* bf */ (const void *)&gEvexTable_root_06_bf_pp,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
         /* d6 */ (const void *)&gEvexTable_root_06_d6_pp,
         /* d7 */ (const void *)&gEvexTable_root_06_d7_pp,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -15158,38 +15158,38 @@ const ND_TABLE_VEX_MMMMM gEvexTable_root_mmmmm =
 {
     ND_ILUT_VEX_MMMMM,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gEvexTable_root_01_opcode,
         /* 02 */ (const void *)&gEvexTable_root_02_opcode,
         /* 03 */ (const void *)&gEvexTable_root_03_opcode,
-        /* 04 */ NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gEvexTable_root_05_opcode,
         /* 06 */ (const void *)&gEvexTable_root_06_opcode,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
     }
 };
 
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
index 5053fea..a1d0ca0 100644
--- a/bddisasm/include/table_root.h
+++ b/bddisasm/include/table_root.h
@@ -342,11 +342,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -357,7 +357,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_mem_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f6_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -377,10 +377,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f6_reg_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_f6_reg_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -409,10 +409,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_de_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_de_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -426,10 +426,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_de_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -458,10 +458,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_dd_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_dd_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -475,10 +475,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_dd_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -507,10 +507,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_df_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_df_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -524,10 +524,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_df_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -550,10 +550,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_01_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -567,10 +567,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_03_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -584,10 +584,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -601,10 +601,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_02_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -616,10 +616,10 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_38_d8_mem_modrmreg =
         /* 01 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_mprefix,
         /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_mprefix,
         /* 03 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_mprefix,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -628,7 +628,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_d8_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_d8_mem_modrmreg,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -648,10 +648,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_dc_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_dc_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -671,10 +671,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_dc_reg_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_dc_reg_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -697,10 +697,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_db_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -714,10 +714,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_15_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -731,10 +731,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_14_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -756,8 +756,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -779,7 +779,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_mprefix,
     }
 };
@@ -802,8 +802,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -811,9 +811,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_mprefix,
     }
 };
@@ -845,8 +845,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -868,7 +868,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_mprefix,
     }
 };
@@ -891,8 +891,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -900,9 +900,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_mprefix,
     }
 };
@@ -926,10 +926,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_fa_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_fa_reg_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -937,7 +937,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fa_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_fa_reg_mprefix,
     }
 };
@@ -952,10 +952,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_fb_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_fb_reg_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -963,7 +963,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fb_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_fb_reg_mprefix,
     }
 };
@@ -990,7 +990,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f8_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_38_f8_mem_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_38_f8_mem_F2_leaf,
@@ -1002,7 +1002,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f8_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1016,10 +1016,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_cf_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1033,10 +1033,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_80_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1045,7 +1045,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_80_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1059,10 +1059,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_82_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1071,7 +1071,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_82_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1085,10 +1085,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_81_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1097,7 +1097,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_81_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1112,9 +1112,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1123,7 +1123,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1137,10 +1137,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_2a_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1149,7 +1149,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_2a_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1171,8 +1171,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_1c_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_1c_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1194,8 +1194,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_1e_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_1e_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1217,8 +1217,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_1d_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_1d_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1232,10 +1232,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_2b_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1249,10 +1249,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_10_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1266,10 +1266,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_29_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1283,10 +1283,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_37_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1308,8 +1308,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_02_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_02_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1331,8 +1331,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_03_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_03_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1354,8 +1354,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_01_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_01_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1369,10 +1369,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_41_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1394,8 +1394,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_06_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_06_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1417,8 +1417,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_07_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_07_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1440,8 +1440,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_05_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_05_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1463,8 +1463,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_04_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_04_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1478,10 +1478,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3c_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1495,10 +1495,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3d_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1512,10 +1512,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3f_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1529,10 +1529,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3e_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1546,10 +1546,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_38_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1563,10 +1563,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_39_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1580,10 +1580,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3b_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1597,10 +1597,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_3a_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1614,10 +1614,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_21_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1631,10 +1631,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_22_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1648,10 +1648,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_20_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1665,10 +1665,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_25_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1682,10 +1682,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_23_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1699,10 +1699,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_24_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1716,10 +1716,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_31_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1733,10 +1733,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_32_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1750,10 +1750,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_30_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1767,10 +1767,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_35_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1784,10 +1784,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_33_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1801,10 +1801,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_34_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1818,10 +1818,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_28_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1843,8 +1843,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_0b_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_0b_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1858,10 +1858,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_40_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1883,8 +1883,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_00_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_00_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1906,8 +1906,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_08_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_08_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1929,8 +1929,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_0a_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_0a_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1952,8 +1952,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_09_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_38_09_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1967,10 +1967,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_17_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1985,9 +1985,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_c9_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2002,9 +2002,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_ca_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2019,9 +2019,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_c8_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2036,9 +2036,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_cc_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2053,9 +2053,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_cd_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2070,9 +2070,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_cb_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2093,11 +2093,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -2105,10 +2105,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f5_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2117,7 +2117,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f5_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2137,49 +2137,49 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode =
         /* 09 */ (const void *)&gRootTable_root_0f_38_09_mprefix,
         /* 0a */ (const void *)&gRootTable_root_0f_38_0a_mprefix,
         /* 0b */ (const void *)&gRootTable_root_0f_38_0b_mprefix,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gRootTable_root_0f_38_10_mprefix,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
         /* 14 */ (const void *)&gRootTable_root_0f_38_14_mprefix,
         /* 15 */ (const void *)&gRootTable_root_0f_38_15_mprefix,
-        /* 16 */ NULL,
+        /* 16 */ ND_NULL,
         /* 17 */ (const void *)&gRootTable_root_0f_38_17_mprefix,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
         /* 1c */ (const void *)&gRootTable_root_0f_38_1c_mprefix,
         /* 1d */ (const void *)&gRootTable_root_0f_38_1d_mprefix,
         /* 1e */ (const void *)&gRootTable_root_0f_38_1e_mprefix,
-        /* 1f */ NULL,
+        /* 1f */ ND_NULL,
         /* 20 */ (const void *)&gRootTable_root_0f_38_20_mprefix,
         /* 21 */ (const void *)&gRootTable_root_0f_38_21_mprefix,
         /* 22 */ (const void *)&gRootTable_root_0f_38_22_mprefix,
         /* 23 */ (const void *)&gRootTable_root_0f_38_23_mprefix,
         /* 24 */ (const void *)&gRootTable_root_0f_38_24_mprefix,
         /* 25 */ (const void *)&gRootTable_root_0f_38_25_mprefix,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
         /* 28 */ (const void *)&gRootTable_root_0f_38_28_mprefix,
         /* 29 */ (const void *)&gRootTable_root_0f_38_29_mprefix,
         /* 2a */ (const void *)&gRootTable_root_0f_38_2a_modrmmod,
         /* 2b */ (const void *)&gRootTable_root_0f_38_2b_mprefix,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
         /* 30 */ (const void *)&gRootTable_root_0f_38_30_mprefix,
         /* 31 */ (const void *)&gRootTable_root_0f_38_31_mprefix,
         /* 32 */ (const void *)&gRootTable_root_0f_38_32_mprefix,
         /* 33 */ (const void *)&gRootTable_root_0f_38_33_mprefix,
         /* 34 */ (const void *)&gRootTable_root_0f_38_34_mprefix,
         /* 35 */ (const void *)&gRootTable_root_0f_38_35_mprefix,
-        /* 36 */ NULL,
+        /* 36 */ ND_NULL,
         /* 37 */ (const void *)&gRootTable_root_0f_38_37_mprefix,
         /* 38 */ (const void *)&gRootTable_root_0f_38_38_mprefix,
         /* 39 */ (const void *)&gRootTable_root_0f_38_39_mprefix,
@@ -2191,196 +2191,196 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode =
         /* 3f */ (const void *)&gRootTable_root_0f_38_3f_mprefix,
         /* 40 */ (const void *)&gRootTable_root_0f_38_40_mprefix,
         /* 41 */ (const void *)&gRootTable_root_0f_38_41_mprefix,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
         /* 80 */ (const void *)&gRootTable_root_0f_38_80_modrmmod,
         /* 81 */ (const void *)&gRootTable_root_0f_38_81_modrmmod,
         /* 82 */ (const void *)&gRootTable_root_0f_38_82_modrmmod,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
         /* c8 */ (const void *)&gRootTable_root_0f_38_c8_mprefix,
         /* c9 */ (const void *)&gRootTable_root_0f_38_c9_mprefix,
         /* ca */ (const void *)&gRootTable_root_0f_38_ca_mprefix,
         /* cb */ (const void *)&gRootTable_root_0f_38_cb_mprefix,
         /* cc */ (const void *)&gRootTable_root_0f_38_cc_mprefix,
         /* cd */ (const void *)&gRootTable_root_0f_38_cd_mprefix,
-        /* ce */ NULL,
+        /* ce */ ND_NULL,
         /* cf */ (const void *)&gRootTable_root_0f_38_cf_mprefix,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
         /* d8 */ (const void *)&gRootTable_root_0f_38_d8_modrmmod,
-        /* d9 */ NULL,
-        /* da */ NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
         /* db */ (const void *)&gRootTable_root_0f_38_db_mprefix,
         /* dc */ (const void *)&gRootTable_root_0f_38_dc_modrmmod,
         /* dd */ (const void *)&gRootTable_root_0f_38_dd_modrmmod,
         /* de */ (const void *)&gRootTable_root_0f_38_de_modrmmod,
         /* df */ (const void *)&gRootTable_root_0f_38_df_modrmmod,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
         /* f0 */ (const void *)&gRootTable_root_0f_38_f0_modrmmod,
         /* f1 */ (const void *)&gRootTable_root_0f_38_f1_modrmmod,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
         /* f5 */ (const void *)&gRootTable_root_0f_38_f5_modrmmod,
         /* f6 */ (const void *)&gRootTable_root_0f_38_f6_modrmmod,
-        /* f7 */ NULL,
+        /* f7 */ ND_NULL,
         /* f8 */ (const void *)&gRootTable_root_0f_38_f8_modrmmod,
         /* f9 */ (const void *)&gRootTable_root_0f_38_f9_modrmmod,
         /* fa */ (const void *)&gRootTable_root_0f_38_fa_modrmmod,
         /* fb */ (const void *)&gRootTable_root_0f_38_fb_modrmmod,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -2435,9 +2435,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_d0_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_d0_F2_leaf,
     }
 };
@@ -2452,10 +2452,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_df_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2469,10 +2469,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0d_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2486,10 +2486,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0c_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2503,10 +2503,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_41_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2520,10 +2520,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_40_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2537,10 +2537,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_17_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2554,10 +2554,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_cf_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2571,10 +2571,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_ce_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2588,10 +2588,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_f0_reg_00_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2600,13 +2600,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_3a_f0_reg_00_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -2615,13 +2615,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_3a_f0_reg_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_modrmrm,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -2629,7 +2629,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_f0_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_f0_reg_modrmreg,
     }
 };
@@ -2644,10 +2644,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_21_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2661,10 +2661,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2687,10 +2687,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_42_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2712,8 +2712,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_0f_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0f_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2727,10 +2727,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0e_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2744,10 +2744,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_44_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2761,10 +2761,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_61_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2778,10 +2778,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_60_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2795,10 +2795,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_63_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2812,10 +2812,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_62_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2829,10 +2829,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_14_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2846,10 +2846,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_14_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2879,11 +2879,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_16_66_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_3a_16_66_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -2891,10 +2891,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_16_66_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2908,10 +2908,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_15_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2925,10 +2925,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_15_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2951,10 +2951,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_20_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2968,10 +2968,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_20_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3001,11 +3001,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_22_66_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_3a_22_66_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -3013,10 +3013,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_22_66_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3030,10 +3030,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_09_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3047,10 +3047,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_08_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3064,10 +3064,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0b_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3081,10 +3081,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_3a_0a_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3099,9 +3099,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_3a_cc_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3109,14 +3109,14 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
         /* 08 */ (const void *)&gRootTable_root_0f_3a_08_mprefix,
         /* 09 */ (const void *)&gRootTable_root_0f_3a_09_mprefix,
         /* 0a */ (const void *)&gRootTable_root_0f_3a_0a_mprefix,
@@ -3125,246 +3125,246 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode =
         /* 0d */ (const void *)&gRootTable_root_0f_3a_0d_mprefix,
         /* 0e */ (const void *)&gRootTable_root_0f_3a_0e_mprefix,
         /* 0f */ (const void *)&gRootTable_root_0f_3a_0f_mprefix,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
         /* 14 */ (const void *)&gRootTable_root_0f_3a_14_modrmmod,
         /* 15 */ (const void *)&gRootTable_root_0f_3a_15_modrmmod,
         /* 16 */ (const void *)&gRootTable_root_0f_3a_16_mprefix,
         /* 17 */ (const void *)&gRootTable_root_0f_3a_17_mprefix,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
         /* 20 */ (const void *)&gRootTable_root_0f_3a_20_modrmmod,
         /* 21 */ (const void *)&gRootTable_root_0f_3a_21_modrmmod,
         /* 22 */ (const void *)&gRootTable_root_0f_3a_22_mprefix,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
         /* 40 */ (const void *)&gRootTable_root_0f_3a_40_mprefix,
         /* 41 */ (const void *)&gRootTable_root_0f_3a_41_mprefix,
         /* 42 */ (const void *)&gRootTable_root_0f_3a_42_mprefix,
-        /* 43 */ NULL,
+        /* 43 */ ND_NULL,
         /* 44 */ (const void *)&gRootTable_root_0f_3a_44_mprefix,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
         /* 60 */ (const void *)&gRootTable_root_0f_3a_60_mprefix,
         /* 61 */ (const void *)&gRootTable_root_0f_3a_61_mprefix,
         /* 62 */ (const void *)&gRootTable_root_0f_3a_62_mprefix,
         /* 63 */ (const void *)&gRootTable_root_0f_3a_63_mprefix,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
         /* cc */ (const void *)&gRootTable_root_0f_3a_cc_mprefix,
-        /* cd */ NULL,
+        /* cd */ ND_NULL,
         /* ce */ (const void *)&gRootTable_root_0f_3a_ce_mprefix,
         /* cf */ (const void *)&gRootTable_root_0f_3a_cf_mprefix,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
         /* df */ (const void *)&gRootTable_root_0f_3a_df_mprefix,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
         /* f0 */ (const void *)&gRootTable_root_0f_3a_f0_modrmmod,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -3392,8 +3392,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_55_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_55_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3415,8 +3415,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_54_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_54_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3511,8 +3511,8 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1a_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3607,8 +3607,8 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1b_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3629,11 +3629,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_bc_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_bc_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -3654,11 +3654,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_bd_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_bd_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -3744,10 +3744,10 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_ba_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_0f_ba_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_0f_ba_06_leaf,
@@ -3796,7 +3796,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_02_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F2_leaf,
     }
@@ -3820,8 +3820,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_07_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_07_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3836,9 +3836,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_00_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3853,9 +3853,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_01_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3869,10 +3869,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_06_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3886,10 +3886,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_05_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3904,9 +3904,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_03_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3920,10 +3920,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_04_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4051,9 +4051,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_06_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_06_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4067,10 +4067,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4097,7 +4097,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F2_leaf,
     }
@@ -4120,9 +4120,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_07_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_07_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4136,10 +4136,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_05_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4153,10 +4153,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_04_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4170,9 +4170,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_01_F2_leaf,
     }
 };
@@ -4184,7 +4184,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm =
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_mprefix,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_05_01_mprefix,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_mprefix,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_01_reg_05_04_mprefix,
         /* 05 */ (const void *)&gRootTable_root_0f_01_reg_05_05_mprefix,
         /* 06 */ (const void *)&gRootTable_root_0f_01_reg_05_06_mprefix,
@@ -4221,7 +4221,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_06_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F2_leaf,
     }
@@ -4244,9 +4244,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_02_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4261,9 +4261,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_03_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4290,7 +4290,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_07_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F2_leaf,
     }
@@ -4340,9 +4340,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_07_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4357,9 +4357,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_04_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4374,9 +4374,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_05_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4391,9 +4391,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4408,9 +4408,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_01_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4425,9 +4425,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_06_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4437,8 +4437,8 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_mprefix,
         /* 01 */ (const void *)&gRootTable_root_0f_01_reg_02_01_mprefix,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_01_reg_02_04_mprefix,
         /* 05 */ (const void *)&gRootTable_root_0f_01_reg_02_05_mprefix,
         /* 06 */ (const void *)&gRootTable_root_0f_01_reg_02_06_mprefix,
@@ -4457,9 +4457,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4474,9 +4474,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_05_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4491,9 +4491,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_01_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4508,9 +4508,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_02_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4525,9 +4525,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_03_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4542,9 +4542,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_04_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4558,8 +4558,8 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm =
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_mprefix,
         /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_mprefix,
         /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -4624,10 +4624,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_01_mem_05_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4848,8 +4848,8 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature =
     ND_ILUT_FEATURE,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1c_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_modrmmod,
     }
 };
@@ -4872,8 +4872,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_07_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_07_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4906,11 +4906,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -4921,7 +4921,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_06_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4942,11 +4942,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -4955,9 +4955,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4978,11 +4978,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -4991,9 +4991,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5008,9 +5008,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_02_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5037,11 +5037,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5050,9 +5050,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_auxiliary,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5067,9 +5067,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_03_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5090,11 +5090,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5103,9 +5103,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_05_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5141,11 +5141,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5160,9 +5160,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5211,10 +5211,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_04_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5228,12 +5228,12 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary =
 {
     ND_ILUT_AUXILIARY,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5241,10 +5241,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5258,12 +5258,12 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary =
 {
     ND_ILUT_AUXILIARY,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5271,10 +5271,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5289,9 +5289,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_07_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5305,12 +5305,12 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary =
 {
     ND_ILUT_AUXILIARY,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5318,10 +5318,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5335,12 +5335,12 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary =
 {
     ND_ILUT_AUXILIARY,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5348,10 +5348,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_03_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5545,11 +5545,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_01_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_01_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5578,7 +5578,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_06_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_06_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_06_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5593,9 +5593,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_07_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5616,11 +5616,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5629,9 +5629,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5652,11 +5652,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5665,9 +5665,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5688,11 +5688,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -5701,9 +5701,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_05_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_auxiliary,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5711,9 +5711,9 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_01_auxiliary,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_c7_mem_03_mprefix,
         /* 04 */ (const void *)&gRootTable_root_0f_c7_mem_04_mprefix,
         /* 05 */ (const void *)&gRootTable_root_0f_c7_mem_05_mprefix,
@@ -5747,7 +5747,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_07_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_07_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_07_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5776,7 +5776,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_06_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_06_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_06_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5784,12 +5784,12 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_0f_c7_reg_06_mprefix,
         /* 07 */ (const void *)&gRootTable_root_0f_c7_reg_07_mprefix,
     }
@@ -5822,8 +5822,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_2f_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_2f_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5867,7 +5867,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_e6_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_e6_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_e6_F2_leaf,
@@ -5899,7 +5899,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_5b_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_5b_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_5b_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6095,9 +6095,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_77_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6118,11 +6118,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6143,11 +6143,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6231,11 +6231,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6250,11 +6250,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6329,9 +6329,9 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature =
     ND_ILUT_FEATURE,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_1e_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6346,13 +6346,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_78_None_66_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -6374,7 +6374,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_78_None_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_78_None_66_modrmreg,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_78_None_F2_leaf,
     }
 };
@@ -6390,7 +6390,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_78_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6399,11 +6399,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_78_None_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_78_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6431,7 +6431,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_79_None_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_79_None_reg_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_79_None_reg_F2_leaf,
     }
 };
@@ -6447,9 +6447,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_79_None_mem_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6473,7 +6473,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_79_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6482,11 +6482,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_79_None_modrmmod,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_79_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6507,9 +6507,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_37_None_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6524,11 +6524,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_37_None_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_37_cyrix_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6548,9 +6548,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_7c_None_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_7c_None_F2_leaf,
     }
 };
@@ -6566,7 +6566,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7c_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6575,11 +6575,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7c_None_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_7c_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6599,9 +6599,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_7d_None_66_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_7d_None_F2_leaf,
     }
 };
@@ -6617,7 +6617,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7d_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6626,11 +6626,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7d_None_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_7d_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6687,8 +6687,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_00_mem_06_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_00_mem_06_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_00_mem_06_F2_leaf,
     }
 };
@@ -6740,7 +6740,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
         /* 04 */ (const void *)&gRootTable_root_0f_00_mem_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_0f_00_mem_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_0f_00_mem_06_mprefix,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -6761,8 +6761,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_00_reg_06_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_00_reg_06_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_00_reg_06_F2_leaf,
     }
 };
@@ -6814,7 +6814,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg =
         /* 04 */ (const void *)&gRootTable_root_0f_00_reg_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_0f_00_reg_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_0f_00_reg_06_mprefix,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -6844,11 +6844,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_b8_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_b8_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -6955,9 +6955,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_0f_f0_mem_F2_leaf,
     }
 };
@@ -6967,7 +6967,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f0_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6982,7 +6982,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_b4_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6997,7 +6997,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_b5_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7033,7 +7033,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_b2_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7055,8 +7055,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f7_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7064,7 +7064,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_mprefix,
     }
 };
@@ -7149,10 +7149,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7161,13 +7161,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -7181,10 +7181,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7193,13 +7193,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -7213,10 +7213,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7225,13 +7225,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_02_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -7242,11 +7242,11 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_a6_reg_modrmreg =
         /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_modrmrm,
         /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_01_modrmrm,
         /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_modrmrm,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -7254,7 +7254,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_modrmreg,
     }
 };
@@ -7313,8 +7313,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_28_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_28_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7336,8 +7336,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_29_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_29_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7358,11 +7358,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_6e_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -7383,11 +7383,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_6e_66_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_6e_66_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -7397,8 +7397,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_0f_6e_66_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7419,11 +7419,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_7e_None_NP_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -7444,11 +7444,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7e_None_66_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_7e_None_66_rexw_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -7465,7 +7465,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_0f_7e_None_66_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_0f_7e_None_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7480,11 +7480,11 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor =
     ND_ILUT_VENDOR,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7e_None_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_7e_cyrix_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -7546,7 +7546,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_12_reg_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_12_reg_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_12_reg_F2_leaf,
     }
@@ -7583,7 +7583,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_d6_reg_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_d6_reg_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_d6_reg_F2_leaf,
@@ -7600,10 +7600,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_d6_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7641,7 +7641,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_6f_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_6f_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_6f_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7670,7 +7670,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_7f_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_7f_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_7f_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7699,7 +7699,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix =
         /* 00 */ (const void *)&gRootTable_root_0f_16_mem_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_16_mem_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_16_mem_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7720,9 +7720,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_16_reg_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_16_reg_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7753,8 +7753,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_17_mem_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_17_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7763,7 +7763,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_17_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7785,8 +7785,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_13_mem_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_13_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7795,7 +7795,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_13_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7817,8 +7817,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_50_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_50_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7826,7 +7826,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_50_reg_mprefix,
     }
 };
@@ -7849,8 +7849,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e7_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7859,7 +7859,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7874,9 +7874,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_NP_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7885,7 +7885,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7929,7 +7929,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_2b_mem_mprefix,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -8368,8 +8368,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_56_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_56_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8391,8 +8391,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_6b_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_6b_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8414,8 +8414,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_63_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_63_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8437,8 +8437,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_67_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_67_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8460,8 +8460,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_fc_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_fc_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8483,8 +8483,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_fe_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_fe_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8506,8 +8506,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d4_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d4_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8529,8 +8529,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ec_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ec_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8552,8 +8552,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ed_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ed_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8575,8 +8575,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_dc_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_dc_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8598,8 +8598,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_dd_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_dd_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8621,8 +8621,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_fd_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_fd_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8644,8 +8644,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_db_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_db_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8667,8 +8667,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_df_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_df_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8690,8 +8690,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e0_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e0_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8855,262 +8855,262 @@ const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow =
 {
     ND_ILUT_OPCODE_3DNOW,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
         /* 0c */ (const void *)&gRootTable_root_0f_0f_0c_leaf,
         /* 0d */ (const void *)&gRootTable_root_0f_0f_0d_leaf,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
         /* 1c */ (const void *)&gRootTable_root_0f_0f_1c_leaf,
         /* 1d */ (const void *)&gRootTable_root_0f_0f_1d_leaf,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
         /* 86 */ (const void *)&gRootTable_root_0f_0f_86_leaf,
         /* 87 */ (const void *)&gRootTable_root_0f_0f_87_leaf,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
         /* 8a */ (const void *)&gRootTable_root_0f_0f_8a_leaf,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
         /* 8e */ (const void *)&gRootTable_root_0f_0f_8e_leaf,
-        /* 8f */ NULL,
+        /* 8f */ ND_NULL,
         /* 90 */ (const void *)&gRootTable_root_0f_0f_90_leaf,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
         /* 94 */ (const void *)&gRootTable_root_0f_0f_94_leaf,
-        /* 95 */ NULL,
+        /* 95 */ ND_NULL,
         /* 96 */ (const void *)&gRootTable_root_0f_0f_96_leaf,
         /* 97 */ (const void *)&gRootTable_root_0f_0f_97_leaf,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
         /* 9a */ (const void *)&gRootTable_root_0f_0f_9a_leaf,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
         /* 9e */ (const void *)&gRootTable_root_0f_0f_9e_leaf,
-        /* 9f */ NULL,
+        /* 9f */ ND_NULL,
         /* a0 */ (const void *)&gRootTable_root_0f_0f_a0_leaf,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
         /* a4 */ (const void *)&gRootTable_root_0f_0f_a4_leaf,
-        /* a5 */ NULL,
+        /* a5 */ ND_NULL,
         /* a6 */ (const void *)&gRootTable_root_0f_0f_a6_leaf,
         /* a7 */ (const void *)&gRootTable_root_0f_0f_a7_leaf,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
         /* aa */ (const void *)&gRootTable_root_0f_0f_aa_leaf,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
         /* ae */ (const void *)&gRootTable_root_0f_0f_ae_leaf,
-        /* af */ NULL,
+        /* af */ ND_NULL,
         /* b0 */ (const void *)&gRootTable_root_0f_0f_b0_leaf,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
         /* b4 */ (const void *)&gRootTable_root_0f_0f_b4_leaf,
-        /* b5 */ NULL,
+        /* b5 */ ND_NULL,
         /* b6 */ (const void *)&gRootTable_root_0f_0f_b6_leaf,
         /* b7 */ (const void *)&gRootTable_root_0f_0f_b7_leaf,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
         /* bb */ (const void *)&gRootTable_root_0f_0f_bb_leaf,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
         /* bf */ (const void *)&gRootTable_root_0f_0f_bf_leaf,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -9132,8 +9132,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e3_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e3_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9155,8 +9155,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_74_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_74_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9178,8 +9178,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_76_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_76_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9201,8 +9201,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_75_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_75_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9224,8 +9224,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_64_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_64_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9247,8 +9247,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_66_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_66_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9270,8 +9270,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_65_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_65_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9293,8 +9293,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c5_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9302,7 +9302,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_mprefix,
     }
 };
@@ -9325,8 +9325,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c4_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c4_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9348,8 +9348,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c4_mem_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c4_mem_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9380,8 +9380,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f5_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f5_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9403,8 +9403,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ee_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ee_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9426,8 +9426,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_de_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_de_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9449,8 +9449,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ea_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ea_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9472,8 +9472,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_da_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_da_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9495,8 +9495,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d7_reg_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9504,7 +9504,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_mprefix,
     }
 };
@@ -9527,8 +9527,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e4_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e4_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9550,8 +9550,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e5_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e5_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9573,8 +9573,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d5_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d5_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9596,8 +9596,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f4_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f4_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9631,8 +9631,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_eb_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_eb_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9654,8 +9654,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f6_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f6_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9712,8 +9712,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_72_reg_06_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_72_reg_06_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9735,8 +9735,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_72_reg_04_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_72_reg_04_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9758,8 +9758,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_72_reg_02_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_72_reg_02_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9767,14 +9767,14 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_72_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_72_reg_02_mprefix,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_72_reg_04_mprefix,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_0f_72_reg_06_mprefix,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -9782,7 +9782,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_72_reg_modrmreg,
     }
 };
@@ -9805,8 +9805,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f2_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9820,10 +9820,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_73_reg_07_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9845,8 +9845,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_73_reg_06_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_73_reg_06_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9860,10 +9860,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_73_reg_03_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9885,8 +9885,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_73_reg_02_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_73_reg_02_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9894,12 +9894,12 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_73_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_73_reg_02_mprefix,
         /* 03 */ (const void *)&gRootTable_root_0f_73_reg_03_mprefix,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_0f_73_reg_06_mprefix,
         /* 07 */ (const void *)&gRootTable_root_0f_73_reg_07_mprefix,
     }
@@ -9909,7 +9909,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_73_reg_modrmreg,
     }
 };
@@ -9932,8 +9932,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f3_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f3_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9955,8 +9955,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_71_reg_06_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_71_reg_06_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9978,8 +9978,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_71_reg_04_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_71_reg_04_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10001,8 +10001,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_71_reg_02_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_71_reg_02_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10010,14 +10010,14 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_71_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_71_reg_02_mprefix,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_71_reg_04_mprefix,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_0f_71_reg_06_mprefix,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -10025,7 +10025,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_71_reg_modrmreg,
     }
 };
@@ -10048,8 +10048,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f1_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f1_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10071,8 +10071,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e2_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10094,8 +10094,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e1_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e1_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10117,8 +10117,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d2_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d2_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10140,8 +10140,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d3_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d3_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10163,8 +10163,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d1_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d1_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10186,8 +10186,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f8_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f8_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10209,8 +10209,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_fa_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_fa_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10232,8 +10232,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_fb_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_fb_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10255,8 +10255,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e8_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e8_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10278,8 +10278,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_e9_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_e9_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10301,8 +10301,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d8_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d8_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10324,8 +10324,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_d9_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_d9_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10347,8 +10347,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_f9_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_f9_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10370,8 +10370,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_68_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_68_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10393,8 +10393,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_6a_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_6a_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10408,10 +10408,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_6d_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10433,8 +10433,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_69_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_69_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10456,8 +10456,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_60_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_60_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10479,8 +10479,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_62_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_62_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10494,10 +10494,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_6c_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10519,8 +10519,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_61_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_61_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10554,8 +10554,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_ef_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_ef_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10576,9 +10576,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_53_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_53_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10604,12 +10604,12 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor =
 {
     ND_ILUT_VENDOR,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_36_cyrix_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -10630,7 +10630,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7b_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10638,12 +10638,12 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor =
 {
     ND_ILUT_VENDOR,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_7b_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -10670,9 +10670,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_52_NP_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_52_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10814,8 +10814,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_c6_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_c6_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10900,7 +10900,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_7a_cyrix_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10908,12 +10908,12 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor =
 {
     ND_ILUT_VENDOR,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_7a_cyrix_modrmmod,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -10959,8 +10959,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_2e_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_2e_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11000,8 +11000,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_15_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_15_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11023,8 +11023,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_14_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_14_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11045,11 +11045,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_09_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_0f_09_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -11081,10 +11081,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11093,13 +11093,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11113,10 +11113,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11125,13 +11125,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11145,10 +11145,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11157,13 +11157,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11177,10 +11177,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11189,13 +11189,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11209,10 +11209,10 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix =
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11221,13 +11221,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11248,9 +11248,9 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_F3_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11259,13 +11259,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_mprefix,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11279,8 +11279,8 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_a7_reg_modrmreg =
         /* 03 */ (const void *)&gRootTable_root_0f_a7_reg_03_modrmrm,
         /* 04 */ (const void *)&gRootTable_root_0f_a7_reg_04_modrmrm,
         /* 05 */ (const void *)&gRootTable_root_0f_a7_reg_05_modrmrm,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11288,7 +11288,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_0f_a7_reg_modrmreg,
     }
 };
@@ -11311,8 +11311,8 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix =
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_57_NP_leaf,
         /* 01 */ (const void *)&gRootTable_root_0f_57_66_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11324,15 +11324,15 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode =
         /* 01 */ (const void *)&gRootTable_root_0f_01_modrmmod,
         /* 02 */ (const void *)&gRootTable_root_0f_02_modrmmod,
         /* 03 */ (const void *)&gRootTable_root_0f_03_modrmmod,
-        /* 04 */ NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_0f_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_0f_06_leaf,
         /* 07 */ (const void *)&gRootTable_root_0f_07_leaf,
         /* 08 */ (const void *)&gRootTable_root_0f_08_leaf,
         /* 09 */ (const void *)&gRootTable_root_0f_09_auxiliary,
-        /* 0a */ NULL,
+        /* 0a */ ND_NULL,
         /* 0b */ (const void *)&gRootTable_root_0f_0b_leaf,
-        /* 0c */ NULL,
+        /* 0c */ ND_NULL,
         /* 0d */ (const void *)&gRootTable_root_0f_0d_modrmmod,
         /* 0e */ (const void *)&gRootTable_root_0f_0e_leaf,
         /* 0f */ (const void *)&gRootTable_root_0f_0f_opcode_3dnow,
@@ -11357,9 +11357,9 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode =
         /* 22 */ (const void *)&gRootTable_root_0f_22_leaf,
         /* 23 */ (const void *)&gRootTable_root_0f_23_leaf,
         /* 24 */ (const void *)&gRootTable_root_0f_24_leaf,
-        /* 25 */ NULL,
+        /* 25 */ ND_NULL,
         /* 26 */ (const void *)&gRootTable_root_0f_26_leaf,
-        /* 27 */ NULL,
+        /* 27 */ ND_NULL,
         /* 28 */ (const void *)&gRootTable_root_0f_28_mprefix,
         /* 29 */ (const void *)&gRootTable_root_0f_29_mprefix,
         /* 2a */ (const void *)&gRootTable_root_0f_2a_mprefix,
@@ -11379,10 +11379,10 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode =
         /* 38 */ (const void *)&gRootTable_root_0f_38_opcode,
         /* 39 */ (const void *)&gRootTable_root_0f_39_leaf,
         /* 3a */ (const void *)&gRootTable_root_0f_3a_opcode,
-        /* 3b */ NULL,
+        /* 3b */ ND_NULL,
         /* 3c */ (const void *)&gRootTable_root_0f_3c_leaf,
         /* 3d */ (const void *)&gRootTable_root_0f_3d_leaf,
-        /* 3e */ NULL,
+        /* 3e */ ND_NULL,
         /* 3f */ (const void *)&gRootTable_root_0f_3f_leaf,
         /* 40 */ (const void *)&gRootTable_root_0f_40_leaf,
         /* 41 */ (const void *)&gRootTable_root_0f_41_leaf,
@@ -11668,11 +11668,11 @@ const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_63_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gRootTable_root_63_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -11687,7 +11687,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_62_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -11750,7 +11750,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg =
         /* 04 */ (const void *)&gRootTable_root_ff_mem_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_ff_mem_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_ff_mem_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11791,11 +11791,11 @@ const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg =
         /* 00 */ (const void *)&gRootTable_root_ff_reg_00_leaf,
         /* 01 */ (const void *)&gRootTable_root_ff_reg_01_leaf,
         /* 02 */ (const void *)&gRootTable_root_ff_reg_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_ff_reg_04_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_ff_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -11836,12 +11836,12 @@ const ND_TABLE_DSIZE gRootTable_root_98_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_98_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_98_ds32_leaf,
         /* 03 */ (const void *)&gRootTable_root_98_ds64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -11867,12 +11867,12 @@ const ND_TABLE_DSIZE gRootTable_root_99_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_99_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_99_ds32_leaf,
         /* 03 */ (const void *)&gRootTable_root_99_ds64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -11953,10 +11953,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a6_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a6_rep_leaf,
     }
 };
@@ -11978,10 +11978,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a7_ds32_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a7_ds32_rep_leaf,
     }
 };
@@ -12003,10 +12003,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a7_ds64_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a7_ds64_rep_leaf,
     }
 };
@@ -12028,10 +12028,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a7_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a7_ds16_rep_leaf,
     }
 };
@@ -12040,12 +12040,12 @@ const ND_TABLE_DSIZE gRootTable_root_a7_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_a7_ds16_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_a7_ds32_auxiliary,
         /* 03 */ (const void *)&gRootTable_root_a7_ds64_auxiliary,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -12127,12 +12127,12 @@ const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg =
     { 
         /* 00 */ (const void *)&gRootTable_root_fe_00_leaf,
         /* 01 */ (const void *)&gRootTable_root_fe_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -12361,12 +12361,12 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm =
     { 
         /* 00 */ (const void *)&gRootTable_root_d9_reg_04_00_leaf,
         /* 01 */ (const void *)&gRootTable_root_d9_reg_04_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_d9_reg_04_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_d9_reg_04_05_leaf,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -12492,7 +12492,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm =
         /* 04 */ (const void *)&gRootTable_root_d9_reg_05_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_d9_reg_05_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_d9_reg_05_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -12507,13 +12507,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_d9_reg_02_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -12591,7 +12591,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_d9_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gRootTable_root_d9_mem_02_leaf,
         /* 03 */ (const void *)&gRootTable_root_d9_mem_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_d9_mem_04_leaf,
@@ -12902,14 +12902,14 @@ const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm =
 {
     ND_ILUT_MODRM_RM,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_de_reg_03_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13130,11 +13130,11 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm =
         /* 00 */ (const void *)&gRootTable_root_df_reg_04_00_leaf,
         /* 01 */ (const void *)&gRootTable_root_df_reg_04_01_leaf,
         /* 02 */ (const void *)&gRootTable_root_df_reg_04_02_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13148,14 +13148,14 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm =
 {
     ND_ILUT_MODRM_RM,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_df_reg_07_04_leaf,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13241,14 +13241,14 @@ const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm =
 {
     ND_ILUT_MODRM_RM,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_da_reg_05_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13260,10 +13260,10 @@ const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg =
         /* 01 */ (const void *)&gRootTable_root_da_reg_01_leaf,
         /* 02 */ (const void *)&gRootTable_root_da_reg_02_leaf,
         /* 03 */ (const void *)&gRootTable_root_da_reg_03_leaf,
-        /* 04 */ NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_da_reg_05_modrmrm,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13408,9 +13408,9 @@ const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm =
         /* 02 */ (const void *)&gRootTable_root_db_reg_04_02_leaf,
         /* 03 */ (const void *)&gRootTable_root_db_reg_04_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_db_reg_04_04_leaf,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13431,7 +13431,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg =
         /* 04 */ (const void *)&gRootTable_root_db_reg_04_modrmrm,
         /* 05 */ (const void *)&gRootTable_root_db_reg_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_db_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13479,9 +13479,9 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg =
         /* 01 */ (const void *)&gRootTable_root_db_mem_01_leaf,
         /* 02 */ (const void *)&gRootTable_root_db_mem_02_leaf,
         /* 03 */ (const void *)&gRootTable_root_db_mem_03_leaf,
-        /* 04 */ NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_db_mem_05_leaf,
-        /* 06 */ NULL,
+        /* 06 */ ND_NULL,
         /* 07 */ (const void *)&gRootTable_root_db_mem_07_leaf,
     }
 };
@@ -13541,8 +13541,8 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg =
         /* 03 */ (const void *)&gRootTable_root_dd_reg_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_dd_reg_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_dd_reg_05_leaf,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -13597,7 +13597,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg =
         /* 02 */ (const void *)&gRootTable_root_dd_mem_02_leaf,
         /* 03 */ (const void *)&gRootTable_root_dd_mem_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_dd_mem_04_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gRootTable_root_dd_mem_06_leaf,
         /* 07 */ (const void *)&gRootTable_root_dd_mem_07_leaf,
     }
@@ -13719,10 +13719,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6c_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6c_rep_leaf,
     }
 };
@@ -13744,10 +13744,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6d_None_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6d_None_rep_leaf,
     }
 };
@@ -13769,10 +13769,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6d_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6d_ds16_rep_leaf,
     }
 };
@@ -13783,10 +13783,10 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize =
     { 
         /* 00 */ (const void *)&gRootTable_root_6d_None_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_6d_ds16_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -13836,12 +13836,12 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_cf_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_cf_ds32_leaf,
         /* 03 */ (const void *)&gRootTable_root_cf_ds64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -13879,7 +13879,7 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize =
 {
     ND_ILUT_ASIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_e3_as16_leaf,
         /* 02 */ (const void *)&gRootTable_root_e3_as32_leaf,
         /* 03 */ (const void *)&gRootTable_root_e3_as64_leaf,
@@ -14005,7 +14005,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_c5_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14020,7 +14020,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_8d_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14041,7 +14041,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gRootTable_root_c4_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -14062,10 +14062,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ac_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ac_rep_leaf,
     }
 };
@@ -14087,10 +14087,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ad_ds32_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ad_ds32_rep_leaf,
     }
 };
@@ -14112,10 +14112,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ad_ds64_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ad_ds64_rep_leaf,
     }
 };
@@ -14137,10 +14137,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ad_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ad_ds16_rep_leaf,
     }
 };
@@ -14149,12 +14149,12 @@ const ND_TABLE_DSIZE gRootTable_root_ad_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_ad_ds16_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_ad_ds32_auxiliary,
         /* 03 */ (const void *)&gRootTable_root_ad_ds64_auxiliary,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -14373,13 +14373,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_c6_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -14400,13 +14400,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_c6_reg_07_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -14415,12 +14415,12 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_reg_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_c6_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
         /* 07 */ (const void *)&gRootTable_root_c6_reg_07_modrmrm,
     }
 };
@@ -14445,13 +14445,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_c7_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -14472,13 +14472,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gRootTable_root_c7_reg_07_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -14487,12 +14487,12 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_reg_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_c7_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
         /* 07 */ (const void *)&gRootTable_root_c7_reg_07_modrmrm,
     }
 };
@@ -14523,10 +14523,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a4_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a4_rep_leaf,
     }
 };
@@ -14548,10 +14548,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a5_ds32_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a5_ds32_rep_leaf,
     }
 };
@@ -14573,10 +14573,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a5_ds64_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a5_ds64_rep_leaf,
     }
 };
@@ -14598,10 +14598,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_a5_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_a5_ds16_rep_leaf,
     }
 };
@@ -14610,12 +14610,12 @@ const ND_TABLE_DSIZE gRootTable_root_a5_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_a5_ds16_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_a5_ds32_auxiliary,
         /* 03 */ (const void *)&gRootTable_root_a5_ds64_auxiliary,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -14643,10 +14643,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
     { 
         /* 00 */ (const void *)&gRootTable_root_90_None_leaf,
         /* 01 */ (const void *)&gRootTable_root_90_rexb_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_90_aF3_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -14727,10 +14727,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6e_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6e_rep_leaf,
     }
 };
@@ -14752,10 +14752,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6f_None_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6f_None_rep_leaf,
     }
 };
@@ -14777,10 +14777,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_6f_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_6f_ds16_rep_leaf,
     }
 };
@@ -14791,10 +14791,10 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize =
     { 
         /* 00 */ (const void *)&gRootTable_root_6f_None_auxiliary,
         /* 01 */ (const void *)&gRootTable_root_6f_ds16_auxiliary,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -14875,13 +14875,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gRootTable_root_8f_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -14901,12 +14901,12 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_61_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_61_ds32_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -14932,12 +14932,12 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_9d_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_9d_ds32_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_9d_dds64_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -15041,12 +15041,12 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_60_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_60_ds32_leaf,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -15072,12 +15072,12 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_9c_ds16_leaf,
         /* 02 */ (const void *)&gRootTable_root_9c_ds32_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gRootTable_root_9c_dds64_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -15548,10 +15548,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ae_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ae_rep_leaf,
     }
 };
@@ -15573,10 +15573,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_af_ds32_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_af_ds32_rep_leaf,
     }
 };
@@ -15598,10 +15598,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_af_ds64_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_af_ds64_rep_leaf,
     }
 };
@@ -15623,10 +15623,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_af_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_af_ds16_rep_leaf,
     }
 };
@@ -15635,12 +15635,12 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_af_ds16_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_af_ds32_auxiliary,
         /* 03 */ (const void *)&gRootTable_root_af_ds64_auxiliary,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -15679,10 +15679,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_aa_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_aa_rep_leaf,
     }
 };
@@ -15704,10 +15704,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ab_ds32_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ab_ds32_rep_leaf,
     }
 };
@@ -15729,10 +15729,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ab_ds64_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ab_ds64_rep_leaf,
     }
 };
@@ -15754,10 +15754,10 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary =
     ND_ILUT_AUXILIARY,
     { 
         /* 00 */ (const void *)&gRootTable_root_ab_ds16_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
         /* 05 */ (const void *)&gRootTable_root_ab_ds16_rep_leaf,
     }
 };
@@ -15766,12 +15766,12 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize =
 {
     ND_ILUT_DSIZE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gRootTable_root_ab_ds16_auxiliary,
         /* 02 */ (const void *)&gRootTable_root_ab_ds32_auxiliary,
         /* 03 */ (const void *)&gRootTable_root_ab_ds64_auxiliary,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
     }
 };
 
@@ -15979,7 +15979,7 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 23 */ (const void *)&gRootTable_root_23_leaf,
         /* 24 */ (const void *)&gRootTable_root_24_leaf,
         /* 25 */ (const void *)&gRootTable_root_25_leaf,
-        /* 26 */ NULL,
+        /* 26 */ ND_NULL,
         /* 27 */ (const void *)&gRootTable_root_27_leaf,
         /* 28 */ (const void *)&gRootTable_root_28_leaf,
         /* 29 */ (const void *)&gRootTable_root_29_leaf,
@@ -15987,7 +15987,7 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 2b */ (const void *)&gRootTable_root_2b_leaf,
         /* 2c */ (const void *)&gRootTable_root_2c_leaf,
         /* 2d */ (const void *)&gRootTable_root_2d_leaf,
-        /* 2e */ NULL,
+        /* 2e */ ND_NULL,
         /* 2f */ (const void *)&gRootTable_root_2f_leaf,
         /* 30 */ (const void *)&gRootTable_root_30_leaf,
         /* 31 */ (const void *)&gRootTable_root_31_leaf,
@@ -15995,7 +15995,7 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 33 */ (const void *)&gRootTable_root_33_leaf,
         /* 34 */ (const void *)&gRootTable_root_34_leaf,
         /* 35 */ (const void *)&gRootTable_root_35_leaf,
-        /* 36 */ NULL,
+        /* 36 */ ND_NULL,
         /* 37 */ (const void *)&gRootTable_root_37_leaf,
         /* 38 */ (const void *)&gRootTable_root_38_leaf,
         /* 39 */ (const void *)&gRootTable_root_39_leaf,
@@ -16003,7 +16003,7 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 3b */ (const void *)&gRootTable_root_3b_leaf,
         /* 3c */ (const void *)&gRootTable_root_3c_leaf,
         /* 3d */ (const void *)&gRootTable_root_3d_leaf,
-        /* 3e */ NULL,
+        /* 3e */ ND_NULL,
         /* 3f */ (const void *)&gRootTable_root_3f_leaf,
         /* 40 */ (const void *)&gRootTable_root_40_leaf,
         /* 41 */ (const void *)&gRootTable_root_41_leaf,
@@ -16041,10 +16041,10 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 61 */ (const void *)&gRootTable_root_61_dsize,
         /* 62 */ (const void *)&gRootTable_root_62_modrmmod,
         /* 63 */ (const void *)&gRootTable_root_63_auxiliary,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
         /* 68 */ (const void *)&gRootTable_root_68_leaf,
         /* 69 */ (const void *)&gRootTable_root_69_leaf,
         /* 6a */ (const void *)&gRootTable_root_6a_leaf,
@@ -16181,10 +16181,10 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* ed */ (const void *)&gRootTable_root_ed_leaf,
         /* ee */ (const void *)&gRootTable_root_ee_leaf,
         /* ef */ (const void *)&gRootTable_root_ef_leaf,
-        /* f0 */ NULL,
+        /* f0 */ ND_NULL,
         /* f1 */ (const void *)&gRootTable_root_f1_leaf,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
         /* f4 */ (const void *)&gRootTable_root_f4_leaf,
         /* f5 */ (const void *)&gRootTable_root_f5_leaf,
         /* f6 */ (const void *)&gRootTable_root_f6_modrmreg,
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
index 49f2acd..66ba995 100644
--- a/bddisasm/include/table_vex.h
+++ b/bddisasm/include/table_vex.h
@@ -12,9 +12,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f2_00_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -23,9 +23,9 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f2_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -40,9 +40,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f7_00_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -57,9 +57,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f7_02_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -74,9 +74,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f7_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -91,9 +91,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f7_03_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -119,9 +119,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f3_00_03_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -136,9 +136,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f3_00_02_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -153,9 +153,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f3_00_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -163,14 +163,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_f3_00_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_f3_00_01_l,
         /* 02 */ (const void *)&gVexTable_root_02_f3_00_02_l,
         /* 03 */ (const void *)&gVexTable_root_02_f3_00_03_l,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -179,9 +179,9 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f3_00_modrmreg,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -196,9 +196,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f5_00_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -213,9 +213,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f5_03_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -230,9 +230,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f5_02_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -241,7 +241,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f5_00_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_02_f5_02_l,
         /* 03 */ (const void *)&gVexTable_root_02_f5_03_l,
     }
@@ -258,7 +258,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -267,9 +267,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_49_00_mem_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -278,13 +278,13 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -299,7 +299,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -308,9 +308,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_49_00_reg_00_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -319,13 +319,13 @@ const ND_TABLE_MODRM_RM gVexTable_root_02_49_00_reg_00_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -334,13 +334,13 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_reg_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_modrmrm,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -364,7 +364,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -373,9 +373,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_49_01_mem_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_01_mem_modrmreg =
     ND_ILUT_MODRM_REG,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -399,7 +399,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_modrmreg,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -414,7 +414,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -423,9 +423,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_49_03_reg_00_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -434,13 +434,13 @@ const ND_TABLE_MODRM_RM gVexTable_root_02_49_03_reg_modrmrm =
     ND_ILUT_MODRM_RM,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -448,7 +448,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_03_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_49_03_reg_modrmrm,
     }
 };
@@ -459,7 +459,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_49_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_49_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_02_49_01_modrmmod,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_02_49_03_modrmmod,
     }
 };
@@ -475,9 +475,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_f6_03_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -485,9 +485,9 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_02_f6_03_l,
     }
 };
@@ -503,7 +503,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -512,9 +512,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_5c_02_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -522,7 +522,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5c_02_reg_l,
     }
 };
@@ -531,10 +531,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_02_5c_02_modrmmod,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -549,7 +549,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -558,9 +558,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_5e_03_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -568,7 +568,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5e_03_reg_l,
     }
 };
@@ -584,7 +584,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -593,9 +593,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_5e_02_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -603,7 +603,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5e_02_reg_l,
     }
 };
@@ -619,7 +619,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -628,9 +628,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_5e_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -638,7 +638,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5e_01_reg_l,
     }
 };
@@ -654,7 +654,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -663,9 +663,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_5e_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -673,7 +673,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5e_00_reg_l,
     }
 };
@@ -700,7 +700,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -709,9 +709,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_4b_03_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -720,7 +720,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -735,7 +735,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -744,9 +744,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_4b_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -755,7 +755,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -770,7 +770,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -779,9 +779,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_4b_02_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -790,7 +790,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_02_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -798,7 +798,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_4b_01_modrmmod,
         /* 02 */ (const void *)&gVexTable_root_02_4b_02_modrmmod,
         /* 03 */ (const void *)&gVexTable_root_02_4b_03_modrmmod,
@@ -815,10 +815,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_de_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -832,10 +832,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_df_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -849,10 +849,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_dc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -866,10 +866,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_dd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -884,9 +884,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_db_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_db_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -894,10 +894,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_db_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -912,7 +912,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -920,10 +920,10 @@ const ND_TABLE_VEX_L gVexTable_root_02_1a_01_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_1a_01_mem_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -932,7 +932,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_1a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -940,10 +940,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_1a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -958,7 +958,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -966,10 +966,10 @@ const ND_TABLE_VEX_L gVexTable_root_02_5a_01_mem_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5a_01_mem_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -978,7 +978,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -986,10 +986,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_5a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1004,7 +1004,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_19_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_19_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1012,10 +1012,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_19_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1030,7 +1030,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_18_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_18_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1038,10 +1038,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_18_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1056,7 +1056,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_13_01_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1071,7 +1071,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_13_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -1081,8 +1081,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_13_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_13_01_00_w,
         /* 01 */ (const void *)&gVexTable_root_02_13_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1090,10 +1090,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_13_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1122,10 +1122,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_98_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1154,10 +1154,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_99_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1186,10 +1186,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_a8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1218,10 +1218,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_a9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1250,10 +1250,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_b8_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1282,10 +1282,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_b9_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1314,10 +1314,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_96_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1346,10 +1346,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_a6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1378,10 +1378,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_b6_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1410,10 +1410,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1442,10 +1442,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1474,10 +1474,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_aa_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1506,10 +1506,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_ab_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1538,10 +1538,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_ba_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1570,10 +1570,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_bb_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1602,10 +1602,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_97_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1634,10 +1634,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_a7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1666,10 +1666,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_b7_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1698,10 +1698,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1730,10 +1730,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1762,10 +1762,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_ac_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1794,10 +1794,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_ad_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1826,10 +1826,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_bc_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1858,10 +1858,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_bd_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1890,10 +1890,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1922,10 +1922,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_9f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1954,10 +1954,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_ae_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -1986,10 +1986,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_af_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2018,10 +2018,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_be_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2050,10 +2050,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_bf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2083,7 +2083,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_92_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_92_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2091,10 +2091,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_92_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2124,7 +2124,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_93_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_93_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2132,10 +2132,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_93_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2150,7 +2150,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_cf_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2158,10 +2158,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_cf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2176,7 +2176,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2185,7 +2185,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_2d_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2193,10 +2193,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2d_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2211,7 +2211,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2220,7 +2220,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_2f_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2228,10 +2228,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2f_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2246,7 +2246,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2255,7 +2255,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_2c_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2263,10 +2263,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2c_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2281,7 +2281,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2290,7 +2290,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_2e_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2298,10 +2298,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2e_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2316,7 +2316,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_2a_01_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2324,10 +2324,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2341,10 +2341,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_1c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2358,10 +2358,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_1e_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2375,10 +2375,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_1d_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2392,10 +2392,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_2b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2410,7 +2410,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_78_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_78_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2418,10 +2418,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_78_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2436,7 +2436,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_58_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_58_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2444,10 +2444,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_58_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2462,7 +2462,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_59_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_59_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2470,10 +2470,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_59_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2488,7 +2488,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_79_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_79_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2496,10 +2496,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_79_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2513,10 +2513,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_29_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2530,10 +2530,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_37_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2548,7 +2548,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_50_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2556,10 +2556,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_50_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_50_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2574,7 +2574,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_51_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2582,10 +2582,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_51_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_51_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2600,7 +2600,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_52_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_52_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2608,10 +2608,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_52_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_52_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2626,7 +2626,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_53_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_53_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2634,10 +2634,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_53_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_53_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2652,7 +2652,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_36_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2660,10 +2660,10 @@ const ND_TABLE_VEX_L gVexTable_root_02_36_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_36_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2671,10 +2671,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_36_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2689,7 +2689,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_0d_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2697,10 +2697,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2715,7 +2715,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_0c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2723,10 +2723,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2741,7 +2741,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_16_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2749,10 +2749,10 @@ const ND_TABLE_VEX_L gVexTable_root_02_16_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_16_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2760,10 +2760,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_16_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2793,7 +2793,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_90_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_90_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2801,10 +2801,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_90_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2834,7 +2834,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_91_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_91_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -2842,10 +2842,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_91_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2859,10 +2859,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_02_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2876,10 +2876,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_03_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2893,10 +2893,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2911,9 +2911,9 @@ const ND_TABLE_VEX_L gVexTable_root_02_41_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_41_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2921,10 +2921,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_41_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2938,10 +2938,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_06_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2955,10 +2955,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_07_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2972,10 +2972,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_05_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -2989,10 +2989,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_04_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3022,7 +3022,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_8c_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_8c_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3030,10 +3030,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_8c_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3063,7 +3063,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_8e_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_8e_01_mem_w,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3071,10 +3071,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_8e_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3088,10 +3088,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3105,10 +3105,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3d_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3122,10 +3122,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3f_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3139,10 +3139,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3e_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3156,10 +3156,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_38_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3173,10 +3173,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_39_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3190,10 +3190,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3207,10 +3207,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_3a_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3232,8 +3232,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_21_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_21_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_21_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3241,10 +3241,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_21_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3266,8 +3266,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_22_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_22_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_22_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3275,10 +3275,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_22_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3300,8 +3300,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_20_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_20_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_20_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3309,10 +3309,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_20_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3334,8 +3334,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_25_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_25_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_25_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3343,10 +3343,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_25_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3368,8 +3368,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_23_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_23_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_23_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3377,10 +3377,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_23_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3402,8 +3402,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_24_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_24_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_24_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3411,10 +3411,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_24_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3436,8 +3436,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_31_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_31_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_31_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3445,10 +3445,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_31_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3470,8 +3470,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_32_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_32_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_32_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3479,10 +3479,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_32_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3504,8 +3504,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_30_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_30_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_30_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3513,10 +3513,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_30_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3538,8 +3538,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_35_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_35_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_35_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3547,10 +3547,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_35_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3572,8 +3572,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_33_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_33_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_33_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3581,10 +3581,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_33_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3606,8 +3606,8 @@ const ND_TABLE_VEX_L gVexTable_root_02_34_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_02_34_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_02_34_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3615,10 +3615,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_34_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3632,10 +3632,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_28_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3649,10 +3649,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3666,10 +3666,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_40_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3683,10 +3683,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_00_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3700,10 +3700,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_08_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3717,10 +3717,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0a_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3734,10 +3734,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_09_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3766,10 +3766,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_47_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3784,7 +3784,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_46_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_46_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3792,10 +3792,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_46_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3824,10 +3824,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_45_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3841,10 +3841,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_17_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3859,7 +3859,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_0f_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3867,10 +3867,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3885,7 +3885,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_02_0e_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -3893,10 +3893,10 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_02_0e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -3920,30 +3920,30 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* 0d */ (const void *)&gVexTable_root_02_0d_pp,
         /* 0e */ (const void *)&gVexTable_root_02_0e_pp,
         /* 0f */ (const void *)&gVexTable_root_02_0f_pp,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
         /* 13 */ (const void *)&gVexTable_root_02_13_pp,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
         /* 16 */ (const void *)&gVexTable_root_02_16_pp,
         /* 17 */ (const void *)&gVexTable_root_02_17_pp,
         /* 18 */ (const void *)&gVexTable_root_02_18_pp,
         /* 19 */ (const void *)&gVexTable_root_02_19_pp,
         /* 1a */ (const void *)&gVexTable_root_02_1a_pp,
-        /* 1b */ NULL,
+        /* 1b */ ND_NULL,
         /* 1c */ (const void *)&gVexTable_root_02_1c_pp,
         /* 1d */ (const void *)&gVexTable_root_02_1d_pp,
         /* 1e */ (const void *)&gVexTable_root_02_1e_pp,
-        /* 1f */ NULL,
+        /* 1f */ ND_NULL,
         /* 20 */ (const void *)&gVexTable_root_02_20_pp,
         /* 21 */ (const void *)&gVexTable_root_02_21_pp,
         /* 22 */ (const void *)&gVexTable_root_02_22_pp,
         /* 23 */ (const void *)&gVexTable_root_02_23_pp,
         /* 24 */ (const void *)&gVexTable_root_02_24_pp,
         /* 25 */ (const void *)&gVexTable_root_02_25_pp,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
         /* 28 */ (const void *)&gVexTable_root_02_28_pp,
         /* 29 */ (const void *)&gVexTable_root_02_29_pp,
         /* 2a */ (const void *)&gVexTable_root_02_2a_pp,
@@ -3970,90 +3970,90 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* 3f */ (const void *)&gVexTable_root_02_3f_pp,
         /* 40 */ (const void *)&gVexTable_root_02_40_pp,
         /* 41 */ (const void *)&gVexTable_root_02_41_pp,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
         /* 45 */ (const void *)&gVexTable_root_02_45_pp,
         /* 46 */ (const void *)&gVexTable_root_02_46_pp,
         /* 47 */ (const void *)&gVexTable_root_02_47_pp,
-        /* 48 */ NULL,
+        /* 48 */ ND_NULL,
         /* 49 */ (const void *)&gVexTable_root_02_49_pp,
-        /* 4a */ NULL,
+        /* 4a */ ND_NULL,
         /* 4b */ (const void *)&gVexTable_root_02_4b_pp,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
         /* 50 */ (const void *)&gVexTable_root_02_50_pp,
         /* 51 */ (const void *)&gVexTable_root_02_51_pp,
         /* 52 */ (const void *)&gVexTable_root_02_52_pp,
         /* 53 */ (const void *)&gVexTable_root_02_53_pp,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
         /* 58 */ (const void *)&gVexTable_root_02_58_pp,
         /* 59 */ (const void *)&gVexTable_root_02_59_pp,
         /* 5a */ (const void *)&gVexTable_root_02_5a_pp,
-        /* 5b */ NULL,
+        /* 5b */ ND_NULL,
         /* 5c */ (const void *)&gVexTable_root_02_5c_pp,
-        /* 5d */ NULL,
+        /* 5d */ ND_NULL,
         /* 5e */ (const void *)&gVexTable_root_02_5e_pp,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
         /* 78 */ (const void *)&gVexTable_root_02_78_pp,
         /* 79 */ (const void *)&gVexTable_root_02_79_pp,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
         /* 8c */ (const void *)&gVexTable_root_02_8c_pp,
-        /* 8d */ NULL,
+        /* 8d */ ND_NULL,
         /* 8e */ (const void *)&gVexTable_root_02_8e_pp,
-        /* 8f */ NULL,
+        /* 8f */ ND_NULL,
         /* 90 */ (const void *)&gVexTable_root_02_90_pp,
         /* 91 */ (const void *)&gVexTable_root_02_91_pp,
         /* 92 */ (const void *)&gVexTable_root_02_92_pp,
         /* 93 */ (const void *)&gVexTable_root_02_93_pp,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
         /* 96 */ (const void *)&gVexTable_root_02_96_pp,
         /* 97 */ (const void *)&gVexTable_root_02_97_pp,
         /* 98 */ (const void *)&gVexTable_root_02_98_pp,
@@ -4064,12 +4064,12 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* 9d */ (const void *)&gVexTable_root_02_9d_pp,
         /* 9e */ (const void *)&gVexTable_root_02_9e_pp,
         /* 9f */ (const void *)&gVexTable_root_02_9f_pp,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
         /* a6 */ (const void *)&gVexTable_root_02_a6_pp,
         /* a7 */ (const void *)&gVexTable_root_02_a7_pp,
         /* a8 */ (const void *)&gVexTable_root_02_a8_pp,
@@ -4080,12 +4080,12 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* ad */ (const void *)&gVexTable_root_02_ad_pp,
         /* ae */ (const void *)&gVexTable_root_02_ae_pp,
         /* af */ (const void *)&gVexTable_root_02_af_pp,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
         /* b6 */ (const void *)&gVexTable_root_02_b6_pp,
         /* b7 */ (const void *)&gVexTable_root_02_b7_pp,
         /* b8 */ (const void *)&gVexTable_root_02_b8_pp,
@@ -4096,70 +4096,70 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* bd */ (const void *)&gVexTable_root_02_bd_pp,
         /* be */ (const void *)&gVexTable_root_02_be_pp,
         /* bf */ (const void *)&gVexTable_root_02_bf_pp,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
         /* cf */ (const void *)&gVexTable_root_02_cf_pp,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
         /* db */ (const void *)&gVexTable_root_02_db_pp,
         /* dc */ (const void *)&gVexTable_root_02_dc_pp,
         /* dd */ (const void *)&gVexTable_root_02_dd_pp,
         /* de */ (const void *)&gVexTable_root_02_de_pp,
         /* df */ (const void *)&gVexTable_root_02_df_pp,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
         /* f2 */ (const void *)&gVexTable_root_02_f2_pp,
         /* f3 */ (const void *)&gVexTable_root_02_f3_pp,
-        /* f4 */ NULL,
+        /* f4 */ ND_NULL,
         /* f5 */ (const void *)&gVexTable_root_02_f5_pp,
         /* f6 */ (const void *)&gVexTable_root_02_f6_pp,
         /* f7 */ (const void *)&gVexTable_root_02_f7_pp,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -4173,13 +4173,13 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
         /* 07 */ (const void *)&gVexTable_root_01_ae_03_mem_07_leaf,
     }
 };
@@ -4194,14 +4194,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gVexTable_root_01_ae_03_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -4224,13 +4224,13 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
         /* 07 */ (const void *)&gVexTable_root_01_ae_02_mem_07_leaf,
     }
 };
@@ -4245,14 +4245,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gVexTable_root_01_ae_02_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -4281,14 +4281,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_ae_00_mem_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_ae_00_mem_03_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -4297,7 +4297,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_ae_00_mem_modrmreg,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4306,7 +4306,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_ae_00_modrmmod,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_ae_02_modrmmod,
         /* 03 */ (const void *)&gVexTable_root_01_ae_03_modrmmod,
     }
@@ -4337,10 +4337,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_4a_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4348,7 +4348,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_l,
     }
 };
@@ -4378,10 +4378,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_4a_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4389,7 +4389,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_l,
     }
 };
@@ -4400,8 +4400,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_4a_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_4a_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4430,10 +4430,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_41_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4441,7 +4441,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_l,
     }
 };
@@ -4471,10 +4471,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_41_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4482,7 +4482,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_l,
     }
 };
@@ -4493,8 +4493,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_41_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_41_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4523,10 +4523,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_42_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4534,7 +4534,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_l,
     }
 };
@@ -4564,10 +4564,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_42_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4575,7 +4575,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_l,
     }
 };
@@ -4586,8 +4586,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_42_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_42_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4602,7 +4602,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4611,9 +4611,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_48_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4621,7 +4621,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_48_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_48_00_reg_l,
     }
 };
@@ -4631,9 +4631,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_48_00_modrmmod,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4648,7 +4648,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4657,9 +4657,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_49_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4667,7 +4667,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_49_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_49_00_reg_l,
     }
 };
@@ -4677,9 +4677,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_49_00_modrmmod,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4709,9 +4709,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4741,9 +4741,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_90_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4782,9 +4782,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4814,9 +4814,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_90_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4835,8 +4835,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_90_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_90_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4866,9 +4866,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_91_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4877,7 +4877,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4907,9 +4907,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_91_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4918,7 +4918,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4928,8 +4928,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_91_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_91_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4944,7 +4944,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -4953,9 +4953,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_92_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -4963,7 +4963,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_92_01_reg_l,
     }
 };
@@ -4994,9 +4994,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_92_03_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_03_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5004,7 +5004,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_92_03_reg_l,
     }
 };
@@ -5020,7 +5020,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5029,9 +5029,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_92_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5039,7 +5039,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_92_00_reg_l,
     }
 };
@@ -5050,7 +5050,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_92_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_92_01_modrmmod,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_92_03_modrmmod,
     }
 };
@@ -5066,7 +5066,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5075,9 +5075,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_93_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5085,7 +5085,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_93_01_reg_l,
     }
 };
@@ -5116,9 +5116,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_93_03_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_03_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5126,7 +5126,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_93_03_reg_l,
     }
 };
@@ -5142,7 +5142,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5151,9 +5151,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_93_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5161,7 +5161,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_93_00_reg_l,
     }
 };
@@ -5172,7 +5172,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_93_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_93_01_modrmmod,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_93_03_modrmmod,
     }
 };
@@ -5203,9 +5203,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_44_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_44_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5213,7 +5213,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_44_01_reg_l,
     }
 };
@@ -5244,9 +5244,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_44_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_44_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5254,7 +5254,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_44_00_reg_l,
     }
 };
@@ -5265,8 +5265,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_44_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_44_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5295,10 +5295,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_45_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5306,7 +5306,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_l,
     }
 };
@@ -5336,10 +5336,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_45_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5347,7 +5347,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_l,
     }
 };
@@ -5358,8 +5358,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_45_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_45_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5389,9 +5389,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_98_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_98_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5399,7 +5399,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_98_01_reg_l,
     }
 };
@@ -5430,9 +5430,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_98_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_98_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5440,7 +5440,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_98_00_reg_l,
     }
 };
@@ -5451,8 +5451,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_98_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_98_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5482,9 +5482,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_99_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_99_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5492,7 +5492,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_99_01_reg_l,
     }
 };
@@ -5523,9 +5523,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_99_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_99_00_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5533,7 +5533,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_99_00_reg_l,
     }
 };
@@ -5544,8 +5544,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_99_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_99_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5560,7 +5560,7 @@ const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_4b_01_reg_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -5568,10 +5568,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_4b_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5579,7 +5579,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_l,
     }
 };
@@ -5609,10 +5609,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_4b_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5620,7 +5620,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_l,
     }
 };
@@ -5631,8 +5631,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_4b_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_4b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5661,10 +5661,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_46_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5672,7 +5672,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_l,
     }
 };
@@ -5702,10 +5702,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_46_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5713,7 +5713,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_l,
     }
 };
@@ -5724,8 +5724,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_46_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_46_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5754,10 +5754,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_47_01_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5765,7 +5765,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_l,
     }
 };
@@ -5795,10 +5795,10 @@ const ND_TABLE_VEX_L gVexTable_root_01_47_00_reg_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5806,7 +5806,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_l,
     }
 };
@@ -5817,8 +5817,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_47_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_47_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5873,9 +5873,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d0_01_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_d0_03_leaf,
     }
 };
@@ -5898,8 +5898,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_55_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_55_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5921,8 +5921,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_54_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_54_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -5979,8 +5979,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_2f_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_2f_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6002,8 +6002,8 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_e6_02_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_e6_02_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6023,7 +6023,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e6_01_leaf,
         /* 02 */ (const void *)&gVexTable_root_01_e6_02_l,
         /* 03 */ (const void *)&gVexTable_root_01_e6_03_leaf,
@@ -6055,7 +6055,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp =
         /* 00 */ (const void *)&gVexTable_root_01_5b_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_5b_01_leaf,
         /* 02 */ (const void *)&gVexTable_root_01_5b_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6077,8 +6077,8 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_5a_01_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_5a_01_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6100,8 +6100,8 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_5a_00_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_5a_00_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6144,8 +6144,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_2d_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_2d_03_leaf,
     }
@@ -6167,8 +6167,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_2a_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_2a_03_leaf,
     }
@@ -6190,8 +6190,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_2c_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_2c_03_leaf,
     }
@@ -6248,9 +6248,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_7c_01_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_7c_03_leaf,
     }
 };
@@ -6271,9 +6271,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_7d_01_leaf,
-        /* 02 */ NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_7d_03_leaf,
     }
 };
@@ -6289,7 +6289,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_f0_03_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6297,9 +6297,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_01_f0_03_modrmmod,
     }
 };
@@ -6315,9 +6315,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_f7_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6325,7 +6325,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_f7_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f7_01_reg_l,
     }
 };
@@ -6334,10 +6334,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f7_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6429,8 +6429,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_28_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_28_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6452,8 +6452,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_29_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_29_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6483,9 +6483,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_6e_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_6e_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6493,10 +6493,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6e_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6526,9 +6526,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_7e_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6543,9 +6543,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_7e_02_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6553,10 +6553,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_7e_01_l,
         /* 02 */ (const void *)&gVexTable_root_01_7e_02_l,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6578,8 +6578,8 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_12_03_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_12_03_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6594,9 +6594,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_12_00_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6611,9 +6611,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_12_00_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6637,9 +6637,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6648,7 +6648,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6685,10 +6685,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6f_01_leaf,
         /* 02 */ (const void *)&gVexTable_root_01_6f_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6708,10 +6708,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_7f_01_leaf,
         /* 02 */ (const void *)&gVexTable_root_01_7f_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6726,9 +6726,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6737,7 +6737,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6752,9 +6752,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_16_00_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6769,9 +6769,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_16_00_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6797,7 +6797,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp =
         /* 00 */ (const void *)&gVexTable_root_01_16_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_16_01_modrmmod,
         /* 02 */ (const void *)&gVexTable_root_01_16_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6812,9 +6812,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6823,7 +6823,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6838,9 +6838,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6849,7 +6849,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6859,8 +6859,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_17_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_17_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6875,9 +6875,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6886,7 +6886,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6901,9 +6901,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6912,7 +6912,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_l,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6922,8 +6922,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_13_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_13_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6937,7 +6937,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_50_01_reg_leaf,
     }
 };
@@ -6952,7 +6952,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_50_00_reg_leaf,
     }
 };
@@ -6963,8 +6963,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_50_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_50_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -6979,7 +6979,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_e7_01_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -6987,10 +6987,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e7_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7005,7 +7005,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_2b_01_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7020,7 +7020,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod =
     ND_ILUT_MODRM_MOD,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_2b_00_mem_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -7030,8 +7030,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_2b_00_modrmmod,
         /* 01 */ (const void *)&gVexTable_root_01_2b_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7046,9 +7046,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_d6_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7056,10 +7056,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d6_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7246,8 +7246,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_56_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_56_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7261,10 +7261,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7278,10 +7278,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_63_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7295,10 +7295,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_67_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7312,10 +7312,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_fc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7329,10 +7329,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_fe_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7346,10 +7346,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d4_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7363,10 +7363,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_ec_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7380,10 +7380,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_ed_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7397,10 +7397,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_dc_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7414,10 +7414,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_dd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7431,10 +7431,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_fd_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7448,10 +7448,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_db_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7465,10 +7465,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_df_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7482,10 +7482,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e0_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7499,10 +7499,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e3_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7516,10 +7516,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_74_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7533,10 +7533,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_76_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7550,10 +7550,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_75_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7567,10 +7567,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_64_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7584,10 +7584,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_66_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7601,10 +7601,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_65_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7619,9 +7619,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7629,7 +7629,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_c5_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_c5_01_reg_l,
     }
 };
@@ -7638,10 +7638,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_c5_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7656,9 +7656,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7673,9 +7673,9 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7692,10 +7692,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_c4_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7709,10 +7709,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7726,10 +7726,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_ee_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7743,10 +7743,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_de_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7760,10 +7760,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_ea_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7777,10 +7777,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_da_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7794,7 +7794,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d7_01_reg_leaf,
     }
 };
@@ -7803,10 +7803,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d7_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7820,10 +7820,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e4_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7837,10 +7837,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7854,10 +7854,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d5_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7871,10 +7871,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f4_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7888,10 +7888,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_eb_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7905,10 +7905,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f6_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -7934,7 +7934,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_70_01_leaf,
         /* 02 */ (const void *)&gVexTable_root_01_70_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_70_03_leaf,
@@ -7963,14 +7963,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_72_01_reg_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gVexTable_root_01_72_01_reg_04_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gVexTable_root_01_72_01_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -7978,7 +7978,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_72_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_72_01_reg_modrmreg,
     }
 };
@@ -7987,10 +7987,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_72_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8004,10 +8004,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f2_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8039,12 +8039,12 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_73_01_reg_02_leaf,
         /* 03 */ (const void *)&gVexTable_root_01_73_01_reg_03_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gVexTable_root_01_73_01_reg_06_leaf,
         /* 07 */ (const void *)&gVexTable_root_01_73_01_reg_07_leaf,
     }
@@ -8054,7 +8054,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_73_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_73_01_reg_modrmreg,
     }
 };
@@ -8063,10 +8063,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_73_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8080,10 +8080,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f3_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8109,14 +8109,14 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_71_01_reg_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gVexTable_root_01_71_01_reg_04_leaf,
-        /* 05 */ NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gVexTable_root_01_71_01_reg_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -8124,7 +8124,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_71_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_71_01_reg_modrmreg,
     }
 };
@@ -8133,10 +8133,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_71_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8150,10 +8150,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8167,10 +8167,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e2_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8184,10 +8184,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8201,10 +8201,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d2_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8218,10 +8218,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d3_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8235,10 +8235,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d1_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8252,10 +8252,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8269,10 +8269,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_fa_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8286,10 +8286,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_fb_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8303,10 +8303,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8320,10 +8320,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_e9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8337,10 +8337,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d8_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8354,10 +8354,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_d9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8371,10 +8371,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_f9_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8388,10 +8388,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_68_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8405,10 +8405,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6a_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8422,10 +8422,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6d_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8439,10 +8439,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_69_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8456,10 +8456,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_60_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8473,10 +8473,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_62_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8490,10 +8490,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_6c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8507,10 +8507,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_61_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8524,10 +8524,10 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_ef_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8548,9 +8548,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_53_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_53_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8571,9 +8571,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_52_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
         /* 02 */ (const void *)&gVexTable_root_01_52_02_leaf,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8595,8 +8595,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_c6_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_c6_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8688,8 +8688,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_2e_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_2e_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8711,8 +8711,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_15_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_15_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8734,8 +8734,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_14_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_14_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8757,8 +8757,8 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_57_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_57_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8780,8 +8780,8 @@ const ND_TABLE_VEX_L gVexTable_root_01_77_00_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_01_77_00_00_leaf,
         /* 01 */ (const void *)&gVexTable_root_01_77_00_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8790,9 +8790,9 @@ const ND_TABLE_VEX_PP gVexTable_root_01_77_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ (const void *)&gVexTable_root_01_77_00_l,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -8800,22 +8800,22 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gVexTable_root_01_10_pp,
         /* 11 */ (const void *)&gVexTable_root_01_11_pp,
         /* 12 */ (const void *)&gVexTable_root_01_12_pp,
@@ -8824,22 +8824,22 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
         /* 15 */ (const void *)&gVexTable_root_01_15_pp,
         /* 16 */ (const void *)&gVexTable_root_01_16_pp,
         /* 17 */ (const void *)&gVexTable_root_01_17_pp,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
         /* 28 */ (const void *)&gVexTable_root_01_28_pp,
         /* 29 */ (const void *)&gVexTable_root_01_29_pp,
         /* 2a */ (const void *)&gVexTable_root_01_2a_pp,
@@ -8848,26 +8848,26 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
         /* 2d */ (const void *)&gVexTable_root_01_2d_pp,
         /* 2e */ (const void *)&gVexTable_root_01_2e_pp,
         /* 2f */ (const void *)&gVexTable_root_01_2f_pp,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
         /* 41 */ (const void *)&gVexTable_root_01_41_pp,
         /* 42 */ (const void *)&gVexTable_root_01_42_pp,
-        /* 43 */ NULL,
+        /* 43 */ ND_NULL,
         /* 44 */ (const void *)&gVexTable_root_01_44_pp,
         /* 45 */ (const void *)&gVexTable_root_01_45_pp,
         /* 46 */ (const void *)&gVexTable_root_01_46_pp,
@@ -8876,10 +8876,10 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
         /* 49 */ (const void *)&gVexTable_root_01_49_pp,
         /* 4a */ (const void *)&gVexTable_root_01_4a_pp,
         /* 4b */ (const void *)&gVexTable_root_01_4b_pp,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
         /* 50 */ (const void *)&gVexTable_root_01_50_pp,
         /* 51 */ (const void *)&gVexTable_root_01_51_pp,
         /* 52 */ (const void *)&gVexTable_root_01_52_pp,
@@ -8920,94 +8920,94 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
         /* 75 */ (const void *)&gVexTable_root_01_75_pp,
         /* 76 */ (const void *)&gVexTable_root_01_76_pp,
         /* 77 */ (const void *)&gVexTable_root_01_77_pp,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
         /* 7c */ (const void *)&gVexTable_root_01_7c_pp,
         /* 7d */ (const void *)&gVexTable_root_01_7d_pp,
         /* 7e */ (const void *)&gVexTable_root_01_7e_pp,
         /* 7f */ (const void *)&gVexTable_root_01_7f_pp,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
         /* 90 */ (const void *)&gVexTable_root_01_90_pp,
         /* 91 */ (const void *)&gVexTable_root_01_91_pp,
         /* 92 */ (const void *)&gVexTable_root_01_92_pp,
         /* 93 */ (const void *)&gVexTable_root_01_93_pp,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
         /* 98 */ (const void *)&gVexTable_root_01_98_pp,
         /* 99 */ (const void *)&gVexTable_root_01_99_pp,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
         /* ae */ (const void *)&gVexTable_root_01_ae_pp,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
         /* c2 */ (const void *)&gVexTable_root_01_c2_pp,
-        /* c3 */ NULL,
+        /* c3 */ ND_NULL,
         /* c4 */ (const void *)&gVexTable_root_01_c4_pp,
         /* c5 */ (const void *)&gVexTable_root_01_c5_pp,
         /* c6 */ (const void *)&gVexTable_root_01_c6_pp,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
         /* d0 */ (const void *)&gVexTable_root_01_d0_pp,
         /* d1 */ (const void *)&gVexTable_root_01_d1_pp,
         /* d2 */ (const void *)&gVexTable_root_01_d2_pp,
@@ -9055,7 +9055,7 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
         /* fc */ (const void *)&gVexTable_root_01_fc_pp,
         /* fd */ (const void *)&gVexTable_root_01_fd_pp,
         /* fe */ (const void *)&gVexTable_root_01_fe_pp,
-        /* ff */ NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -9085,9 +9085,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_32_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_32_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9095,7 +9095,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_03_32_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_32_01_reg_l,
     }
 };
@@ -9104,10 +9104,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_32_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9137,9 +9137,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_33_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_33_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9147,7 +9147,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_03_33_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_33_01_reg_l,
     }
 };
@@ -9156,10 +9156,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_33_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9189,9 +9189,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_30_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_30_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9199,7 +9199,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_03_30_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_30_01_reg_l,
     }
 };
@@ -9208,10 +9208,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_30_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9241,9 +9241,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_31_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_31_01_reg_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9251,7 +9251,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_03_31_01_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_31_01_reg_l,
     }
 };
@@ -9260,10 +9260,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_31_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9278,9 +9278,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_f0_03_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9288,9 +9288,9 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
         /* 03 */ (const void *)&gVexTable_root_03_f0_03_l,
     }
 };
@@ -9306,9 +9306,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_df_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_df_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9316,10 +9316,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_df_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9333,10 +9333,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0d_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9350,10 +9350,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0c_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9368,7 +9368,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_4b_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9376,10 +9376,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_4b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9394,7 +9394,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_4a_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9402,10 +9402,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_4a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9420,7 +9420,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9435,7 +9435,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_1d_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9445,8 +9445,8 @@ const ND_TABLE_VEX_L gVexTable_root_03_1d_01_l =
     { 
         /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_w,
         /* 01 */ (const void *)&gVexTable_root_03_1d_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9454,10 +9454,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_1d_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9472,9 +9472,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_41_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_41_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9482,10 +9482,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_41_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9499,10 +9499,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_40_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9517,7 +9517,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_19_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9525,10 +9525,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_19_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_19_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9536,10 +9536,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_19_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9554,7 +9554,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_39_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -9562,10 +9562,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_39_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_39_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9573,10 +9573,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_39_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9591,9 +9591,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_17_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9608,9 +9608,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_17_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9627,10 +9627,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_17_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9659,10 +9659,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_69_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9691,10 +9691,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_68_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9723,10 +9723,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9755,10 +9755,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9787,10 +9787,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_5d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9819,10 +9819,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_5c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9851,10 +9851,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_5f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9883,10 +9883,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_5e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9915,10 +9915,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9947,10 +9947,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -9979,10 +9979,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10011,10 +10011,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_6e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10043,10 +10043,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_79_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10075,10 +10075,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_78_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10107,10 +10107,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7b_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10139,10 +10139,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7a_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10171,10 +10171,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7d_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10203,10 +10203,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10235,10 +10235,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7f_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10267,10 +10267,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_7e_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10284,7 +10284,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_cf_01_01_leaf,
     }
 };
@@ -10293,10 +10293,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_cf_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10310,7 +10310,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_ce_01_01_leaf,
     }
 };
@@ -10319,10 +10319,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_ce_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10337,7 +10337,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_18_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10345,10 +10345,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_18_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_18_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10356,10 +10356,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_18_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10374,7 +10374,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_38_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10382,10 +10382,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_38_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_38_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10393,10 +10393,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_38_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10411,9 +10411,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_21_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10428,9 +10428,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_21_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10447,10 +10447,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_21_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10464,10 +10464,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_42_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10481,10 +10481,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0f_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10499,7 +10499,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_02_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_02_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10507,10 +10507,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_02_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10525,7 +10525,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_4c_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10533,10 +10533,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_4c_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10550,10 +10550,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0e_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10567,10 +10567,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_44_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10585,9 +10585,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_61_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_61_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10595,10 +10595,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_61_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10613,9 +10613,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_60_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_60_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10623,10 +10623,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_60_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10641,9 +10641,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_63_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_63_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10651,10 +10651,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_63_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10669,9 +10669,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_62_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_62_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10679,10 +10679,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_62_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10697,7 +10697,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_06_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10705,10 +10705,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_06_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_06_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10716,10 +10716,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_06_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_46_01_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10742,10 +10742,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_46_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_46_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10753,10 +10753,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_46_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10785,10 +10785,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_49_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10817,10 +10817,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_48_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10835,7 +10835,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_05_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_05_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10843,10 +10843,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_05_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10861,7 +10861,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_04_01_w =
     ND_ILUT_VEX_W,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_04_01_00_leaf,
-        /* 01 */ NULL,
+        /* 01 */ ND_NULL,
     }
 };
 
@@ -10869,10 +10869,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_04_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10886,7 +10886,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_01_01_01_01_leaf,
     }
 };
@@ -10895,10 +10895,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_01_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_01_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10906,10 +10906,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_01_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10923,7 +10923,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w =
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_00_01_01_01_leaf,
     }
 };
@@ -10932,10 +10932,10 @@ const ND_TABLE_VEX_L gVexTable_root_03_00_01_l =
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_00_01_01_w,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10943,10 +10943,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_00_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10961,9 +10961,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10978,9 +10978,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -10997,10 +10997,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_14_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11030,9 +11030,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_16_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_16_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11040,10 +11040,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_16_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11058,9 +11058,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11075,9 +11075,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11094,10 +11094,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_15_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11112,9 +11112,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_20_01_mem_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11129,9 +11129,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_20_01_reg_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11148,10 +11148,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_20_01_modrmmod,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11181,9 +11181,9 @@ const ND_TABLE_VEX_L gVexTable_root_03_22_01_l =
     ND_ILUT_VEX_L,
     { 
         /* 00 */ (const void *)&gVexTable_root_03_22_01_00_wi,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11191,10 +11191,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_22_01_l,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11208,10 +11208,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_09_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11225,10 +11225,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_08_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11242,10 +11242,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0b_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11259,10 +11259,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp =
 {
     ND_ILUT_VEX_PP,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_03_0a_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
     }
 };
 
@@ -11273,11 +11273,11 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* 00 */ (const void *)&gVexTable_root_03_00_pp,
         /* 01 */ (const void *)&gVexTable_root_03_01_pp,
         /* 02 */ (const void *)&gVexTable_root_03_02_pp,
-        /* 03 */ NULL,
+        /* 03 */ ND_NULL,
         /* 04 */ (const void *)&gVexTable_root_03_04_pp,
         /* 05 */ (const void *)&gVexTable_root_03_05_pp,
         /* 06 */ (const void *)&gVexTable_root_03_06_pp,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
         /* 08 */ (const void *)&gVexTable_root_03_08_pp,
         /* 09 */ (const void *)&gVexTable_root_03_09_pp,
         /* 0a */ (const void *)&gVexTable_root_03_0a_pp,
@@ -11286,82 +11286,82 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* 0d */ (const void *)&gVexTable_root_03_0d_pp,
         /* 0e */ (const void *)&gVexTable_root_03_0e_pp,
         /* 0f */ (const void *)&gVexTable_root_03_0f_pp,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
         /* 14 */ (const void *)&gVexTable_root_03_14_pp,
         /* 15 */ (const void *)&gVexTable_root_03_15_pp,
         /* 16 */ (const void *)&gVexTable_root_03_16_pp,
         /* 17 */ (const void *)&gVexTable_root_03_17_pp,
         /* 18 */ (const void *)&gVexTable_root_03_18_pp,
         /* 19 */ (const void *)&gVexTable_root_03_19_pp,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
         /* 1d */ (const void *)&gVexTable_root_03_1d_pp,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
         /* 20 */ (const void *)&gVexTable_root_03_20_pp,
         /* 21 */ (const void *)&gVexTable_root_03_21_pp,
         /* 22 */ (const void *)&gVexTable_root_03_22_pp,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
         /* 30 */ (const void *)&gVexTable_root_03_30_pp,
         /* 31 */ (const void *)&gVexTable_root_03_31_pp,
         /* 32 */ (const void *)&gVexTable_root_03_32_pp,
         /* 33 */ (const void *)&gVexTable_root_03_33_pp,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
         /* 38 */ (const void *)&gVexTable_root_03_38_pp,
         /* 39 */ (const void *)&gVexTable_root_03_39_pp,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
         /* 40 */ (const void *)&gVexTable_root_03_40_pp,
         /* 41 */ (const void *)&gVexTable_root_03_41_pp,
         /* 42 */ (const void *)&gVexTable_root_03_42_pp,
-        /* 43 */ NULL,
+        /* 43 */ ND_NULL,
         /* 44 */ (const void *)&gVexTable_root_03_44_pp,
-        /* 45 */ NULL,
+        /* 45 */ ND_NULL,
         /* 46 */ (const void *)&gVexTable_root_03_46_pp,
-        /* 47 */ NULL,
+        /* 47 */ ND_NULL,
         /* 48 */ (const void *)&gVexTable_root_03_48_pp,
         /* 49 */ (const void *)&gVexTable_root_03_49_pp,
         /* 4a */ (const void *)&gVexTable_root_03_4a_pp,
         /* 4b */ (const void *)&gVexTable_root_03_4b_pp,
         /* 4c */ (const void *)&gVexTable_root_03_4c_pp,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
         /* 5c */ (const void *)&gVexTable_root_03_5c_pp,
         /* 5d */ (const void *)&gVexTable_root_03_5d_pp,
         /* 5e */ (const void *)&gVexTable_root_03_5e_pp,
@@ -11370,10 +11370,10 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* 61 */ (const void *)&gVexTable_root_03_61_pp,
         /* 62 */ (const void *)&gVexTable_root_03_62_pp,
         /* 63 */ (const void *)&gVexTable_root_03_63_pp,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
         /* 68 */ (const void *)&gVexTable_root_03_68_pp,
         /* 69 */ (const void *)&gVexTable_root_03_69_pp,
         /* 6a */ (const void *)&gVexTable_root_03_6a_pp,
@@ -11382,14 +11382,14 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* 6d */ (const void *)&gVexTable_root_03_6d_pp,
         /* 6e */ (const void *)&gVexTable_root_03_6e_pp,
         /* 6f */ (const void *)&gVexTable_root_03_6f_pp,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
         /* 78 */ (const void *)&gVexTable_root_03_78_pp,
         /* 79 */ (const void *)&gVexTable_root_03_79_pp,
         /* 7a */ (const void *)&gVexTable_root_03_7a_pp,
@@ -11398,134 +11398,134 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* 7d */ (const void *)&gVexTable_root_03_7d_pp,
         /* 7e */ (const void *)&gVexTable_root_03_7e_pp,
         /* 7f */ (const void *)&gVexTable_root_03_7f_pp,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
         /* ce */ (const void *)&gVexTable_root_03_ce_pp,
         /* cf */ (const void *)&gVexTable_root_03_cf_pp,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
         /* df */ (const void *)&gVexTable_root_03_df_pp,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
         /* f0 */ (const void *)&gVexTable_root_03_f0_pp,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -11533,38 +11533,38 @@ const ND_TABLE_VEX_MMMMM gVexTable_root_mmmmm =
 {
     ND_ILUT_VEX_MMMMM,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gVexTable_root_01_opcode,
         /* 02 */ (const void *)&gVexTable_root_02_opcode,
         /* 03 */ (const void *)&gVexTable_root_03_opcode,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
     }
 };
 
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
index 2444fc6..7a07c81 100644
--- a/bddisasm/include/table_xop.h
+++ b/bddisasm/include/table_xop.h
@@ -25,12 +25,12 @@ const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg =
     { 
         /* 00 */ (const void *)&gXopTable_root_0a_12_00_leaf,
         /* 01 */ (const void *)&gXopTable_root_0a_12_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -38,262 +38,262 @@ const ND_TABLE_OPCODE gXopTable_root_0a_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
         /* 10 */ (const void *)&gXopTable_root_0a_10_leaf,
-        /* 11 */ NULL,
+        /* 11 */ ND_NULL,
         /* 12 */ (const void *)&gXopTable_root_0a_12_modrmreg,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
-        /* 95 */ NULL,
-        /* 96 */ NULL,
-        /* 97 */ NULL,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
-        /* c1 */ NULL,
-        /* c2 */ NULL,
-        /* c3 */ NULL,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
+        /* 95 */ ND_NULL,
+        /* 96 */ ND_NULL,
+        /* 97 */ ND_NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
+        /* c1 */ ND_NULL,
+        /* c2 */ ND_NULL,
+        /* c3 */ ND_NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -343,7 +343,7 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gXopTable_root_09_01_01_leaf,
         /* 02 */ (const void *)&gXopTable_root_09_01_02_leaf,
         /* 03 */ (const void *)&gXopTable_root_09_01_03_leaf,
@@ -370,14 +370,14 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg =
 {
     ND_ILUT_MODRM_REG,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gXopTable_root_09_02_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
         /* 06 */ (const void *)&gXopTable_root_09_02_06_leaf,
-        /* 07 */ NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -399,12 +399,12 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg =
     { 
         /* 00 */ (const void *)&gXopTable_root_09_12_reg_00_leaf,
         /* 01 */ (const void *)&gXopTable_root_09_12_reg_01_leaf,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
     }
 };
 
@@ -412,7 +412,7 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
 {
     ND_ILUT_MODRM_MOD,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gXopTable_root_09_12_reg_modrmreg,
     }
 };
@@ -787,150 +787,150 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
+        /* 00 */ ND_NULL,
         /* 01 */ (const void *)&gXopTable_root_09_01_modrmreg,
         /* 02 */ (const void *)&gXopTable_root_09_02_modrmreg,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
         /* 12 */ (const void *)&gXopTable_root_09_12_modrmmod,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
         /* 80 */ (const void *)&gXopTable_root_09_80_leaf,
         /* 81 */ (const void *)&gXopTable_root_09_81_leaf,
         /* 82 */ (const void *)&gXopTable_root_09_82_leaf,
         /* 83 */ (const void *)&gXopTable_root_09_83_leaf,
-        /* 84 */ NULL,
-        /* 85 */ NULL,
-        /* 86 */ NULL,
-        /* 87 */ NULL,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
-        /* 8e */ NULL,
-        /* 8f */ NULL,
+        /* 84 */ ND_NULL,
+        /* 85 */ ND_NULL,
+        /* 86 */ ND_NULL,
+        /* 87 */ ND_NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
+        /* 8e */ ND_NULL,
+        /* 8f */ ND_NULL,
         /* 90 */ (const void *)&gXopTable_root_09_90_w,
         /* 91 */ (const void *)&gXopTable_root_09_91_w,
         /* 92 */ (const void *)&gXopTable_root_09_92_w,
@@ -943,106 +943,106 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
         /* 99 */ (const void *)&gXopTable_root_09_99_w,
         /* 9a */ (const void *)&gXopTable_root_09_9a_w,
         /* 9b */ (const void *)&gXopTable_root_09_9b_w,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
-        /* 9e */ NULL,
-        /* 9f */ NULL,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
-        /* a2 */ NULL,
-        /* a3 */ NULL,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
-        /* a6 */ NULL,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
-        /* b6 */ NULL,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
-        /* c0 */ NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
+        /* 9e */ ND_NULL,
+        /* 9f */ ND_NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
+        /* a2 */ ND_NULL,
+        /* a3 */ ND_NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
+        /* a6 */ ND_NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
+        /* b6 */ ND_NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
+        /* c0 */ ND_NULL,
         /* c1 */ (const void *)&gXopTable_root_09_c1_leaf,
         /* c2 */ (const void *)&gXopTable_root_09_c2_leaf,
         /* c3 */ (const void *)&gXopTable_root_09_c3_leaf,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
         /* c6 */ (const void *)&gXopTable_root_09_c6_leaf,
         /* c7 */ (const void *)&gXopTable_root_09_c7_leaf,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
         /* cb */ (const void *)&gXopTable_root_09_cb_leaf,
-        /* cc */ NULL,
-        /* cd */ NULL,
-        /* ce */ NULL,
-        /* cf */ NULL,
-        /* d0 */ NULL,
+        /* cc */ ND_NULL,
+        /* cd */ ND_NULL,
+        /* ce */ ND_NULL,
+        /* cf */ ND_NULL,
+        /* d0 */ ND_NULL,
         /* d1 */ (const void *)&gXopTable_root_09_d1_leaf,
         /* d2 */ (const void *)&gXopTable_root_09_d2_leaf,
         /* d3 */ (const void *)&gXopTable_root_09_d3_leaf,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
         /* d6 */ (const void *)&gXopTable_root_09_d6_leaf,
         /* d7 */ (const void *)&gXopTable_root_09_d7_leaf,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
         /* db */ (const void *)&gXopTable_root_09_db_leaf,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
         /* e1 */ (const void *)&gXopTable_root_09_e1_leaf,
         /* e2 */ (const void *)&gXopTable_root_09_e2_leaf,
         /* e3 */ (const void *)&gXopTable_root_09_e3_leaf,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
-        /* ec */ NULL,
-        /* ed */ NULL,
-        /* ee */ NULL,
-        /* ef */ NULL,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
+        /* ec */ ND_NULL,
+        /* ed */ ND_NULL,
+        /* ee */ ND_NULL,
+        /* ef */ ND_NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -1236,262 +1236,262 @@ const ND_TABLE_OPCODE gXopTable_root_08_opcode =
 {
     ND_ILUT_OPCODE,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
-        /* 08 */ NULL,
-        /* 09 */ NULL,
-        /* 0a */ NULL,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
-        /* 20 */ NULL,
-        /* 21 */ NULL,
-        /* 22 */ NULL,
-        /* 23 */ NULL,
-        /* 24 */ NULL,
-        /* 25 */ NULL,
-        /* 26 */ NULL,
-        /* 27 */ NULL,
-        /* 28 */ NULL,
-        /* 29 */ NULL,
-        /* 2a */ NULL,
-        /* 2b */ NULL,
-        /* 2c */ NULL,
-        /* 2d */ NULL,
-        /* 2e */ NULL,
-        /* 2f */ NULL,
-        /* 30 */ NULL,
-        /* 31 */ NULL,
-        /* 32 */ NULL,
-        /* 33 */ NULL,
-        /* 34 */ NULL,
-        /* 35 */ NULL,
-        /* 36 */ NULL,
-        /* 37 */ NULL,
-        /* 38 */ NULL,
-        /* 39 */ NULL,
-        /* 3a */ NULL,
-        /* 3b */ NULL,
-        /* 3c */ NULL,
-        /* 3d */ NULL,
-        /* 3e */ NULL,
-        /* 3f */ NULL,
-        /* 40 */ NULL,
-        /* 41 */ NULL,
-        /* 42 */ NULL,
-        /* 43 */ NULL,
-        /* 44 */ NULL,
-        /* 45 */ NULL,
-        /* 46 */ NULL,
-        /* 47 */ NULL,
-        /* 48 */ NULL,
-        /* 49 */ NULL,
-        /* 4a */ NULL,
-        /* 4b */ NULL,
-        /* 4c */ NULL,
-        /* 4d */ NULL,
-        /* 4e */ NULL,
-        /* 4f */ NULL,
-        /* 50 */ NULL,
-        /* 51 */ NULL,
-        /* 52 */ NULL,
-        /* 53 */ NULL,
-        /* 54 */ NULL,
-        /* 55 */ NULL,
-        /* 56 */ NULL,
-        /* 57 */ NULL,
-        /* 58 */ NULL,
-        /* 59 */ NULL,
-        /* 5a */ NULL,
-        /* 5b */ NULL,
-        /* 5c */ NULL,
-        /* 5d */ NULL,
-        /* 5e */ NULL,
-        /* 5f */ NULL,
-        /* 60 */ NULL,
-        /* 61 */ NULL,
-        /* 62 */ NULL,
-        /* 63 */ NULL,
-        /* 64 */ NULL,
-        /* 65 */ NULL,
-        /* 66 */ NULL,
-        /* 67 */ NULL,
-        /* 68 */ NULL,
-        /* 69 */ NULL,
-        /* 6a */ NULL,
-        /* 6b */ NULL,
-        /* 6c */ NULL,
-        /* 6d */ NULL,
-        /* 6e */ NULL,
-        /* 6f */ NULL,
-        /* 70 */ NULL,
-        /* 71 */ NULL,
-        /* 72 */ NULL,
-        /* 73 */ NULL,
-        /* 74 */ NULL,
-        /* 75 */ NULL,
-        /* 76 */ NULL,
-        /* 77 */ NULL,
-        /* 78 */ NULL,
-        /* 79 */ NULL,
-        /* 7a */ NULL,
-        /* 7b */ NULL,
-        /* 7c */ NULL,
-        /* 7d */ NULL,
-        /* 7e */ NULL,
-        /* 7f */ NULL,
-        /* 80 */ NULL,
-        /* 81 */ NULL,
-        /* 82 */ NULL,
-        /* 83 */ NULL,
-        /* 84 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
+        /* 08 */ ND_NULL,
+        /* 09 */ ND_NULL,
+        /* 0a */ ND_NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
+        /* 20 */ ND_NULL,
+        /* 21 */ ND_NULL,
+        /* 22 */ ND_NULL,
+        /* 23 */ ND_NULL,
+        /* 24 */ ND_NULL,
+        /* 25 */ ND_NULL,
+        /* 26 */ ND_NULL,
+        /* 27 */ ND_NULL,
+        /* 28 */ ND_NULL,
+        /* 29 */ ND_NULL,
+        /* 2a */ ND_NULL,
+        /* 2b */ ND_NULL,
+        /* 2c */ ND_NULL,
+        /* 2d */ ND_NULL,
+        /* 2e */ ND_NULL,
+        /* 2f */ ND_NULL,
+        /* 30 */ ND_NULL,
+        /* 31 */ ND_NULL,
+        /* 32 */ ND_NULL,
+        /* 33 */ ND_NULL,
+        /* 34 */ ND_NULL,
+        /* 35 */ ND_NULL,
+        /* 36 */ ND_NULL,
+        /* 37 */ ND_NULL,
+        /* 38 */ ND_NULL,
+        /* 39 */ ND_NULL,
+        /* 3a */ ND_NULL,
+        /* 3b */ ND_NULL,
+        /* 3c */ ND_NULL,
+        /* 3d */ ND_NULL,
+        /* 3e */ ND_NULL,
+        /* 3f */ ND_NULL,
+        /* 40 */ ND_NULL,
+        /* 41 */ ND_NULL,
+        /* 42 */ ND_NULL,
+        /* 43 */ ND_NULL,
+        /* 44 */ ND_NULL,
+        /* 45 */ ND_NULL,
+        /* 46 */ ND_NULL,
+        /* 47 */ ND_NULL,
+        /* 48 */ ND_NULL,
+        /* 49 */ ND_NULL,
+        /* 4a */ ND_NULL,
+        /* 4b */ ND_NULL,
+        /* 4c */ ND_NULL,
+        /* 4d */ ND_NULL,
+        /* 4e */ ND_NULL,
+        /* 4f */ ND_NULL,
+        /* 50 */ ND_NULL,
+        /* 51 */ ND_NULL,
+        /* 52 */ ND_NULL,
+        /* 53 */ ND_NULL,
+        /* 54 */ ND_NULL,
+        /* 55 */ ND_NULL,
+        /* 56 */ ND_NULL,
+        /* 57 */ ND_NULL,
+        /* 58 */ ND_NULL,
+        /* 59 */ ND_NULL,
+        /* 5a */ ND_NULL,
+        /* 5b */ ND_NULL,
+        /* 5c */ ND_NULL,
+        /* 5d */ ND_NULL,
+        /* 5e */ ND_NULL,
+        /* 5f */ ND_NULL,
+        /* 60 */ ND_NULL,
+        /* 61 */ ND_NULL,
+        /* 62 */ ND_NULL,
+        /* 63 */ ND_NULL,
+        /* 64 */ ND_NULL,
+        /* 65 */ ND_NULL,
+        /* 66 */ ND_NULL,
+        /* 67 */ ND_NULL,
+        /* 68 */ ND_NULL,
+        /* 69 */ ND_NULL,
+        /* 6a */ ND_NULL,
+        /* 6b */ ND_NULL,
+        /* 6c */ ND_NULL,
+        /* 6d */ ND_NULL,
+        /* 6e */ ND_NULL,
+        /* 6f */ ND_NULL,
+        /* 70 */ ND_NULL,
+        /* 71 */ ND_NULL,
+        /* 72 */ ND_NULL,
+        /* 73 */ ND_NULL,
+        /* 74 */ ND_NULL,
+        /* 75 */ ND_NULL,
+        /* 76 */ ND_NULL,
+        /* 77 */ ND_NULL,
+        /* 78 */ ND_NULL,
+        /* 79 */ ND_NULL,
+        /* 7a */ ND_NULL,
+        /* 7b */ ND_NULL,
+        /* 7c */ ND_NULL,
+        /* 7d */ ND_NULL,
+        /* 7e */ ND_NULL,
+        /* 7f */ ND_NULL,
+        /* 80 */ ND_NULL,
+        /* 81 */ ND_NULL,
+        /* 82 */ ND_NULL,
+        /* 83 */ ND_NULL,
+        /* 84 */ ND_NULL,
         /* 85 */ (const void *)&gXopTable_root_08_85_leaf,
         /* 86 */ (const void *)&gXopTable_root_08_86_leaf,
         /* 87 */ (const void *)&gXopTable_root_08_87_leaf,
-        /* 88 */ NULL,
-        /* 89 */ NULL,
-        /* 8a */ NULL,
-        /* 8b */ NULL,
-        /* 8c */ NULL,
-        /* 8d */ NULL,
+        /* 88 */ ND_NULL,
+        /* 89 */ ND_NULL,
+        /* 8a */ ND_NULL,
+        /* 8b */ ND_NULL,
+        /* 8c */ ND_NULL,
+        /* 8d */ ND_NULL,
         /* 8e */ (const void *)&gXopTable_root_08_8e_leaf,
         /* 8f */ (const void *)&gXopTable_root_08_8f_leaf,
-        /* 90 */ NULL,
-        /* 91 */ NULL,
-        /* 92 */ NULL,
-        /* 93 */ NULL,
-        /* 94 */ NULL,
+        /* 90 */ ND_NULL,
+        /* 91 */ ND_NULL,
+        /* 92 */ ND_NULL,
+        /* 93 */ ND_NULL,
+        /* 94 */ ND_NULL,
         /* 95 */ (const void *)&gXopTable_root_08_95_leaf,
         /* 96 */ (const void *)&gXopTable_root_08_96_leaf,
         /* 97 */ (const void *)&gXopTable_root_08_97_leaf,
-        /* 98 */ NULL,
-        /* 99 */ NULL,
-        /* 9a */ NULL,
-        /* 9b */ NULL,
-        /* 9c */ NULL,
-        /* 9d */ NULL,
+        /* 98 */ ND_NULL,
+        /* 99 */ ND_NULL,
+        /* 9a */ ND_NULL,
+        /* 9b */ ND_NULL,
+        /* 9c */ ND_NULL,
+        /* 9d */ ND_NULL,
         /* 9e */ (const void *)&gXopTable_root_08_9e_leaf,
         /* 9f */ (const void *)&gXopTable_root_08_9f_leaf,
-        /* a0 */ NULL,
-        /* a1 */ NULL,
+        /* a0 */ ND_NULL,
+        /* a1 */ ND_NULL,
         /* a2 */ (const void *)&gXopTable_root_08_a2_w,
         /* a3 */ (const void *)&gXopTable_root_08_a3_w,
-        /* a4 */ NULL,
-        /* a5 */ NULL,
+        /* a4 */ ND_NULL,
+        /* a5 */ ND_NULL,
         /* a6 */ (const void *)&gXopTable_root_08_a6_leaf,
-        /* a7 */ NULL,
-        /* a8 */ NULL,
-        /* a9 */ NULL,
-        /* aa */ NULL,
-        /* ab */ NULL,
-        /* ac */ NULL,
-        /* ad */ NULL,
-        /* ae */ NULL,
-        /* af */ NULL,
-        /* b0 */ NULL,
-        /* b1 */ NULL,
-        /* b2 */ NULL,
-        /* b3 */ NULL,
-        /* b4 */ NULL,
-        /* b5 */ NULL,
+        /* a7 */ ND_NULL,
+        /* a8 */ ND_NULL,
+        /* a9 */ ND_NULL,
+        /* aa */ ND_NULL,
+        /* ab */ ND_NULL,
+        /* ac */ ND_NULL,
+        /* ad */ ND_NULL,
+        /* ae */ ND_NULL,
+        /* af */ ND_NULL,
+        /* b0 */ ND_NULL,
+        /* b1 */ ND_NULL,
+        /* b2 */ ND_NULL,
+        /* b3 */ ND_NULL,
+        /* b4 */ ND_NULL,
+        /* b5 */ ND_NULL,
         /* b6 */ (const void *)&gXopTable_root_08_b6_leaf,
-        /* b7 */ NULL,
-        /* b8 */ NULL,
-        /* b9 */ NULL,
-        /* ba */ NULL,
-        /* bb */ NULL,
-        /* bc */ NULL,
-        /* bd */ NULL,
-        /* be */ NULL,
-        /* bf */ NULL,
+        /* b7 */ ND_NULL,
+        /* b8 */ ND_NULL,
+        /* b9 */ ND_NULL,
+        /* ba */ ND_NULL,
+        /* bb */ ND_NULL,
+        /* bc */ ND_NULL,
+        /* bd */ ND_NULL,
+        /* be */ ND_NULL,
+        /* bf */ ND_NULL,
         /* c0 */ (const void *)&gXopTable_root_08_c0_leaf,
         /* c1 */ (const void *)&gXopTable_root_08_c1_leaf,
         /* c2 */ (const void *)&gXopTable_root_08_c2_leaf,
         /* c3 */ (const void *)&gXopTable_root_08_c3_leaf,
-        /* c4 */ NULL,
-        /* c5 */ NULL,
-        /* c6 */ NULL,
-        /* c7 */ NULL,
-        /* c8 */ NULL,
-        /* c9 */ NULL,
-        /* ca */ NULL,
-        /* cb */ NULL,
+        /* c4 */ ND_NULL,
+        /* c5 */ ND_NULL,
+        /* c6 */ ND_NULL,
+        /* c7 */ ND_NULL,
+        /* c8 */ ND_NULL,
+        /* c9 */ ND_NULL,
+        /* ca */ ND_NULL,
+        /* cb */ ND_NULL,
         /* cc */ (const void *)&gXopTable_root_08_cc_leaf,
         /* cd */ (const void *)&gXopTable_root_08_cd_leaf,
         /* ce */ (const void *)&gXopTable_root_08_ce_leaf,
         /* cf */ (const void *)&gXopTable_root_08_cf_leaf,
-        /* d0 */ NULL,
-        /* d1 */ NULL,
-        /* d2 */ NULL,
-        /* d3 */ NULL,
-        /* d4 */ NULL,
-        /* d5 */ NULL,
-        /* d6 */ NULL,
-        /* d7 */ NULL,
-        /* d8 */ NULL,
-        /* d9 */ NULL,
-        /* da */ NULL,
-        /* db */ NULL,
-        /* dc */ NULL,
-        /* dd */ NULL,
-        /* de */ NULL,
-        /* df */ NULL,
-        /* e0 */ NULL,
-        /* e1 */ NULL,
-        /* e2 */ NULL,
-        /* e3 */ NULL,
-        /* e4 */ NULL,
-        /* e5 */ NULL,
-        /* e6 */ NULL,
-        /* e7 */ NULL,
-        /* e8 */ NULL,
-        /* e9 */ NULL,
-        /* ea */ NULL,
-        /* eb */ NULL,
+        /* d0 */ ND_NULL,
+        /* d1 */ ND_NULL,
+        /* d2 */ ND_NULL,
+        /* d3 */ ND_NULL,
+        /* d4 */ ND_NULL,
+        /* d5 */ ND_NULL,
+        /* d6 */ ND_NULL,
+        /* d7 */ ND_NULL,
+        /* d8 */ ND_NULL,
+        /* d9 */ ND_NULL,
+        /* da */ ND_NULL,
+        /* db */ ND_NULL,
+        /* dc */ ND_NULL,
+        /* dd */ ND_NULL,
+        /* de */ ND_NULL,
+        /* df */ ND_NULL,
+        /* e0 */ ND_NULL,
+        /* e1 */ ND_NULL,
+        /* e2 */ ND_NULL,
+        /* e3 */ ND_NULL,
+        /* e4 */ ND_NULL,
+        /* e5 */ ND_NULL,
+        /* e6 */ ND_NULL,
+        /* e7 */ ND_NULL,
+        /* e8 */ ND_NULL,
+        /* e9 */ ND_NULL,
+        /* ea */ ND_NULL,
+        /* eb */ ND_NULL,
         /* ec */ (const void *)&gXopTable_root_08_ec_leaf,
         /* ed */ (const void *)&gXopTable_root_08_ed_leaf,
         /* ee */ (const void *)&gXopTable_root_08_ee_leaf,
         /* ef */ (const void *)&gXopTable_root_08_ef_leaf,
-        /* f0 */ NULL,
-        /* f1 */ NULL,
-        /* f2 */ NULL,
-        /* f3 */ NULL,
-        /* f4 */ NULL,
-        /* f5 */ NULL,
-        /* f6 */ NULL,
-        /* f7 */ NULL,
-        /* f8 */ NULL,
-        /* f9 */ NULL,
-        /* fa */ NULL,
-        /* fb */ NULL,
-        /* fc */ NULL,
-        /* fd */ NULL,
-        /* fe */ NULL,
-        /* ff */ NULL,
+        /* f0 */ ND_NULL,
+        /* f1 */ ND_NULL,
+        /* f2 */ ND_NULL,
+        /* f3 */ ND_NULL,
+        /* f4 */ ND_NULL,
+        /* f5 */ ND_NULL,
+        /* f6 */ ND_NULL,
+        /* f7 */ ND_NULL,
+        /* f8 */ ND_NULL,
+        /* f9 */ ND_NULL,
+        /* fa */ ND_NULL,
+        /* fb */ ND_NULL,
+        /* fc */ ND_NULL,
+        /* fd */ ND_NULL,
+        /* fe */ ND_NULL,
+        /* ff */ ND_NULL,
     }
 };
 
@@ -1499,38 +1499,38 @@ const ND_TABLE_VEX_MMMMM gXopTable_root_mmmmm =
 {
     ND_ILUT_VEX_MMMMM,
     { 
-        /* 00 */ NULL,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-        /* 06 */ NULL,
-        /* 07 */ NULL,
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+        /* 04 */ ND_NULL,
+        /* 05 */ ND_NULL,
+        /* 06 */ ND_NULL,
+        /* 07 */ ND_NULL,
         /* 08 */ (const void *)&gXopTable_root_08_opcode,
         /* 09 */ (const void *)&gXopTable_root_09_opcode,
         /* 0a */ (const void *)&gXopTable_root_0a_opcode,
-        /* 0b */ NULL,
-        /* 0c */ NULL,
-        /* 0d */ NULL,
-        /* 0e */ NULL,
-        /* 0f */ NULL,
-        /* 10 */ NULL,
-        /* 11 */ NULL,
-        /* 12 */ NULL,
-        /* 13 */ NULL,
-        /* 14 */ NULL,
-        /* 15 */ NULL,
-        /* 16 */ NULL,
-        /* 17 */ NULL,
-        /* 18 */ NULL,
-        /* 19 */ NULL,
-        /* 1a */ NULL,
-        /* 1b */ NULL,
-        /* 1c */ NULL,
-        /* 1d */ NULL,
-        /* 1e */ NULL,
-        /* 1f */ NULL,
+        /* 0b */ ND_NULL,
+        /* 0c */ ND_NULL,
+        /* 0d */ ND_NULL,
+        /* 0e */ ND_NULL,
+        /* 0f */ ND_NULL,
+        /* 10 */ ND_NULL,
+        /* 11 */ ND_NULL,
+        /* 12 */ ND_NULL,
+        /* 13 */ ND_NULL,
+        /* 14 */ ND_NULL,
+        /* 15 */ ND_NULL,
+        /* 16 */ ND_NULL,
+        /* 17 */ ND_NULL,
+        /* 18 */ ND_NULL,
+        /* 19 */ ND_NULL,
+        /* 1a */ ND_NULL,
+        /* 1b */ ND_NULL,
+        /* 1c */ ND_NULL,
+        /* 1d */ ND_NULL,
+        /* 1e */ ND_NULL,
+        /* 1f */ ND_NULL,
     }
 };
 
diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h
index 36e166d..f746270 100644
--- a/bddisasm/include/tabledefs.h
+++ b/bddisasm/include/tabledefs.h
@@ -5,6 +5,8 @@
 #ifndef TABLEDEFS_H
 #define TABLEDEFS_H
 
+#include "../inc/disasmtypes.h"
+
 //
 // Types of tables.
 //
@@ -80,104 +82,104 @@ typedef enum _ND_ILUT_TYPE
 
 typedef struct _ND_TABLE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[1];
 } ND_TABLE, *PND_TABLE;
 
 typedef struct _ND_TABLE_INSTRUCTION
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Instruction;
 } ND_TABLE_INSTRUCTION, *PND_TABLE_INSTRUCTION;
 
 typedef struct _ND_TABLE_OPCODE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[256];
 } ND_TABLE_OPCODE, *PND_TABLE_OPCODE;
 
 typedef struct _ND_TABLE_MODRM_MOD
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[2];
 } ND_TABLE_MODRM_MOD, *PND_TABLE_MODRM_MOD;
 
 typedef struct _ND_TABLE_MODRM_REG
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[8];
 } ND_TABLE_MODRM_REG, *PND_TABLE_MODRM_REG;
 
 typedef struct _ND_TABLE_MODRM_RM
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[8];
 } ND_TABLE_MODRM_RM, *PND_TABLE_MODRM_RM;
 
 typedef struct _ND_TABLE_MPREFIX
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_MPREFIX, *PND_TABLE_MPREFIX;
 
 
 typedef struct _ND_TABLE_AUXILIARY
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[6];
 } ND_TABLE_AUXILIARY, *PND_TABLE_AUXILIARY;
 
 typedef struct _ND_TABLE_VENDOR
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[6];
 } ND_TABLE_VENDOR;
 
 typedef struct _ND_TABLE_FEATURE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_FEATURE;
 
 typedef struct _ND_TABLE_DSIZE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[6];
 } ND_TABLE_DSIZE, *PND_TABLE_DSIZE;
 
 typedef struct _ND_TABLE_ASIZE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_ASIZE, *PND_TABLE_ASIZE;
 
 typedef struct _ND_TABLE_MODE
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_MODE, *PND_TABLE_MODE;
 
 typedef struct _ND_TABLE_VEX_MMMMM
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[32];
 } ND_TABLE_VEX_MMMMM, *PND_TABLE_VEX_MMMMM;
 
 typedef struct _ND_TABLE_VEX_PP
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_VEX_PP, *PND_TABLE_VEX_PP;
 
 typedef struct _ND_TABLE_VEX_L
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[4];
 } ND_TABLE_VEX_L, *PND_TABLE_VEX_L;
 
 typedef struct _ND_TABLE_VEX_W
 {
-    uint32_t        Type;
+    ND_UINT32       Type;
     const void      *Table[8];
 } ND_TABLE_VEX_W, *PND_TABLE_VEX_W;
 
@@ -194,37 +196,37 @@ __attribute__((aligned(128)))
 #endif
 typedef struct _ND_INSTRUCTION
 {
-    uint16_t        Instruction;    // Instruction identifier. Check ND_INS_CLASS definitions.
-    uint8_t         Category;       // Instruction category. Check ND_INS_TYPE.
-    uint8_t         IsaSet;         // Instruction set. Check ND_INS_SET.
-    uint16_t        Mnemonic;       // Mnemonic (index inside the global mnemonic table).
+    ND_UINT16       Instruction;    // Instruction identifier. Check ND_INS_CLASS definitions.
+    ND_UINT8        Category;       // Instruction category. Check ND_INS_TYPE.
+    ND_UINT8        IsaSet;         // Instruction set. Check ND_INS_SET.
+    ND_UINT16       Mnemonic;       // Mnemonic (index inside the global mnemonic table).
 
-    uint16_t        ValidPrefixes;  // Accepted prefixes.
-    uint32_t        ValidModes;     // Valid operating modes for the instruction.
-    uint8_t         ValidDecorators;// Accepted decorators (valid for EVEX instructions).
+    ND_UINT16       ValidPrefixes;  // Accepted prefixes.
+    ND_UINT32       ValidModes;     // Valid operating modes for the instruction.
+    ND_UINT8        ValidDecorators;// Accepted decorators (valid for EVEX instructions).
 
-    uint8_t         OpsCount;       // Low 4 bits: explicit operands count; high 4 bits: implicit ops count.
+    ND_UINT8        OpsCount;       // Low 4 bits: explicit operands count; high 4 bits: implicit ops count.
 
-    uint8_t         TupleType;      // EVEX tuple type.
-    uint8_t         ExcType : 5;    // SSE/VEX/EVEX/OPMASK/AMX exception type.
-    uint8_t         ExcClass : 3;   // Indicates the exception class (SSE/AVX, EVEX, OPMASK or AMX).
+    ND_UINT8        TupleType;      // EVEX tuple type.
+    ND_UINT8        ExcType : 5;    // SSE/VEX/EVEX/OPMASK/AMX exception type.
+    ND_UINT8        ExcClass : 3;   // Indicates the exception class (SSE/AVX, EVEX, OPMASK or AMX).
     
-    uint8_t         FpuFlags;       // FPU status word C0, C1, C2 & C3 access type.
+    ND_UINT8        FpuFlags;       // FPU status word C0, C1, C2 & C3 access type.
 
-    uint8_t         Reserved2;
-    uint16_t        Reserved3;
+    ND_UINT8        Reserved2;
+    ND_UINT16       Reserved3;
 
-    uint32_t        Attributes;     // Instruction attributes.
-    uint64_t        CpuidFlag;      // Required CPUID feature flag.
+    ND_UINT32       Attributes;     // Instruction attributes.
+    ND_UINT64       CpuidFlag;      // Required CPUID feature flag.
 
     // Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag
     // cannot be both cleared and set.
-    uint32_t        TestedFlags;    // Tested flags.
-    uint32_t        ModifiedFlags;  // Modified flags.
-    uint32_t        SetFlags;       // Flags that are always set to 1.
-    uint32_t        ClearedFlags;   // Flags that are always cleared.
+    ND_UINT32       TestedFlags;    // Tested flags.
+    ND_UINT32       ModifiedFlags;  // Modified flags.
+    ND_UINT32       SetFlags;       // Flags that are always set to 1.
+    ND_UINT32       ClearedFlags;   // Flags that are always cleared.
 
-    uint64_t        Operands[10];
+    ND_UINT64       Operands[10];
 } ND_INSTRUCTION, *PND_INSTRUCTION;
 #ifdef _MSC_VER
 #pragma warning(pop)
@@ -241,12 +243,12 @@ typedef struct _ND_INSTRUCTION
 // Byte 4: operand decorators
 // Byte 5: operand block addressing mode - 0 if not block addressing
 //
-#define ND_OP(type, size, flags, acc, dec, block)       (((uint64_t)((type) & 0xFF) << 0)   |    \
-                                                         ((uint64_t)((size) & 0xFF) << 8)   |    \
-                                                         ((uint64_t)((flags) & 0xFF) << 16) |    \
-                                                         ((uint64_t)((acc) & 0xFF) << 24)   |    \
-                                                         ((uint64_t)((dec) & 0xFF) << 32)   |    \
-                                                         ((uint64_t)((block) & 0xFF) << 40))
+#define ND_OP(type, size, flags, acc, dec, block)       (((ND_UINT64)((type) & 0xFF) << 0)   |    \
+                                                         ((ND_UINT64)((size) & 0xFF) << 8)   |    \
+                                                         ((ND_UINT64)((flags) & 0xFF) << 16) |    \
+                                                         ((ND_UINT64)((acc) & 0xFF) << 24)   |    \
+                                                         ((ND_UINT64)((dec) & 0xFF) << 32)   |    \
+                                                         ((ND_UINT64)((block) & 0xFF) << 40))
 
 #define OP ND_OP
 
diff --git a/bddisasm_test/basic/cet_64.result b/bddisasm_test/basic/cet_64.result
index 4520e71..bf8badb 100644
--- a/bddisasm_test/basic/cet_64.result
+++ b/bddisasm_test/basic/cet_64.result
@@ -114,9 +114,9 @@
         ISA Set: CET_SS, Ins cat: CET, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 7
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
@@ -131,9 +131,9 @@
         ISA Set: CET_SS, Ins cat: CET, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 7
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
diff --git a/bddisasm_test/basic/tsx_64.result b/bddisasm_test/basic/tsx_64.result
index 601852a..0e73c36 100644
--- a/bddisasm_test/basic/tsx_64.result
+++ b/bddisasm_test/basic/tsx_64.result
@@ -39,7 +39,7 @@
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
diff --git a/bddisasm_test/cet/cet_32.result b/bddisasm_test/cet/cet_32.result
index 8e479f6..3f6ea19 100644
--- a/bddisasm_test/cet/cet_32.result
+++ b/bddisasm_test/cet/cet_32.result
@@ -133,9 +133,9 @@
         ISA Set: CET_SS, Ins cat: CET, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 7
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
diff --git a/bddisasm_test/cet/cet_64.result b/bddisasm_test/cet/cet_64.result
index 237a8d8..6b340ae 100644
--- a/bddisasm_test/cet/cet_64.result
+++ b/bddisasm_test/cet/cet_64.result
@@ -167,9 +167,9 @@
         ISA Set: CET_SS, Ins cat: CET, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 7
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
@@ -184,9 +184,9 @@
         ISA Set: CET_SS, Ins cat: CET, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 7
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
                 VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
diff --git a/bdshemu/bdshemu.c b/bdshemu/bdshemu.c
index ef89ca2..c69d00e 100644
--- a/bdshemu/bdshemu.c
+++ b/bdshemu/bdshemu.c
@@ -6,15 +6,15 @@
 // bdshemu.c
 //
 
-
-#include "nd_crt.h"
-#include "bddisasm.h"
 #include "bdshemu.h"
+#include "../bddisasm/include/nd_crt.h"
 
 #ifdef __clang__
 #include <wmmintrin.h>
 #else
+#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86)
 #include <immintrin.h>
+#endif // defined(ND_ARCH_X64) || defined(ND_ARCH_X86)
 #endif // __clang__
 
 //
@@ -24,38 +24,38 @@ typedef struct _SHEMU_VALUE
 {
     union
     {
-        uint8_t         Bytes[ND_MAX_REGISTER_SIZE];
-        uint16_t        Words[ND_MAX_REGISTER_SIZE / sizeof(uint16_t)];
-        uint32_t        Dwords[ND_MAX_REGISTER_SIZE / sizeof(uint32_t)];
-        uint64_t        Qwords[ND_MAX_REGISTER_SIZE / sizeof(uint64_t)];
+        ND_UINT8        Bytes[ND_MAX_REGISTER_SIZE];
+        ND_UINT16       Words[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT16)];
+        ND_UINT32       Dwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT32)];
+        ND_UINT64       Qwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT64)];
 
         struct
         {
-            uint16_t    FpuControlWord;
-            uint16_t    FpuStatusWord;
-            uint16_t    FpuTagWord;
-            uint16_t    Rsvd;
-            uint32_t    FpuDataPointer;
-            uint32_t    FpuInstructionPointer;
-            uint32_t    FpuLastInstructionOpcode;
+            ND_UINT16   FpuControlWord;
+            ND_UINT16   FpuStatusWord;
+            ND_UINT16   FpuTagWord;
+            ND_UINT16   Rsvd;
+            ND_UINT32   FpuDataPointer;
+            ND_UINT32   FpuInstructionPointer;
+            ND_UINT32   FpuLastInstructionOpcode;
         } FpuEnvironment;
 
         struct
         {
-            uint16_t    FpuControlWord;
-            uint16_t    FpuStatuwsWord;
-            uint16_t    FpuTagWord;
-            uint16_t    FpuOpcode;
-            uint64_t    FpuRip;
-            uint64_t    FpuDataPointer;
-            uint32_t    Mxcsr;
-            uint32_t    MxcsrMask;
+            ND_UINT16   FpuControlWord;
+            ND_UINT16   FpuStatuwsWord;
+            ND_UINT16   FpuTagWord;
+            ND_UINT16   FpuOpcode;
+            ND_UINT64   FpuRip;
+            ND_UINT64   FpuDataPointer;
+            ND_UINT32   Mxcsr;
+            ND_UINT32   MxcsrMask;
         } XsaveArea;
 
         struct
         {
-            uint16_t    Limit;
-            uint64_t    Base;
+            ND_UINT16   Limit;
+            ND_UINT64   Base;
         } Descriptor;
 
     } Value;
@@ -119,7 +119,7 @@ shemu_printf(
     char buff[1024];
     va_list args;
 
-    if (NULL == Context->Log)
+    if (ND_NULL == Context->Log)
     {
         return;
     }
@@ -145,20 +145,20 @@ static void *
 shemu_memcpy(
     void *Dest,
     const void *Source,
-    size_t Size
+    ND_SIZET Size
     )
 {
     void *start = Dest;
-    uint32_t index = 0;
+    ND_UINT32 index = 0;
 
-    if (NULL == Dest)
+    if (ND_NULL == Dest)
     {
-        return NULL;
+        return ND_NULL;
     }
 
-    if (NULL == Source)
+    if (ND_NULL == Source)
     {
-        return NULL;
+        return ND_NULL;
     }
 
     while (Size--)
@@ -175,13 +175,13 @@ shemu_memcpy(
 //
 // ShemuBts
 //
-inline static uint8_t
+inline static ND_UINT8
 ShemuBts(
-    uint8_t *BitMap,
-    uint64_t Position
+    ND_UINT8 *BitMap,
+    ND_UINT64 Position
     )
 {
-    uint8_t old;
+    ND_UINT8 old;
 
     old = (BitMap[Position / 8] >> (Position % 8)) & 1;
 
@@ -194,13 +194,13 @@ ShemuBts(
 //
 // ShemuBtr
 //
-inline static uint8_t
+inline static ND_UINT8
 ShemuBtr(
-    uint8_t *BitMap,
-    uint64_t Position
+    ND_UINT8 *BitMap,
+    ND_UINT64 Position
     )
 {
-    uint8_t old;
+    ND_UINT8 old;
 
     old = (BitMap[Position / 8] >> (Position % 8)) & 1;
 
@@ -213,10 +213,10 @@ ShemuBtr(
 //
 // ShemuBt
 //
-inline static uint8_t
+inline static ND_UINT8
 ShemuBt(
-    uint8_t *BitMap,
-    uint64_t Position
+    ND_UINT8 *BitMap,
+    ND_UINT64 Position
     )
 {
     return (BitMap[Position / 8] >> (Position % 8)) & 1;
@@ -228,82 +228,82 @@ ShemuBt(
 //
 static void
 ShemuSetBits(
-    uint8_t *Bitmap,
-    uint64_t Start,
-    uint64_t Size,
-    bool Val
+    ND_UINT8 *Bitmap,
+    ND_UINT64 Start,
+    ND_UINT64 Size,
+    ND_BOOL Val
     )
 //
 // No size validations here; the caller has to make sure the ranges are all good.
 //
 {
-    uint64_t i;
+    ND_UINT64 i;
 
     for (i = 0; i < Size; i++)
     {
         if (Val)
         {
-            ShemuBts(Bitmap, (uint64_t)(Start + i));
+            ShemuBts(Bitmap, (ND_UINT64)(Start + i));
         }
         else
         {
-            ShemuBtr(Bitmap, (uint64_t)(Start + i));
+            ShemuBtr(Bitmap, (ND_UINT64)(Start + i));
         }
     }
 }
 
 
+////
+//// ShemuAllBitsSet
+////
+//static ND_BOOL
+//ShemuAllBitsSet(
+//    ND_UINT8 *Bitmap,
+//    ND_UINT64 Start,
+//    ND_UINT32 Size
+//    )
+////
+//// No size validations here; the caller has to make sure the ranges are all good.
+////
+//{
+//    ND_UINT32 i;
 //
-// ShemuAllBitsSet
-//
-static bool
-ShemuAllBitsSet(
-    uint8_t *Bitmap,
-    uint64_t Start,
-    uint32_t Size
-    )
-//
-// No size validations here; the caller has to make sure the ranges are all good.
+//    for (i = 0; i < Size; i++)
+//    {
+//        if (!ShemuBt(Bitmap, (ND_UINT64)(Start + i)))
+//        {
+//            return ND_FALSE;
+//        }
+//    }
 //
-{
-    uint32_t i;
-
-    for (i = 0; i < Size; i++)
-    {
-        if (!ShemuBt(Bitmap, (uint64_t)(Start + i)))
-        {
-            return false;
-        }
-    }
-
-    return true;
-}
+//    return ND_TRUE;
+//}
 
 
 //
 // ShemuAnyBitsSet
 //
-static bool
+static ND_BOOL
 ShemuAnyBitsSet(
-    uint8_t *Bitmap,
-    uint64_t Start,
-    uint32_t Size
+    ND_UINT8 *Bitmap,
+    ND_UINT64 Start,
+    ND_UINT32 Size
     )
 //
 // No size validations here; the caller has to make sure the ranges are all good.
 //
 {
-    uint32_t i;
+    ND_UINT32 i;
 
     for (i = 0; i < Size; i++)
     {
-        if (ShemuBt(Bitmap, (uint64_t)(Start + i)))
+        if (ShemuBt(Bitmap, (ND_UINT64)(Start + i)))
         {
-            return true;
+            return ND_TRUE;
         }
     }
 
-    return false;
+    return ND_FALSE;
 }
 
 
@@ -313,14 +313,14 @@ ShemuAnyBitsSet(
 static void
 ShemuSetFlags(
     SHEMU_CONTEXT *Context,
-    uint64_t Dst,
-    uint64_t Src1,
-    uint64_t Src2,
+    ND_UINT64 Dst,
+    ND_UINT64 Src1,
+    ND_UINT64 Src2,
     ND_OPERAND_SIZE Size,
-    uint8_t FlagsMode
+    ND_UINT8 FlagsMode
     )
 {
-    uint8_t pfArr[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+    ND_UINT8 pfArr[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
 
     // Mask the operands with their respective size.
     Dst = ND_TRIM(Size, Dst);
@@ -482,10 +482,10 @@ ShemuSetFlags(
 //
 // ShemuEvalCondition
 //
-static bool
+static ND_BOOL
 ShemuEvalCondition(
     SHEMU_CONTEXT *Context,
-    uint8_t ConditionCode
+    ND_UINT8 ConditionCode
     )
 {
     switch (ConditionCode)
@@ -493,104 +493,104 @@ ShemuEvalCondition(
     case ND_COND_OVERFLOW: // O
         if (GET_FLAG(Context, NDR_RFLAG_OF) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_OVERFLOW): // NO
         if (GET_FLAG(Context, NDR_RFLAG_OF) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_CARRY: // C/B/NAE
         if (GET_FLAG(Context, NDR_RFLAG_CF) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE
         if (GET_FLAG(Context, NDR_RFLAG_CF) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_ZERO: // E/Z
         if (GET_FLAG(Context, NDR_RFLAG_ZF) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_ZERO): // NE/NZ
         if (GET_FLAG(Context, NDR_RFLAG_ZF) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_BELOW_OR_EQUAL: // BE/NA
         if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE
         if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_SIGN: // S
         if (GET_FLAG(Context, NDR_RFLAG_SF) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_SIGN): // NS
         if (GET_FLAG(Context, NDR_RFLAG_SF) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_PARITY: // P
         if (GET_FLAG(Context, NDR_RFLAG_PF) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_PARITY): // NP
         if (GET_FLAG(Context, NDR_RFLAG_PF) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_LESS: // L/NGE
         if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_LESS): // NL/GE
         if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_LESS_OR_EQUAL: // LE/NG
         if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) |
             (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G
         if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) |
             (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0)
         {
-            return true;
+            return ND_TRUE;
         }
         break;
     }
 
-    return false;
+    return ND_FALSE;
 
 }
 
@@ -598,11 +598,11 @@ ShemuEvalCondition(
 //
 // ShemuIsShellcodePtr
 //
-inline static bool
+inline static ND_BOOL
 ShemuIsShellcodePtr(
     SHEMU_CONTEXT *Context,
-    uint64_t Gla,
-    uint32_t Size
+    ND_UINT64 Gla,
+    ND_UINT32 Size
     )
 {
     return (Gla >= Context->ShellcodeBase && Gla < Context->ShellcodeBase + Context->ShellcodeSize &&
@@ -613,11 +613,11 @@ ShemuIsShellcodePtr(
 //
 // ShemuIsStackPtr
 //
-inline static bool
+inline static ND_BOOL
 ShemuIsStackPtr(
     SHEMU_CONTEXT *Context,
-    uint64_t Gla,
-    uint32_t Size
+    ND_UINT64 Gla,
+    ND_UINT32 Size
 )
 {
     return (Gla >= Context->StackBase && Gla < Context->StackBase + Context->StackSize &&
@@ -628,12 +628,12 @@ ShemuIsStackPtr(
 //
 // ShemuGetGprValue
 //
-static uint64_t
+static ND_UINT64
 ShemuGetGprValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg,
-    uint32_t Size,
-    bool High8
+    ND_UINT32 Reg,
+    ND_UINT32 Size,
+    ND_BOOL High8
     )
 {
     switch (Size)
@@ -667,13 +667,13 @@ ShemuGetGprValue(
 static void
 ShemuSetGprValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg,
-    uint32_t Size,
-    uint64_t Value,
-    bool High8
+    ND_UINT32 Reg,
+    ND_UINT32 Size,
+    ND_UINT64 Value,
+    ND_BOOL High8
     )
 {
-    uint32_t bit;
+    ND_UINT32 bit;
 
     switch (Size)
     {
@@ -681,20 +681,20 @@ ShemuSetGprValue(
         if (High8)
         {
             // AH, CH, DH or BH accessed.
-            *((uint8_t *)(&Context->Registers.RegRax + Reg - 4) + 1) = Value & 0xFF;
+            *((ND_UINT8 *)(&Context->Registers.RegRax + Reg - 4) + 1) = Value & 0xFF;
         }
         else
         {
-            *((uint8_t *)(&Context->Registers.RegRax + Reg)) = Value & 0xff;
+            *((ND_UINT8 *)(&Context->Registers.RegRax + Reg)) = Value & 0xff;
         }
         break;
 
     case 2:
-        *((uint16_t *)(&Context->Registers.RegRax + Reg)) = Value & 0xffff;
+        *((ND_UINT16 *)(&Context->Registers.RegRax + Reg)) = Value & 0xffff;
         break;
 
     case 4:
-        // Higher uint32_t is always set to zero.
+        // Higher ND_UINT32 is always set to zero.
         *(&Context->Registers.RegRax + Reg) = Value & 0xffffffff;
         break;
 
@@ -720,13 +720,13 @@ ShemuSetGprValue(
 //
 // ShemuCmpGprValue
 //
-static bool
+static ND_BOOL
 ShemuCmpGprValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg,
-    uint32_t Size,
-    uint64_t Value,
-    bool High8
+    ND_UINT32 Reg,
+    ND_UINT32 Size,
+    ND_UINT64 Value,
+    ND_BOOL High8
     )
 {
     switch (Size)
@@ -735,18 +735,18 @@ ShemuCmpGprValue(
         if (High8)
         {
             // AH, CH, DH or BH.
-            return *((uint8_t *)(&Context->Registers.RegRax + Reg - 4) + 1) == (Value & 0xff);
+            return *((ND_UINT8 *)(&Context->Registers.RegRax + Reg - 4) + 1) == (Value & 0xff);
         }
         else
         {
-            return *((uint8_t *)(&Context->Registers.RegRax + Reg)) == (Value & 0xff);
+            return *((ND_UINT8 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xff);
         }
 
     case 2:
-        return *((uint16_t *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffff);
+        return *((ND_UINT16 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffff);
 
     case 4:
-        return *((uint32_t *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffffffff);
+        return *((ND_UINT32 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffffffff);
 
     default:
         return *(&Context->Registers.RegRax + Reg) == Value;
@@ -757,10 +757,10 @@ ShemuCmpGprValue(
 //
 // ShemuGetSegValue
 //
-static uint64_t
+static ND_UINT64
 ShemuGetSegValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg
+    ND_UINT32 Reg
     )
 {
     switch (Reg)
@@ -789,8 +789,8 @@ ShemuGetSegValue(
 static void
 ShemuSetSegValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg,
-    uint16_t Value
+    ND_UINT32 Reg,
+    ND_UINT16 Value
     )
 {
     switch (Reg)
@@ -820,10 +820,10 @@ ShemuSetSegValue(
 //
 // ShemuGetSegBase
 //
-static uint64_t
+static ND_UINT64
 ShemuGetSegBase(
     SHEMU_CONTEXT *Context,
-    uint32_t Reg
+    ND_UINT32 Reg
     )
 {
     switch (Reg)
@@ -849,22 +849,22 @@ ShemuGetSegBase(
 //
 // ShemuComputeLinearAddress
 //
-static uint64_t
+static ND_UINT64
 ShemuComputeLinearAddress(
     SHEMU_CONTEXT *Context,
     PND_OPERAND Operand
     )
 {
-    uint64_t gla = 0;
+    ND_UINT64 gla = 0;
 
     if (Operand->Info.Memory.HasBase)
     {
-        gla += ShemuGetGprValue(Context, Operand->Info.Memory.Base, Operand->Info.Memory.BaseSize, false);
+        gla += ShemuGetGprValue(Context, Operand->Info.Memory.Base, Operand->Info.Memory.BaseSize, ND_FALSE);
     }
 
     if (Operand->Info.Memory.HasIndex)
     {
-        gla += ShemuGetGprValue(Context, Operand->Info.Memory.Index, Operand->Info.Memory.IndexSize, false) *
+        gla += ShemuGetGprValue(Context, Operand->Info.Memory.Index, Operand->Info.Memory.IndexSize, ND_FALSE) *
                                 Operand->Info.Memory.Scale;
     }
 
@@ -883,12 +883,12 @@ ShemuComputeLinearAddress(
     // Special handling for BT, BTR, BTS, BTC instructions with bitbase addressing.
     if (Operand->Info.Memory.IsBitbase)
     {
-        uint64_t bitbase, op1size, op2size, reg;
+        ND_UINT64 bitbase, op1size, op2size, reg;
 
         op1size = Context->Instruction.Operands[0].Size;
         op2size = Context->Instruction.Operands[1].Size;
 
-        reg = ((uint64_t*)&Context->Registers.RegRax)[Context->Instruction.Operands[1].Info.Register.Reg];
+        reg = ((ND_UINT64*)&Context->Registers.RegRax)[Context->Instruction.Operands[1].Info.Register.Reg];
 
         // Note: only BT* with register source (NOT immediate) support bitbase addressing.
         bitbase = ND_SIGN_EX(op2size, reg);
@@ -948,27 +948,27 @@ ShemuComputeLinearAddress(
 static SHEMU_STATUS
 ShemuGetMemValue(
     SHEMU_CONTEXT *Context,
-    uint64_t Gla,
-    uint32_t Size,
-    uint8_t *Value
+    ND_UINT64 Gla,
+    ND_UINT32 Size,
+    ND_UINT8 *Value
     )
 {
-    uint8_t *addr;
-    uint32_t offset;
+    ND_UINT8 *addr;
+    ND_UINT32 offset;
 
     if (ShemuIsShellcodePtr(Context, Gla, Size))
     {
         addr = Context->Shellcode;
-        offset = (uint32_t)(Gla - Context->ShellcodeBase);
+        offset = (ND_UINT32)(Gla - Context->ShellcodeBase);
     }
     else if (ShemuIsStackPtr(Context, Gla, Size))
     {
         addr = Context->Stack;
-        offset = (uint32_t)(Gla - Context->StackBase);
+        offset = (ND_UINT32)(Gla - Context->StackBase);
     }
     else
     {
-        bool res = false;
+        ND_BOOL res = ND_FALSE;
 
         // We allow a maximum number of external memory accesses, due to performance reasons.
         if (++Context->ExtMemAccess > Context->MemThreshold)
@@ -979,16 +979,16 @@ ShemuGetMemValue(
         // NOTE: The accessed GLA may partially access an internal address (shellcode or stack) and an external address.
         // Since the AccessMemory callback can be provided with the full SHEMU_CONTEXT, the integrator can choose how
         // to handle those accesses; some options are:
-        // - Don't handle them at all, and return error (false);
+        // - Don't handle them at all, and return error (ND_FALSE);
         // - Handle them by reading the actual memory value; this has the disadvantage that if the shellcode/stack 
         //   portion has been modified due to emulation, the AccessMemory function would return the original memory 
         //   value;
         // - Handle them properly, by returning the emulated values for the internal addresses, and the external
         //   values for the external addresses.
         // bdshemu does not care directly about this, and lets the integrator choose his own strategy.
-        if (NULL != Context->AccessMemory)
+        if (ND_NULL != Context->AccessMemory)
         {
-            res = Context->AccessMemory(Context, Gla, Size, Value, false);
+            res = Context->AccessMemory(Context, Gla, Size, Value, ND_FALSE);
         }
 
         if (res)
@@ -1005,13 +1005,13 @@ ShemuGetMemValue(
         *Value = *(addr + offset);
         break;
     case 2:
-        *(uint16_t *)Value = *(uint16_t *)(addr + offset);
+        *(ND_UINT16 *)Value = *(ND_UINT16 *)(addr + offset);
         break;
     case 4:
-        *(uint32_t *)Value = *(uint32_t *)(addr + offset);
+        *(ND_UINT32 *)Value = *(ND_UINT32 *)(addr + offset);
         break;
     case 8:
-        *(uint64_t *)Value = *(uint64_t *)(addr + offset);
+        *(ND_UINT64 *)Value = *(ND_UINT64 *)(addr + offset);
         break;
     default:
         shemu_memcpy(Value, addr + offset, Size);
@@ -1028,18 +1028,18 @@ ShemuGetMemValue(
 static SHEMU_STATUS
 ShemuSetMemValue(
     SHEMU_CONTEXT *Context,
-    uint64_t Gla,
-    uint32_t Size,
-    uint8_t *Value
+    ND_UINT64 Gla,
+    ND_UINT32 Size,
+    ND_UINT8 *Value
     )
 {
-    uint8_t *addr;
-    uint32_t offset;
+    ND_UINT8 *addr;
+    ND_UINT32 offset;
 
     if (ShemuIsShellcodePtr(Context, Gla, Size))
     {
         addr = Context->Shellcode;
-        offset = (uint32_t)(Gla - Context->ShellcodeBase);
+        offset = (ND_UINT32)(Gla - Context->ShellcodeBase);
 
         // Bypass self-writes, if needed to.
         if (!!(Context->Options & SHEMU_OPT_BYPASS_SELF_WRITES))
@@ -1050,11 +1050,11 @@ ShemuSetMemValue(
     else if (ShemuIsStackPtr(Context, Gla, Size))
     {
         addr = Context->Stack;
-        offset = (uint32_t)(Gla - Context->StackBase);
+        offset = (ND_UINT32)(Gla - Context->StackBase);
     }
     else
     {
-        bool res = false;
+        ND_BOOL res = ND_FALSE;
 
         // We allow a maximum number of external memory accesses, due to performance reasons.
         if (++Context->ExtMemAccess > Context->MemThreshold)
@@ -1070,9 +1070,9 @@ ShemuSetMemValue(
         // - Create a store-buffer like structure, where every external store is cached; when a load is issued on
         //   a previously written address, the value from the store-buffer can be returned;
         // For obvious reasons, actually storing the value at the indicated address is a very, very bad idea.
-        if (NULL != Context->AccessMemory)
+        if (ND_NULL != Context->AccessMemory)
         {
-            res = Context->AccessMemory(Context, Gla, Size, Value, true);
+            res = Context->AccessMemory(Context, Gla, Size, Value, ND_TRUE);
         }
 
         if (res)
@@ -1089,13 +1089,13 @@ ShemuSetMemValue(
         *(addr + offset) = *Value & 0xff;
         break;
     case 2:
-        *(uint16_t *)(addr + offset) = *(uint16_t *)Value & 0xffff;
+        *(ND_UINT16 *)(addr + offset) = *(ND_UINT16 *)Value & 0xffff;
         break;
     case 4:
-        *(uint32_t *)(addr + offset) = *(uint32_t *)Value & 0xffffffff;
+        *(ND_UINT32 *)(addr + offset) = *(ND_UINT32 *)Value & 0xffffffff;
         break;
     case 8:
-        *(uint64_t *)(addr + offset) = *(uint64_t *)Value;
+        *(ND_UINT64 *)(addr + offset) = *(ND_UINT64 *)Value;
         break;
     default:
         shemu_memcpy(addr + offset, Value, Size);
@@ -1112,7 +1112,7 @@ ShemuSetMemValue(
 static SHEMU_STATUS
 ShemuGetOperandValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Operand,
+    ND_UINT32 Operand,
     SHEMU_VALUE *Value
     )
 {
@@ -1186,9 +1186,9 @@ ShemuGetOperandValue(
     }
     else if (op->Type == ND_OP_MEM)
     {
-        uint64_t gla = ShemuComputeLinearAddress(Context, op);
-        uint32_t offset;
-        uint8_t seg;
+        ND_UINT64 gla = ShemuComputeLinearAddress(Context, op);
+        ND_UINT32 offset;
+        ND_UINT8 seg;
 
         if (op->Info.Memory.IsAG)
         {
@@ -1211,7 +1211,7 @@ ShemuGetOperandValue(
         }
 
         // Check if this is a TIB/PCR access. Make sure the FS/GS register is used for the access, in order to avoid
-        // false positives where legitimate code accesses a linear TIB directly.
+        // ND_FALSE positives where legitimate code accesses a linear TIB directly.
         // Note that this covers accesses to the PEB field inside the TIB.
         if (gla == Context->TibBase + offset && Context->Instruction.Seg == seg)
         {
@@ -1252,21 +1252,21 @@ ShemuGetOperandValue(
         // If this is a stack access, we need to update the stack pointer.
         if (op->Info.Memory.IsStack)
         {
-            uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false);
+            ND_UINT64 regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), ND_FALSE);
 
             regval += op->Size;
 
-            ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false);
+            ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, ND_FALSE);
         }
 
         // If this is a string operation, make sure we update RSI/RDI.
         if (op->Info.Memory.IsString)
         {
-            uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false);
+            ND_UINT64 regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE);
 
             regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size;
 
-            ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false);
+            ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE);
         }
 
 done_gla:;
@@ -1298,7 +1298,7 @@ done_gla:;
 static SHEMU_STATUS
 ShemuSetOperandValue(
     SHEMU_CONTEXT *Context,
-    uint32_t Operand,
+    ND_UINT32 Operand,
     SHEMU_VALUE *Value
     )
 {
@@ -1391,7 +1391,7 @@ ShemuSetOperandValue(
     else if (op->Type == ND_OP_MEM)
     {
         // Compute the GLA.
-        uint64_t gla = ShemuComputeLinearAddress(Context, op);
+        ND_UINT64 gla = ShemuComputeLinearAddress(Context, op);
 
         // Handle self-write. We store a 1 for each written byte inside the shellcode space. Once the modified bytes
         // are executed, we can trigger the self-write detection.
@@ -1403,8 +1403,8 @@ ShemuSetOperandValue(
         // Handle RIP save on the stack.
         if (ShemuIsStackPtr(Context, gla, MAX(op->Size, Context->Instruction.WordLength)))
         {
-            uint8_t stckstrlen = 0;
-            uint32_t i;
+            ND_UINT8 stckstrlen = 0;
+            ND_UINT32 i;
 
             // Note: only Context->Instruction.WordLength bits are flagged as RIP, as that is the RIP size.
             if (Context->Instruction.Instruction == ND_INS_CALLNR ||
@@ -1458,7 +1458,7 @@ ShemuSetOperandValue(
                 // Make sure the value is not present inside a non-dirty GPR. 
                 for (i = 0; i < 16; i++)
                 {
-                    if (ShemuCmpGprValue(Context, i, Value->Size, Value->Value.Qwords[0], false) &&
+                    if (ShemuCmpGprValue(Context, i, Value->Size, Value->Value.Qwords[0], ND_FALSE) &&
                         (0 == (Context->DirtyGprBitmap & (1 << i))))
                     {
                         // A register is saved on the stack, but that register wasn't written during the emulation.
@@ -1492,21 +1492,21 @@ ShemuSetOperandValue(
         // If this is a stack access, we need to update the stack pointer.
         if (op->Info.Memory.IsStack)
         {
-            uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false);
+            ND_UINT64 regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), ND_FALSE);
 
             regval -= op->Size;
 
-            ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false);
+            ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, ND_FALSE);
         }
 
         // If this is a string operation, make sure we update RSI/RDI.
         if (op->Info.Memory.IsString)
         {
-            uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false);
+            ND_UINT64 regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE);
 
             regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size;
 
-            ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false);
+            ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE);
         }
     }
     else
@@ -1523,23 +1523,23 @@ ShemuSetOperandValue(
 //
 static void
 ShemuMultiply64Unsigned(
-    uint64_t Operand1,
-    uint64_t Operand2,
-    uint64_t *ResHigh,
-    uint64_t *ResLow
+    ND_UINT64 Operand1,
+    ND_UINT64 Operand2,
+    ND_UINT64 *ResHigh,
+    ND_UINT64 *ResLow
     )
 {
-    uint64_t xLow = (uint64_t)(uint32_t)Operand1;
-    uint64_t xHigh = Operand1 >> 32;
-    uint64_t yLow = (uint64_t)(uint32_t)Operand2;
-    uint64_t yHigh = Operand2 >> 32;
+    ND_UINT64 xLow = (ND_UINT64)(ND_UINT32)Operand1;
+    ND_UINT64 xHigh = Operand1 >> 32;
+    ND_UINT64 yLow = (ND_UINT64)(ND_UINT32)Operand2;
+    ND_UINT64 yHigh = Operand2 >> 32;
 
-    uint64_t p0 = xLow * yLow;
-    uint64_t p1 = xLow * yHigh;
-    uint64_t p2 = xHigh * yLow;
-    uint64_t p3 = xHigh * yHigh;
+    ND_UINT64 p0 = xLow * yLow;
+    ND_UINT64 p1 = xLow * yHigh;
+    ND_UINT64 p2 = xHigh * yLow;
+    ND_UINT64 p3 = xHigh * yHigh;
 
-    uint32_t cy = (uint32_t)(((p0 >> 32) + (uint32_t)p1 + (uint32_t)p2) >> 32);
+    ND_UINT32 cy = (ND_UINT32)(((p0 >> 32) + (ND_UINT32)p1 + (ND_UINT32)p2) >> 32);
 
     *ResLow = p0 + (p1 << 32) + (p2 << 32);
     *ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + cy;
@@ -1551,13 +1551,13 @@ ShemuMultiply64Unsigned(
 //
 static void
 ShemuMultiply64Signed(
-    int64_t Operand1,
-    int64_t Operand2,
-    int64_t *ResHigh,
-    int64_t *ResLow
+    ND_SINT64 Operand1,
+    ND_SINT64 Operand2,
+    ND_SINT64 *ResHigh,
+    ND_SINT64 *ResLow
     )
 {
-    ShemuMultiply64Unsigned((uint64_t)Operand1, (uint64_t)Operand2, (uint64_t *)ResHigh, (uint64_t *)ResLow);
+    ShemuMultiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow);
     if (Operand1 < 0LL) *ResHigh -= Operand2;
     if (Operand2 < 0LL) *ResHigh -= Operand1;
 }
@@ -1566,19 +1566,19 @@ ShemuMultiply64Signed(
 //
 // ShemuCheckDiv
 //
-static bool
+static ND_BOOL
 ShemuCheckDiv(
-    uint64_t Divident,
-    uint64_t Divider,
-    uint8_t Size            // The size of the Source (Divider). The Divident is twice as large.
+    ND_UINT64 Divident,
+    ND_UINT64 Divider,
+    ND_UINT8 Size            // The size of the Source (Divider). The Divident is twice as large.
     )
 {
-    // Returns true if all checks are OK, and Divident / Divider will not cause #DE.
+    // Returns ND_TRUE if all checks are OK, and Divident / Divider will not cause #DE.
 
     if (Divider == 0)
     {
         // Division by zero.
-        return false;
+        return ND_FALSE;
     }
 
     // If the result won't fit in the destination, a #DE would be generated.
@@ -1587,45 +1587,45 @@ ShemuCheckDiv(
     case 1:
         if (((Divident >> 8) & 0xFF) >= Divider)
         {
-            return false;
+            return ND_FALSE;
         }
         break;
 
     case 2:
         if (((Divident >> 16) & 0xFFFF) >= Divider)
         {
-            return false;
+            return ND_FALSE;
         }
         break;
 
     case 4:
         if (((Divident >> 32) & 0xFFFFFFFF) >= Divider)
         {
-            return false;
+            return ND_FALSE;
         }
         break;
 
     default:
         // 64 bit source division is not supported.
-        return false;
+        return ND_FALSE;
     }
 
-    return true;
+    return ND_TRUE;
 }
 
 
 //
 // ShemuCheckIdiv
 //
-static bool
+static ND_BOOL
 ShemuCheckIdiv(
-    int64_t Divident,
-    int64_t Divider,
-    uint8_t Size            // The size of the Source (Divider).
+    ND_SINT64 Divident,
+    ND_SINT64 Divider,
+    ND_UINT8 Size            // The size of the Source (Divider).
     )
 {
-    bool neg1, neg2;
-    uint64_t quotient, max;
+    ND_BOOL neg1, neg2;
+    ND_UINT64 quotient, max;
 
     neg1 = Divident < 0;
     neg2 = Divider < 0;
@@ -1643,11 +1643,11 @@ ShemuCheckIdiv(
     // Do checks when dividing positive values.
     if (!ShemuCheckDiv(Divident, Divider, Size))
     {
-        return false;
+        return ND_FALSE;
     }
 
     // Get the positive quotient.
-    quotient = (uint64_t)Divident / (uint64_t)Divider;
+    quotient = (ND_UINT64)Divident / (ND_UINT64)Divider;
 
     max = (Size == 1) ? 0x80 : (Size == 2) ? 0x8000 : (Size == 4) ? 0x80000000 : 0x8000000000000000;
 
@@ -1656,7 +1656,7 @@ ShemuCheckIdiv(
         // The Divident and the Divider have different signs, the quotient must be negative. If it's positive => #DE.
         if (ND_GET_SIGN(Size, quotient) && quotient != max)
         {
-            return false;
+            return ND_FALSE;
         }
     }
     else
@@ -1665,17 +1665,18 @@ ShemuCheckIdiv(
         // negative => #DE.
         if (ND_GET_SIGN(Size, quotient))
         {
-            return false;
+            return ND_FALSE;
         }
     }
 
-    return true;
+    return ND_TRUE;
 }
 
 
 //
 // ShemuPrintContext
 //
+#ifndef BDDISASM_NO_FORMAT
 static void
 ShemuPrintContext(
     SHEMU_CONTEXT *Context
@@ -1708,6 +1709,9 @@ ShemuPrintContext(
 
     shemu_printf(Context, "Emulating: 0x%016llx %s\n", Context->Registers.RegRip, text);
 }
+#else
+#define ShemuPrintContext(Context)
+#endif // !BDDISASM_NO_FORMAT 
 
 
 //
@@ -1719,26 +1723,26 @@ ShemuEmulate(
     )
 {
     SHEMU_VALUE res = { 0 }, dst = { 0 }, src = { 0 }, rcx = { 0 }, aux = { 0 };
-    bool stop = false, cf;
-    uint16_t cs = 0;
-    uint64_t tsc = 0x1248fe7a5c30;
+    ND_BOOL stop = ND_FALSE, cf;
+    ND_UINT16 cs = 0;
+    ND_UINT64 tsc = 0x1248fe7a5c30;
 
-    if (NULL == Context)
+    if (ND_NULL == Context)
     {
         return SHEMU_ABORT_INVALID_PARAMETER;
     }
 
-    if (NULL == Context->Shellcode)
+    if (ND_NULL == Context->Shellcode)
     {
         return SHEMU_ABORT_INVALID_PARAMETER;
     }
 
-    if (NULL == Context->Stack)
+    if (ND_NULL == Context->Stack)
     {
         return SHEMU_ABORT_INVALID_PARAMETER;
     }
 
-    if (NULL == Context->Intbuf)
+    if (ND_NULL == Context->Intbuf)
     {
         return SHEMU_ABORT_INVALID_PARAMETER;
     }
@@ -1761,8 +1765,8 @@ ShemuEmulate(
     while (Context->InstructionsCount++ < Context->MaxInstructionsCount)
     {
         NDSTATUS ndstatus;
-        uint64_t rip;
-        uint32_t i;
+        ND_UINT64 rip;
+        ND_UINT32 i;
 
         tsc++;
 
@@ -1798,7 +1802,7 @@ ShemuEmulate(
 
         // Decode the next instruction.
         ndstatus = NdDecodeEx(&Context->Instruction, Context->Shellcode + rip,
-                              Context->ShellcodeSize - (size_t)rip, Context->Mode, Context->Mode);
+                              Context->ShellcodeSize - (ND_SIZET)rip, Context->Mode, Context->Mode);
         if (!ND_SUCCESS(ndstatus))
         {
             if (ND_STATUS_BUFFER_TOO_SMALL == ndstatus)
@@ -1843,7 +1847,7 @@ ShemuEmulate(
         {
         case ND_INS_FNSTENV:
             src.Size = Context->Instruction.Operands[0].Size;
-            src.Value.FpuEnvironment.FpuInstructionPointer = (uint32_t)Context->Registers.FpuRip;
+            src.Value.FpuEnvironment.FpuInstructionPointer = (ND_UINT32)Context->Registers.FpuRip;
             SET_OP(Context, 0, &src);
             break;
 
@@ -2016,14 +2020,14 @@ ShemuEmulate(
         case ND_INS_PUSHA:
         case ND_INS_PUSHAD:
             src.Size = 32;
-            src.Value.Dwords[7] = (uint32_t)Context->Registers.RegRax;
-            src.Value.Dwords[6] = (uint32_t)Context->Registers.RegRcx;
-            src.Value.Dwords[5] = (uint32_t)Context->Registers.RegRdx;
-            src.Value.Dwords[4] = (uint32_t)Context->Registers.RegRbx;
-            src.Value.Dwords[3] = (uint32_t)Context->Registers.RegRsp;
-            src.Value.Dwords[2] = (uint32_t)Context->Registers.RegRbp;
-            src.Value.Dwords[1] = (uint32_t)Context->Registers.RegRsi;
-            src.Value.Dwords[0] = (uint32_t)Context->Registers.RegRdi;
+            src.Value.Dwords[7] = (ND_UINT32)Context->Registers.RegRax;
+            src.Value.Dwords[6] = (ND_UINT32)Context->Registers.RegRcx;
+            src.Value.Dwords[5] = (ND_UINT32)Context->Registers.RegRdx;
+            src.Value.Dwords[4] = (ND_UINT32)Context->Registers.RegRbx;
+            src.Value.Dwords[3] = (ND_UINT32)Context->Registers.RegRsp;
+            src.Value.Dwords[2] = (ND_UINT32)Context->Registers.RegRbp;
+            src.Value.Dwords[1] = (ND_UINT32)Context->Registers.RegRsi;
+            src.Value.Dwords[0] = (ND_UINT32)Context->Registers.RegRdi;
             SET_OP(Context, 1, &src);
             break;
 
@@ -2074,9 +2078,9 @@ ShemuEmulate(
             }
             else
             {
-                int64_t val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]);
+                ND_SINT64 val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]);
                 val = val >> src.Value.Qwords[0];
-                res.Value.Qwords[0] = (uint64_t)val;
+                res.Value.Qwords[0] = (ND_UINT64)val;
             }
 
             if (src.Value.Qwords[0] != 0)
@@ -2105,13 +2109,13 @@ ShemuEmulate(
         case ND_INS_ROL:
         case ND_INS_ROR:
             {
-                uint32_t cnt, tempcnt, cntmask;
-                uint8_t tempCF = 0;
+                ND_UINT32 cnt, tempcnt, cntmask;
+                ND_UINT8 tempCF = 0;
 
                 GET_OP(Context, 0, &dst);
                 GET_OP(Context, 1, &src);
 
-                cnt = (uint32_t)src.Value.Qwords[0];
+                cnt = (ND_UINT32)src.Value.Qwords[0];
                 tempcnt = 0;
                 cntmask = ((dst.Size == 8) ? 0x3F : 0x1F);
 
@@ -2160,7 +2164,7 @@ ShemuEmulate(
                     {
                         tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]);
                         dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + 
-                                              ((uint64_t)GET_FLAG(Context, NDR_RFLAG_CF) << (dst.Size * 8 - 1));
+                                              ((ND_UINT64)GET_FLAG(Context, NDR_RFLAG_CF) << (dst.Size * 8 - 1));
                         SET_FLAG(Context, NDR_RFLAG_CF, tempCF);
                         tempcnt--;
                     }
@@ -2190,7 +2194,7 @@ ShemuEmulate(
                     while (tempcnt != 0)
                     {
                         tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]);
-                        dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + ((uint64_t)tempCF << (dst.Size * 8 - 1));
+                        dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + ((ND_UINT64)tempCF << (dst.Size * 8 - 1));
                         tempcnt--;
                     }
 
@@ -2379,7 +2383,7 @@ ShemuEmulate(
 
         case ND_INS_JMPFD:
         case ND_INS_CALLFD:
-            cs = (uint16_t)Context->Instruction.Operands[0].Info.Address.BaseSeg;
+            cs = (ND_UINT16)Context->Instruction.Operands[0].Info.Address.BaseSeg;
             goto check_far_branch;
 
         case ND_INS_JMPFI:
@@ -2414,13 +2418,13 @@ ShemuEmulate(
             switch (Context->Instruction.WordLength)
             {
             case 2:
-                cs = (uint16_t)src.Value.Words[1];
+                cs = (ND_UINT16)src.Value.Words[1];
                 break;
             case 4:
-                cs = (uint16_t)src.Value.Dwords[1];
+                cs = (ND_UINT16)src.Value.Dwords[1];
                 break;
             case 8:
-                cs = (uint16_t)src.Value.Qwords[1];
+                cs = (ND_UINT16)src.Value.Qwords[1];
                 break;
             default:
                 cs = 0;
@@ -2436,7 +2440,7 @@ check_far_branch:
             // We may, in the future, emulate far branches, but they imply some tricky context switches (including
             // the default TEB), so it may not be as straight forward as it seems. For now, all we wish to achieve 
             // is detection of far branches in long-mode, from Wow 64.
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_INS_LODS:
@@ -2539,7 +2543,7 @@ check_far_branch:
                 }
                 else
                 {
-                    res.Value.Words[0] = (int8_t)dst.Value.Bytes[0] * (int8_t)src.Value.Bytes[0];
+                    res.Value.Words[0] = (ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0];
                 }
             }
             else if (dst.Size == 2)
@@ -2550,7 +2554,7 @@ check_far_branch:
                 }
                 else
                 {
-                    res.Value.Dwords[0] = (int16_t)dst.Value.Words[0] * (int16_t)src.Value.Words[0];
+                    res.Value.Dwords[0] = (ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0];
                 }
             }
             else if (dst.Size == 4)
@@ -2561,7 +2565,7 @@ check_far_branch:
                 }
                 else
                 {
-                    res.Value.Qwords[0] = (int64_t)(int32_t)dst.Value.Dwords[0] * (int64_t)(int32_t)src.Value.Dwords[0];
+                    res.Value.Qwords[0] = (ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0];
                 }
             }
             else
@@ -2574,7 +2578,7 @@ check_far_branch:
                 else
                 {
                     ShemuMultiply64Signed(dst.Value.Qwords[0], src.Value.Qwords[0],
-                                          (int64_t*)&res.Value.Qwords[1], (int64_t*)&res.Value.Qwords[0]);
+                                          (ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]);
                 }
             }
 
@@ -2584,11 +2588,11 @@ check_far_branch:
                 switch (dst.Size)
                 {
                 case 1:
-                    *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0];
+                    *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0];
                     break;
                 case 2:
-                    *((uint16_t*)&Context->Registers.RegRdx) = res.Value.Words[1];
-                    *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0];
+                    *((ND_UINT16*)&Context->Registers.RegRdx) = res.Value.Words[1];
+                    *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0];
                     break;
                 case 4:
                     Context->Registers.RegRdx = res.Value.Dwords[1];
@@ -2608,7 +2612,7 @@ check_far_branch:
 
             if (ND_INS_MUL == Context->Instruction.Instruction)
             {
-                uint8_t cfof = 0;
+                ND_UINT8 cfof = 0;
 
                 // CF and OF are set to 0 if the high part of the result is 0, otherwise they are set to 1.
                 switch (dst.Size)
@@ -2634,7 +2638,7 @@ check_far_branch:
             {
                 // The CF and OF flags are set when the signed integer value of the intermediate product differs from
                 // the sign extended operand - size - truncated product, otherwise the CF and OF flags are cleared.
-                uint8_t cfof = 0, sign = 0;
+                ND_UINT8 cfof = 0, sign = 0;
 
                 sign = ND_MSB(res.Size, res.Value.Qwords[0]);
 
@@ -2642,19 +2646,19 @@ check_far_branch:
                 {
                 case 1:
                     cfof = (0 == res.Value.Bytes[1] && 0 == sign) || 
-                           ((uint8_t)-1 == res.Value.Bytes[1] && 1 == sign) ? 0 : 1;
+                           ((ND_UINT8)-1 == res.Value.Bytes[1] && 1 == sign) ? 0 : 1;
                     break;
                 case 2:
                     cfof = (0 == res.Value.Words[1] && 0 == sign) || 
-                           ((uint16_t)-1 == res.Value.Words[1] && 1 == sign) ? 0 : 1;
+                           ((ND_UINT16)-1 == res.Value.Words[1] && 1 == sign) ? 0 : 1;
                     break;
                 case 4:
                     cfof = (0 == res.Value.Dwords[1] && 0 == sign) || 
-                           ((uint32_t)-1 == res.Value.Dwords[1] && 1 == sign) ? 0 : 1;
+                           ((ND_UINT32)-1 == res.Value.Dwords[1] && 1 == sign) ? 0 : 1;
                     break;
                 case 8:
                     cfof = (0 == res.Value.Qwords[1] && 0 == sign) || 
-                           ((uint64_t)-1 == res.Value.Qwords[1] && 1 == sign) ? 0 : 1;
+                           ((ND_UINT64)-1 == res.Value.Qwords[1] && 1 == sign) ? 0 : 1;
                     break;
                 }
 
@@ -2671,97 +2675,97 @@ check_far_branch:
 
             if (src.Size == 1)
             {
-                uint16_t divident;
+                ND_UINT16 divident;
 
-                divident = (uint16_t)Context->Registers.RegRax;
+                divident = (ND_UINT16)Context->Registers.RegRax;
 
                 if (ND_INS_DIV == Context->Instruction.Instruction)
                 {
                     if (!ShemuCheckDiv(divident, src.Value.Bytes[0], 1))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Bytes[0] = (uint8_t)(divident / src.Value.Bytes[0]);
-                    res.Value.Bytes[1] = (uint8_t)(divident % src.Value.Bytes[0]);
+                    res.Value.Bytes[0] = (ND_UINT8)(divident / src.Value.Bytes[0]);
+                    res.Value.Bytes[1] = (ND_UINT8)(divident % src.Value.Bytes[0]);
                 }
                 else
                 {
-                    if (!ShemuCheckIdiv((int64_t)(int16_t)divident, (int64_t)(int8_t)src.Value.Bytes[0], 1))
+                    if (!ShemuCheckIdiv((ND_SINT64)(ND_SINT16)divident, (ND_SINT64)(ND_SINT8)src.Value.Bytes[0], 1))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Bytes[0] = (int8_t)((int16_t)divident / (int8_t)src.Value.Bytes[0]);
-                    res.Value.Bytes[1] = (int8_t)((int16_t)divident % (int8_t)src.Value.Bytes[0]);
+                    res.Value.Bytes[0] = (ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]);
+                    res.Value.Bytes[1] = (ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]);
                 }
 
                 // Result in AX (AL - quotient, AH - reminder).
-                *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0];
+                *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0];
             }
             else if (src.Size == 2)
             {
-                uint32_t divident;
+                ND_UINT32 divident;
 
-                divident = ((uint32_t)(uint16_t)Context->Registers.RegRdx << 16) | 
-                            (uint32_t)(uint16_t)Context->Registers.RegRax;
+                divident = ((ND_UINT32)(ND_UINT16)Context->Registers.RegRdx << 16) | 
+                            (ND_UINT32)(ND_UINT16)Context->Registers.RegRax;
 
                 if (ND_INS_DIV == Context->Instruction.Instruction)
                 {
                     if (!ShemuCheckDiv(divident, src.Value.Words[0], 2))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Words[0] = (uint16_t)(divident / src.Value.Words[0]);
-                    res.Value.Words[1] = (uint16_t)(divident % src.Value.Words[0]);
+                    res.Value.Words[0] = (ND_UINT16)(divident / src.Value.Words[0]);
+                    res.Value.Words[1] = (ND_UINT16)(divident % src.Value.Words[0]);
                 }
                 else
                 {
-                    if (!ShemuCheckIdiv((int64_t)(int32_t)divident, (int64_t)(int16_t)src.Value.Words[0], 2))
+                    if (!ShemuCheckIdiv((ND_SINT64)(ND_SINT32)divident, (ND_SINT64)(ND_SINT16)src.Value.Words[0], 2))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Words[0] = (int16_t)((int32_t)divident / (int16_t)src.Value.Words[0]);
-                    res.Value.Words[1] = (int16_t)((int32_t)divident % (int16_t)src.Value.Words[0]);
+                    res.Value.Words[0] = (ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]);
+                    res.Value.Words[1] = (ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]);
                 }
 
-                *((uint16_t*)&Context->Registers.RegRdx) = res.Value.Words[1];
-                *((uint16_t*)&Context->Registers.RegRax) = res.Value.Words[0];
+                *((ND_UINT16*)&Context->Registers.RegRdx) = res.Value.Words[1];
+                *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0];
             }
             else if (src.Size == 4)
             {
-                uint64_t divident;
+                ND_UINT64 divident;
 
-                divident = ((uint64_t)(uint32_t)Context->Registers.RegRdx << 32) | 
-                            (uint64_t)(uint32_t)Context->Registers.RegRax;
+                divident = ((ND_UINT64)(ND_UINT32)Context->Registers.RegRdx << 32) | 
+                            (ND_UINT64)(ND_UINT32)Context->Registers.RegRax;
 
                 if (ND_INS_DIV == Context->Instruction.Instruction)
                 {
                     if (!ShemuCheckDiv(divident, src.Value.Dwords[0], 4))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Dwords[0] = (uint32_t)(divident / src.Value.Dwords[0]);
-                    res.Value.Dwords[1] = (uint32_t)(divident % src.Value.Dwords[0]);
+                    res.Value.Dwords[0] = (ND_UINT32)(divident / src.Value.Dwords[0]);
+                    res.Value.Dwords[1] = (ND_UINT32)(divident % src.Value.Dwords[0]);
                 }
                 else
                 {
-                    if (!ShemuCheckIdiv((int64_t)divident, (int64_t)(int32_t)src.Value.Dwords[0], 4))
+                    if (!ShemuCheckIdiv((ND_SINT64)divident, (ND_SINT64)(ND_SINT32)src.Value.Dwords[0], 4))
                     {
-                        stop = true;
+                        stop = ND_TRUE;
                         break;
                     }
 
-                    res.Value.Dwords[0] = (int32_t)((int64_t)divident / (int32_t)src.Value.Dwords[0]);
-                    res.Value.Dwords[1] = (int32_t)((int64_t)divident % (int32_t)src.Value.Dwords[0]);
+                    res.Value.Dwords[0] = (ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]);
+                    res.Value.Dwords[1] = (ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]);
                 }
 
                 Context->Registers.RegRdx = res.Value.Dwords[1];
@@ -2814,29 +2818,29 @@ check_far_branch:
 
         case ND_INS_SAHF:
             {
-                uint8_t ah = (Context->Registers.RegRax >> 8) & 0xFF;
+                ND_UINT8 ah = (Context->Registers.RegRax >> 8) & 0xFF;
                 // Handle reserved bits.
                 ah |= (1 << 1);
                 ah &= ~((1 << 3) | (1 << 5));
-                ((uint8_t *)&Context->Registers.RegFlags)[0] = ah;
+                ((ND_UINT8 *)&Context->Registers.RegFlags)[0] = ah;
             }
             break;
 
         case ND_INS_LAHF:
             {
-                uint8_t ah = ((uint8_t *)&Context->Registers.RegFlags)[0];
-                ((uint8_t *)&Context->Registers.RegRax)[1] = ah;
+                ND_UINT8 ah = ((ND_UINT8 *)&Context->Registers.RegFlags)[0];
+                ((ND_UINT8 *)&Context->Registers.RegRax)[1] = ah;
             }
             break;
 
         case ND_INS_SALC:
             if (GET_FLAG(Context, NDR_RFLAG_CF))
             {
-                *((uint8_t *)&Context->Registers.RegRax) = 0xFF;
+                *((ND_UINT8 *)&Context->Registers.RegRax) = 0xFF;
             }
             else
             {
-                *((uint8_t *)&Context->Registers.RegRax) = 0x0;
+                *((ND_UINT8 *)&Context->Registers.RegRax) = 0x0;
             }
             break;
 
@@ -3021,13 +3025,13 @@ check_far_branch:
                 Context->Flags |= SHEMU_FLAG_SYSCALL;
             }
 
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_INS_SYSCALL:
         case ND_INS_SYSENTER:
             Context->Flags |= SHEMU_FLAG_SYSCALL;
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         // Some basic privileged instructions supported, specific to kernel-mode shellcodes.
@@ -3038,7 +3042,7 @@ check_far_branch:
             }
 
             Context->Flags |= SHEMU_FLAG_SWAPGS;
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_INS_RDMSR:
@@ -3053,7 +3057,7 @@ check_far_branch:
                 Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_READ;
             }
 
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_INS_WRMSR:
@@ -3068,7 +3072,7 @@ check_far_branch:
                 Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_WRITE;
             }
 
-            stop = true;
+            stop = ND_TRUE;
             break;
 
         case ND_INS_SIDT:
@@ -3079,9 +3083,10 @@ check_far_branch:
                 Context->Flags |= SHEMU_FLAG_SIDT;
             }
 
-            stop = true;
+            stop = ND_TRUE;
             break;
 
+#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86)
         case ND_INS_AESIMC:
         case ND_INS_AESDEC:
         case ND_INS_AESDECLAST:
@@ -3091,7 +3096,7 @@ check_far_branch:
             // Make sure AES support is present, and we can emulate AES decryption using AES instructions.
             if (0 == (Context->Options & SHEMU_OPT_SUPPORT_AES))
             {
-                stop = true;
+                stop = ND_TRUE;
                 break;
             }
 
@@ -3119,6 +3124,7 @@ check_far_branch:
             SET_OP(Context, 0, &dst);
             break;
         }
+#endif
 
         case ND_INS_RDTSC:
             src.Size = 4;
diff --git a/bdshemu/bdshemu.vcxproj b/bdshemu/bdshemu.vcxproj
index 9fd7f31..ddf8a46 100644
--- a/bdshemu/bdshemu.vcxproj
+++ b/bdshemu/bdshemu.vcxproj
@@ -1,6 +1,10 @@
 <?xml version="1.0" encoding="utf-8"?>
 <Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
   <ItemGroup Label="ProjectConfigurations">
+    <ProjectConfiguration Include="DebugKernel|ARM64">
+      <Configuration>DebugKernel</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="DebugKernel|Win32">
       <Configuration>DebugKernel</Configuration>
       <Platform>Win32</Platform>
@@ -9,10 +13,18 @@
       <Configuration>DebugKernel</Configuration>
       <Platform>x64</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="Debug|ARM64">
+      <Configuration>Debug</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Debug|Win32">
       <Configuration>Debug</Configuration>
       <Platform>Win32</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="ReleaseKernel|ARM64">
+      <Configuration>ReleaseKernel</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="ReleaseKernel|Win32">
       <Configuration>ReleaseKernel</Configuration>
       <Platform>Win32</Platform>
@@ -21,6 +33,10 @@
       <Configuration>ReleaseKernel</Configuration>
       <Platform>x64</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="Release|ARM64">
+      <Configuration>Release</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Release|Win32">
       <Configuration>Release</Configuration>
       <Platform>Win32</Platform>
@@ -79,6 +95,12 @@
     <PlatformToolset>v142</PlatformToolset>
     <CharacterSet>Unicode</CharacterSet>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <UseDebugLibraries>true</UseDebugLibraries>
+    <PlatformToolset>v142</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'" Label="Configuration">
     <ConfigurationType>StaticLibrary</ConfigurationType>
     <UseDebugLibraries>true</UseDebugLibraries>
@@ -88,6 +110,15 @@
     <DriverTargetPlatform>Desktop</DriverTargetPlatform>
     <SupportsPackaging>false</SupportsPackaging>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <UseDebugLibraries>true</UseDebugLibraries>
+    <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
+    <CharacterSet>Unicode</CharacterSet>
+    <TargetVersion></TargetVersion>
+    <DriverTargetPlatform>Desktop</DriverTargetPlatform>
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+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="Configuration">
     <ConfigurationType>StaticLibrary</ConfigurationType>
     <UseDebugLibraries>false</UseDebugLibraries>
@@ -95,6 +126,13 @@
     <WholeProgramOptimization>false</WholeProgramOptimization>
     <CharacterSet>Unicode</CharacterSet>
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+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <UseDebugLibraries>false</UseDebugLibraries>
+    <PlatformToolset>v142</PlatformToolset>
+    <WholeProgramOptimization>false</WholeProgramOptimization>
+    <CharacterSet>Unicode</CharacterSet>
+  </PropertyGroup>
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     <ConfigurationType>StaticLibrary</ConfigurationType>
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@@ -105,6 +143,16 @@
     <DriverTargetPlatform>Desktop</DriverTargetPlatform>
     <SupportsPackaging>false</SupportsPackaging>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'" Label="Configuration">
+    <ConfigurationType>StaticLibrary</ConfigurationType>
+    <UseDebugLibraries>false</UseDebugLibraries>
+    <PlatformToolset>WindowsKernelModeDriver10.0</PlatformToolset>
+    <WholeProgramOptimization>false</WholeProgramOptimization>
+    <CharacterSet>Unicode</CharacterSet>
+    <TargetVersion></TargetVersion>
+    <DriverTargetPlatform>Desktop</DriverTargetPlatform>
+    <SupportsPackaging>false</SupportsPackaging>
+  </PropertyGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
   <ImportGroup Label="ExtensionSettings">
   </ImportGroup>
@@ -125,15 +173,27 @@
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     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'" Label="PropertySheets">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <PropertyGroup Label="UserMacros" />
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
     <LinkIncremental>true</LinkIncremental>
@@ -153,12 +213,24 @@
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <LinkIncremental>true</LinkIncremental>
+    <TargetExt>.lib</TargetExt>
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'">
     <LinkIncremental>true</LinkIncremental>
     <TargetExt>.lib</TargetExt>
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'">
+    <LinkIncremental>true</LinkIncremental>
+    <TargetExt>.lib</TargetExt>
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
     <LinkIncremental>false</LinkIncremental>
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
@@ -177,12 +249,24 @@
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
     <TargetExt>.lib</TargetExt>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <LinkIncremental>false</LinkIncremental>
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+    <TargetExt>.lib</TargetExt>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|x64'">
     <LinkIncremental>false</LinkIncremental>
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
     <TargetExt>.lib</TargetExt>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">
+    <LinkIncremental>false</LinkIncremental>
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+    <TargetExt>.lib</TargetExt>
+  </PropertyGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
     <ClCompile>
       <PrecompiledHeader>NotUsing</PrecompiledHeader>
@@ -253,6 +337,37 @@
       <LinkLibraryDependencies>true</LinkLibraryDependencies>
     </ProjectReference>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <ClCompile>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <Optimization>Disabled</Optimization>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <SDLCheck>
+      </SDLCheck>
+      <AdditionalIncludeDirectories>..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <StringPooling>true</StringPooling>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <RuntimeLibrary>MultiThreadedDebugDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <AdditionalOptions>/D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+    </ClCompile>
+    <Link>
+      <SubSystem>Console</SubSystem>
+      <GenerateDebugInformation>true</GenerateDebugInformation>
+      <AdditionalDependencies>bddisasm.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalLibraryDirectories>$(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+    </Link>
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+  </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|x64'">
     <ClCompile>
       <PrecompiledHeader>NotUsing</PrecompiledHeader>
@@ -284,6 +399,37 @@
       <LinkLibraryDependencies>true</LinkLibraryDependencies>
     </ProjectReference>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='DebugKernel|ARM64'">
+    <ClCompile>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <WarningLevel>Level4</WarningLevel>
+      <Optimization>Disabled</Optimization>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <SDLCheck>
+      </SDLCheck>
+      <AdditionalIncludeDirectories>..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <StringPooling>true</StringPooling>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <RuntimeLibrary>MultiThreadedDebugDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <BasicRuntimeChecks>Default</BasicRuntimeChecks>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
+      <AdditionalOptions>/kernel /D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+    </ClCompile>
+    <Link>
+      <SubSystem>Console</SubSystem>
+      <GenerateDebugInformation>true</GenerateDebugInformation>
+      <AdditionalDependencies>bddisasm.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalLibraryDirectories>$(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+    </Link>
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+  </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
     <ClCompile>
       <WarningLevel>Level4</WarningLevel>
@@ -363,6 +509,46 @@
       <ExceptionHandling>Sync</ExceptionHandling>
       <MinimalRebuild>true</MinimalRebuild>
       <AdditionalOptions>/D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <CompileAs>Default</CompileAs>
+    </ClCompile>
+    <Link>
+      <SubSystem>Console</SubSystem>
+      <EnableCOMDATFolding>true</EnableCOMDATFolding>
+      <OptimizeReferences>true</OptimizeReferences>
+      <GenerateDebugInformation>true</GenerateDebugInformation>
+      <AdditionalDependencies>bddisasm.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalLibraryDirectories>$(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+    </Link>
+    <Lib />
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+  </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <ClCompile>
+      <WarningLevel>Level4</WarningLevel>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <Optimization>Disabled</Optimization>
+      <FunctionLevelLinking>
+      </FunctionLevelLinking>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <SDLCheck>
+      </SDLCheck>
+      <AdditionalIncludeDirectories>..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <ShowIncludes>false</ShowIncludes>
+      <RuntimeLibrary>MultiThreadedDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <StringPooling>true</StringPooling>
+      <InlineFunctionExpansion>Default</InlineFunctionExpansion>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <ExceptionHandling>Sync</ExceptionHandling>
+      <MinimalRebuild>true</MinimalRebuild>
+      <AdditionalOptions>/D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+      <CompileAs>Default</CompileAs>
     </ClCompile>
     <Link>
       <SubSystem>Console</SubSystem>
@@ -415,6 +601,44 @@
       <LinkLibraryDependencies>true</LinkLibraryDependencies>
     </ProjectReference>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='ReleaseKernel|ARM64'">
+    <ClCompile>
+      <WarningLevel>Level4</WarningLevel>
+      <PrecompiledHeader>NotUsing</PrecompiledHeader>
+      <Optimization>Disabled</Optimization>
+      <FunctionLevelLinking>
+      </FunctionLevelLinking>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+      <SDLCheck>
+      </SDLCheck>
+      <AdditionalIncludeDirectories>..\inc;..\bddisasm\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <TreatWarningAsError>true</TreatWarningAsError>
+      <ShowIncludes>false</ShowIncludes>
+      <RuntimeLibrary>MultiThreadedDLL</RuntimeLibrary>
+      <BufferSecurityCheck>false</BufferSecurityCheck>
+      <StringPooling>true</StringPooling>
+      <InlineFunctionExpansion>Default</InlineFunctionExpansion>
+      <FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
+      <IgnoreStandardIncludePath>false</IgnoreStandardIncludePath>
+      <ProgramDataBaseFileName>$(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb</ProgramDataBaseFileName>
+      <ExceptionHandling>Sync</ExceptionHandling>
+      <MinimalRebuild>true</MinimalRebuild>
+      <AdditionalOptions>/kernel /D "AMD64" %(AdditionalOptions)</AdditionalOptions>
+    </ClCompile>
+    <Link>
+      <SubSystem>Console</SubSystem>
+      <EnableCOMDATFolding>true</EnableCOMDATFolding>
+      <OptimizeReferences>true</OptimizeReferences>
+      <GenerateDebugInformation>true</GenerateDebugInformation>
+      <AdditionalDependencies>bddisasm.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalLibraryDirectories>$(SolutionDir)bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+    </Link>
+    <Lib />
+    <ProjectReference>
+      <LinkLibraryDependencies>true</LinkLibraryDependencies>
+    </ProjectReference>
+  </ItemDefinitionGroup>
   <ItemGroup>
     <ClCompile Include="bdshemu.c" />
   </ItemGroup>
diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py
index 3e784e1..934ef73 100644
--- a/bindings/pybddisasm/setup.py
+++ b/bindings/pybddisasm/setup.py
@@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
 from codecs import open
 
 VERSION = (0, 1, 3)
-LIBRARY_VERSION = (1, 34, 9)
+LIBRARY_VERSION = (1, 34, 10)
 LIBRARY_INSTRUX_SIZE = 856
 
 packages = ['pybddisasm']
diff --git a/inc/bddisasm.h b/inc/bddisasm.h
index e169f63..884274f 100644
--- a/inc/bddisasm.h
+++ b/inc/bddisasm.h
@@ -5,6 +5,7 @@
 #ifndef BDDISASM_H
 #define BDDISASM_H
 
+#include "disasmtypes.h"
 #include "disasmstatus.h"
 #include "registers.h"
 #include "constants.h"
@@ -120,9 +121,9 @@
 #define ND_SIZE_UNKNOWN             0xFFFFFFFF  // Unknown/invalid size.
 
 
-typedef uint32_t ND_OPERAND_SIZE;
+typedef ND_UINT32 ND_OPERAND_SIZE;
 
-typedef uint32_t ND_REG_SIZE;
+typedef ND_UINT32 ND_REG_SIZE;
 
 
 //
@@ -403,15 +404,15 @@ typedef uint32_t ND_REG_SIZE;
 #define ND_SET_SIGN(sz, x)          ND_SIGN_EX(sz, x)
 
 #ifdef BIG_ENDIAN
-#define ND_FETCH_64(b)              ((uint64_t)FETCH_uint32_t((char *)b) | ((uint64_t)FETCH_uint32_t((char *)b + 4) << 32))
-#define ND_FETCH_32(b)              ((uint32_t)FETCH_WORD((char *)b)  | ((uint32_t)FETCH_WORD((char *)b + 2)  << 16))
+#define ND_FETCH_64(b)              ((ND_UINT64)ND_FETCH_32((char *)b) | ((ND_UINT64)ND_FETCH_32((char *)b + 4) << 32))
+#define ND_FETCH_32(b)              ((ND_UINT32)ND_FETCH_16((char *)b) | ((ND_UINT32)ND_FETCH_16((char *)b + 2) << 16))
 #define ND_FETCH_16(b)              ((((char *)b)[0]) | (((char *)b)[1] << 8))
 #define ND_FETCH_8(b)               (*((char *)b))
 #else
-#define ND_FETCH_64(b)              (*((uint64_t *)(b)))
-#define ND_FETCH_32(b)              (*((uint32_t *)(b)))
-#define ND_FETCH_16(b)              (*((uint16_t *)(b)))
-#define ND_FETCH_8(b)               (*((uint8_t *)(b)))
+#define ND_FETCH_64(b)              (*((ND_UINT64 *)(b)))
+#define ND_FETCH_32(b)              (*((ND_UINT32 *)(b)))
+#define ND_FETCH_16(b)              (*((ND_UINT16 *)(b)))
+#define ND_FETCH_8(b)               (*((ND_UINT8 *)(b)))
 #endif
 
 
@@ -463,31 +464,31 @@ typedef uint32_t ND_REG_SIZE;
 //  - bits [29, 9] (21 bits)    - reserved
 //  - bit 8                     - High8 indicator: indicates whether the reg is AH/CH/DH/BH
 //  - bits [7, 0] (8 bits)      - the register ID
-#define ND_OP_REG_ID(op)            (((uint64_t)((op)->Type & 0xF) << 60) |                                 \
-                                     ((uint64_t)((op)->Info.Register.Type & 0xFF) << 52) |                  \
-                                     ((uint64_t)((op)->Info.Register.Size & 0xFFFF) << 36) |                \
-                                     ((uint64_t)((op)->Info.Register.Count & 0x3F) << 30) |                 \
-                                     ((uint64_t)((op)->Info.Register.IsHigh8 & 0x1) << 8) |                 \
-                                     ((uint64_t)((op)->Info.Register.Reg)))
+#define ND_OP_REG_ID(op)            (((ND_UINT64)((op)->Type & 0xF) << 60) |                                 \
+                                     ((ND_UINT64)((op)->Info.Register.Type & 0xFF) << 52) |                  \
+                                     ((ND_UINT64)((op)->Info.Register.Size & 0xFFFF) << 36) |                \
+                                     ((ND_UINT64)((op)->Info.Register.Count & 0x3F) << 30) |                 \
+                                     ((ND_UINT64)((op)->Info.Register.IsHigh8 & 0x1) << 8) |                 \
+                                     ((ND_UINT64)((op)->Info.Register.Reg)))
 
 // Example: ND_IS_OP_REG(op, ND_REG_GPR, 4, REG_ESP)
 // Example: ND_IS_OP_REG(op, ND_REG_CR,  8, REG_CR3)
 // Example: ND_IS_OP_REG(op, ND_REG_RIP, 8, 0)
 
 // Checks if the indicated operand op is a register of type t, with size s and index r.
-#define ND_IS_OP_REG(op, t, s, r)   (ND_OP_REG_ID(op) == (((uint64_t)(ND_OP_REG) << 60) |                   \
-                                                          ((uint64_t)((t) & 0xFF) << 52) |                  \
-                                                          ((uint64_t)((s) & 0xFFFF) << 36) |                \
-                                                          ((uint64_t)(1) << 30) |                           \
-                                                          ((uint64_t)(r))))
+#define ND_IS_OP_REG(op, t, s, r)   (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) |                   \
+                                                          ((ND_UINT64)((t) & 0xFF) << 52) |                  \
+                                                          ((ND_UINT64)((s) & 0xFFFF) << 36) |                \
+                                                          ((ND_UINT64)(1) << 30) |                           \
+                                                          ((ND_UINT64)(r))))
 
 // Checks if the indicated operand op is a register of type t, with size s and index r.
-#define ND_IS_OP_REG_EX(op, t, s, r, b, h)   (ND_OP_REG_ID(op) == (((uint64_t)(ND_OP_REG) << 60) |          \
-                                                          ((uint64_t)((t) & 0xFF) << 52) |                  \
-                                                          ((uint64_t)((s) & 0xFFFF) << 36) |                \
-                                                          ((uint64_t)((b) & 0x3F) << 30) |                  \
-                                                          ((uint64_t)((h) & 0x1) << 8) |                    \
-                                                          ((uint64_t)(r))))
+#define ND_IS_OP_REG_EX(op, t, s, r, b, h)   (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) |          \
+                                                          ((ND_UINT64)((t) & 0xFF) << 52) |                  \
+                                                          ((ND_UINT64)((s) & 0xFFFF) << 36) |                \
+                                                          ((ND_UINT64)((b) & 0x3F) << 30) |                  \
+                                                          ((ND_UINT64)((h) & 0x1) << 8) |                    \
+                                                          ((ND_UINT64)(r))))
 
 // Checjs if the indicated operand is the stack.
 #define ND_IS_OP_STACK(op)          ((op)->Type == ND_OP_MEM && (op)->Info.Memory.IsStack)
@@ -697,14 +698,14 @@ typedef enum _ND_EX_TYPE_AMX
 //
 typedef union _ND_OPERAND_ACCESS
 {
-    uint8_t             Access;
+    ND_UINT8        Access;
     struct
     {
-        uint8_t         Read : 1;       // The operand is read.
-        uint8_t         Write : 1;      // The operand is written.
-        uint8_t         CondRead : 1;   // The operand is read only under some conditions.
-        uint8_t         CondWrite : 1;  // The operand is written only under some conditions.
-        uint8_t         Prefetch : 1;   // The operand is prefetched.
+        ND_UINT8    Read : 1;       // The operand is read.
+        ND_UINT8    Write : 1;      // The operand is written.
+        ND_UINT8    CondRead : 1;   // The operand is read only under some conditions.
+        ND_UINT8    CondWrite : 1;  // The operand is written only under some conditions.
+        ND_UINT8    Prefetch : 1;   // The operand is prefetched.
     };
 } ND_OPERAND_ACCESS;
 
@@ -714,12 +715,12 @@ typedef union _ND_OPERAND_ACCESS
 //
 typedef union _ND_OPERAND_FLAGS
 {
-    uint8_t             Flags;
+    ND_UINT8        Flags;
     struct
     {
-        uint8_t         IsDefault : 1;        // 1 if the operand is default. This also applies to implicit ops.
-        uint8_t         SignExtendedOp1 : 1;  // 1 if the operand is sign extended to the first operands' size.
-        uint8_t         SignExtendedDws : 1;  // 1 if the operand is sign extended to the default word size.
+        ND_UINT8    IsDefault : 1;        // 1 if the operand is default. This also applies to implicit ops.
+        ND_UINT8    SignExtendedOp1 : 1;  // 1 if the operand is sign extended to the first operands' size.
+        ND_UINT8    SignExtendedDws : 1;  // 1 if the operand is sign extended to the default word size.
     };
 } ND_OPERAND_FLAGS;
 
@@ -729,7 +730,7 @@ typedef union _ND_OPERAND_FLAGS
 //
 typedef struct _ND_OPDESC_CONSTANT
 {
-    uint64_t           Const;   // Instruction constant, ie ROL reg, 1.
+    ND_UINT64       Const;   // Instruction constant, ie ROL reg, 1.
 } ND_OPDESC_CONSTANT;
 
 
@@ -738,7 +739,7 @@ typedef struct _ND_OPDESC_CONSTANT
 //
 typedef struct _ND_OPDESC_IMMEDIATE
 {
-    uint64_t           Imm;     // Immediate. Only Size bytes are valid. The rest are undefined.
+    ND_UINT64       Imm;     // Immediate. Only Size bytes are valid. The rest are undefined.
 } ND_OPDESC_IMMEDIATE;
 
 
@@ -747,7 +748,7 @@ typedef struct _ND_OPDESC_IMMEDIATE
 //
 typedef struct _ND_OPDESC_REL_OFFSET
 {
-    uint64_t           Rel;     // Relative offset (relative to the current RIP). Sign extended.
+    ND_UINT64       Rel;     // Relative offset (relative to the current RIP). Sign extended.
 } ND_OPDESC_RELOFFSET;
 
 
@@ -761,11 +762,11 @@ typedef struct _ND_OPDESC_REGISTER
                                 // field, as a smaller amount of data may be processed from a
                                 // register (especially if we have a SSE register or a mask register).
                                 // Also note that as of now, 64 bytes is the maximum register size.
-    uint32_t        Reg;        // The register number/ID.
-    uint32_t        Count;      // The number of registers accessed, starting with Reg.
+    ND_UINT32       Reg;        // The register number/ID.
+    ND_UINT32       Count;      // The number of registers accessed, starting with Reg.
 
-    bool            IsHigh8:1;  // TRUE if this is AH, CH, DH or BH register.
-    bool            IsBlock:1;  // TRUE if this is a block register addressing.
+    ND_BOOL         IsHigh8:1;  // TRUE if this is AH, CH, DH or BH register.
+    ND_BOOL         IsBlock:1;  // TRUE if this is a block register addressing.
 } ND_OPDESC_REGISTER;
 
 
@@ -775,8 +776,8 @@ typedef struct _ND_OPDESC_REGISTER
 typedef struct _ND_OPDESC_ADDRESS
 {
     // Size is the size of the address. Usually 4 (16 bit mode) or 6 (32 bit mode) or 10 (64 bit).
-    uint16_t    BaseSeg;        // Base segment selector of the address.
-    uint64_t    Offset;         // Offset inside the segment.
+    ND_UINT16       BaseSeg;    // Base segment selector of the address.
+    ND_UINT64       Offset;     // Offset inside the segment.
 } ND_OPDESC_ADDRESS;
 
 
@@ -798,49 +799,49 @@ typedef enum _ND_SHSTK_ACCESS
 //
 typedef struct _ND_OPDESC_MEMORY
 {
-    bool            HasSeg:1;           // TRUE if segment is present & used.
-    bool            HasBase:1;          // TRUE if base register is present.
-    bool            HasIndex:1;         // TRUE if index & scale are present.
-    bool            HasDisp:1;          // TRUE if displacement is present.
-    bool            HasCompDisp:1;      // TRUE if compressed disp8 is used (EVEX instructions).
-    bool            HasBroadcast:1;     // TRUE if the memory operand is a broadcast operand.
-
-    bool            IsRipRel:1;         // TRUE if this is a rip-relative addressing. Base, Index, Scale are
+    ND_BOOL         HasSeg:1;           // TRUE if segment is present & used.
+    ND_BOOL         HasBase:1;          // TRUE if base register is present.
+    ND_BOOL         HasIndex:1;         // TRUE if index & scale are present.
+    ND_BOOL         HasDisp:1;          // TRUE if displacement is present.
+    ND_BOOL         HasCompDisp:1;      // TRUE if compressed disp8 is used (EVEX instructions).
+    ND_BOOL         HasBroadcast:1;     // TRUE if the memory operand is a broadcast operand.
+
+    ND_BOOL         IsRipRel:1;         // TRUE if this is a rip-relative addressing. Base, Index, Scale are
                                         // all ignored.
-    bool            IsStack:1;          // TRUE if this is a stack op. Note that explicit stack accesses are not
+    ND_BOOL         IsStack:1;          // TRUE if this is a stack op. Note that explicit stack accesses are not
                                         // included (eg: mov eax, [rsp] will NOT set IsStack).
-    bool            IsString:1;         // TRUE for [RSI] and [RDI] operands inside string operations.
-    bool            IsShadowStack:1;    // TRUE if this is a shadow stack access. Check out ShStkType for more info.
-    bool            IsDirect:1;         // TRUE if direct addressing (MOV [...], EAX, 0xA3).
-    bool            IsBitbase:1;        // TRUE if this is a bit base. Used for BT* instructions. The bitbase
+    ND_BOOL         IsString:1;         // TRUE for [RSI] and [RDI] operands inside string operations.
+    ND_BOOL         IsShadowStack:1;    // TRUE if this is a shadow stack access. Check out ShStkType for more info.
+    ND_BOOL         IsDirect:1;         // TRUE if direct addressing (MOV [...], EAX, 0xA3).
+    ND_BOOL         IsBitbase:1;        // TRUE if this is a bit base. Used for BT* instructions. The bitbase
                                         // stored in the second operand must be added to the linear address.
-    bool            IsAG:1;             // TRUE if the memory operand is address generation and no mem access is
+    ND_BOOL         IsAG:1;             // TRUE if the memory operand is address generation and no mem access is
                                         // made.
-    bool            IsMib:1;            // TRUE if MIB addressing is used (MPX instructions).
-    bool            IsVsib:1;           // TRUE if the index register selects a vector register.
-    bool            IsSibMem:1;         // TRUE if the addressing uses sibmem (AMX instructions).
+    ND_BOOL         IsMib:1;            // TRUE if MIB addressing is used (MPX instructions).
+    ND_BOOL         IsVsib:1;           // TRUE if the index register selects a vector register.
+    ND_BOOL         IsSibMem:1;         // TRUE if the addressing uses sibmem (AMX instructions).
 
 
     ND_REG_SIZE     BaseSize;           // Base size, in bytes. Max 8 bytes.
     ND_REG_SIZE     IndexSize;          // Ditto for index size. Max 8 bytes.
-    uint8_t         DispSize;           // Displacement size. Max 4 bytes.
-    uint8_t         CompDispSize;       // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64.
+    ND_UINT8        DispSize;           // Displacement size. Max 4 bytes.
+    ND_UINT8        CompDispSize;       // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64.
 
-    uint8_t         ShStkType;          // Shadow stack access type. Check out ND_SHSTK_ACCESS.
+    ND_UINT8        ShStkType;          // Shadow stack access type. Check out ND_SHSTK_ACCESS.
 
     struct
     {
-        uint8_t     IndexSize;          // VSIB index size.
-        uint8_t     ElemSize;           // VSIB element size.
-        uint8_t     ElemCount;          // Number of elements scattered/gathered/prefetched.
+        ND_UINT8    IndexSize;          // VSIB index size.
+        ND_UINT8    ElemSize;           // VSIB element size.
+        ND_UINT8    ElemCount;          // Number of elements scattered/gathered/prefetched.
     } Vsib;
 
-    uint8_t         Seg;                // Base segment used to address the memory. 0 = es, 1 = cs, etc.
-    uint8_t         Base;               // Base register. Can only be a GPR.
-    uint8_t         Index;              // Index register. Can be a vector reg (ZMM0-ZMM31).
-    uint8_t         Scale;              // Scale: 1, 2, 4 or 8. Always present if Index is present.
+    ND_UINT8        Seg;                // Base segment used to address the memory. 0 = es, 1 = cs, etc.
+    ND_UINT8        Base;               // Base register. Can only be a GPR.
+    ND_UINT8        Index;              // Index register. Can be a vector reg (ZMM0-ZMM31).
+    ND_UINT8        Scale;              // Scale: 1, 2, 4 or 8. Always present if Index is present.
 
-    uint64_t        Disp;               // Sign extended displacement.
+    ND_UINT64       Disp;               // Sign extended displacement.
 
 } ND_OPDESC_MEMORY;
 
@@ -850,26 +851,26 @@ typedef struct _ND_OPDESC_MEMORY
 //
 typedef struct _ND_OPERAND_DECORATOR
 {
-    bool                HasMask:1;      // TRUE if mask is present, 0 otherwise.
-    bool                HasZero:1;      // TRUE if zeroing will be made, 0 if merging will be made.
-    bool                HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands.
+    ND_BOOL         HasMask:1;      // TRUE if mask is present, 0 otherwise.
+    ND_BOOL         HasZero:1;      // TRUE if zeroing will be made, 0 if merging will be made.
+    ND_BOOL         HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands.
 
     // These are used only to indicate where the SAE and ER decorators should be placed in the disassembly.
     // Otherwise, SAE and ER are global, per instruction, and don't apply to a single operand.
-    bool                HasSae:1;       // TRUE if SAE is present.
-    bool                HasEr:1;        // TRUE if ER is present. 
+    ND_BOOL         HasSae:1;       // TRUE if SAE is present.
+    ND_BOOL         HasEr:1;        // TRUE if ER is present. 
 
     // Mask register specifier.
     struct
     {
-        uint8_t         Msk;            // Mask register used. Only k0-k7 can be encoded.
+        ND_UINT8    Msk;            // Mask register used. Only k0-k7 can be encoded.
     } Mask;
 
     // Broadcast specifier
     struct
     {
-        uint8_t         Count;          // Number of times to broadcast the element.
-        uint8_t         Size;           // Size of one element.
+        ND_UINT8    Count;          // Number of times to broadcast the element.
+        ND_UINT8    Size;           // Size of one element.
     } Broadcast;
 
 } ND_OPERAND_DECORATOR;
@@ -918,13 +919,13 @@ typedef struct _ND_OPERAND
 //
 typedef union _ND_REX
 {
-    uint8_t         Rex;
+    ND_UINT8        Rex;
     struct
     {
-        uint8_t     b : 1;      // b (rm or low opcode) extension field.
-        uint8_t     x : 1;      // x (index) extension field.
-        uint8_t     r : 1;      // r (reg) extension field.
-        uint8_t     w : 1;      // w (size) extension field. Promotes to 64 bit.
+        ND_UINT8    b : 1;      // b (rm or low opcode) extension field.
+        ND_UINT8    x : 1;      // x (index) extension field.
+        ND_UINT8    r : 1;      // r (reg) extension field.
+        ND_UINT8    w : 1;      // w (size) extension field. Promotes to 64 bit.
     };
 } ND_REX;
 
@@ -934,12 +935,12 @@ typedef union _ND_REX
 //
 typedef union _ND_MODRM
 {
-    uint8_t         ModRm;
+    ND_UINT8        ModRm;
     struct
     {
-        uint8_t     rm : 3;     // rm field.
-        uint8_t     reg : 3;    // reg field.
-        uint8_t     mod : 2;    // mod field. Indicates memory access (0, 1 or 2), or register access (3).
+        ND_UINT8    rm : 3;     // rm field.
+        ND_UINT8    reg : 3;    // reg field.
+        ND_UINT8    mod : 2;    // mod field. Indicates memory access (0, 1 or 2), or register access (3).
     };
 } ND_MODRM;
 
@@ -949,12 +950,12 @@ typedef union _ND_MODRM
 //
 typedef union _ND_SIB
 {
-    uint8_t         Sib;
+    ND_UINT8        Sib;
     struct
     {
-        uint8_t     base : 3;   // Base register.
-        uint8_t     index : 3;  // Index register.
-        uint8_t     scale : 2;  // Scale.
+        ND_UINT8    base : 3;   // Base register.
+        ND_UINT8    index : 3;  // Index register.
+        ND_UINT8    scale : 2;  // Scale.
     };
 } ND_SIB;
 
@@ -964,15 +965,15 @@ typedef union _ND_SIB
 //
 typedef union _ND_DREX
 {
-    uint8_t         Drex;
+    ND_UINT8        Drex;
     struct
     {
-        uint8_t     b : 1;
-        uint8_t     x : 1;
-        uint8_t     r : 1;
-        uint8_t     oc0 : 1;
-        uint8_t     vd : 3;
-        uint8_t     d : 1;
+        ND_UINT8    b : 1;
+        ND_UINT8    x : 1;
+        ND_UINT8    r : 1;
+        ND_UINT8    oc0 : 1;
+        ND_UINT8    vd : 3;
+        ND_UINT8    d : 1;
     };
 } ND_DREX;
 
@@ -982,15 +983,15 @@ typedef union _ND_DREX
 //
 typedef union _ND_VEX2
 {
-    uint8_t        Vex[2];
+    ND_UINT8        Vex[2];
     struct
     {
-        uint8_t    op;          // 0xC5
+        ND_UINT8    op;          // 0xC5
 
-        uint8_t    p : 2;       // p0, p1
-        uint8_t    l : 1;       // L
-        uint8_t    v : 4;       // ~v0, ~v1, ~v2, ~v3
-        uint8_t    r : 1;       // ~R
+        ND_UINT8    p : 2;       // p0, p1
+        ND_UINT8    l : 1;       // L
+        ND_UINT8    v : 4;       // ~v0, ~v1, ~v2, ~v3
+        ND_UINT8    r : 1;       // ~R
     };
 } ND_VEX2;
 
@@ -1000,20 +1001,20 @@ typedef union _ND_VEX2
 //
 typedef union _ND_VEX3
 {
-    uint8_t         Vex[3];
+    ND_UINT8        Vex[3];
     struct
     {
-        uint8_t     op;         // 0xC4
+        ND_UINT8    op;         // 0xC4
 
-        uint8_t     m : 5;      // m0, m1, m2, m3, m4
-        uint8_t     b : 1;      // ~B
-        uint8_t     x : 1;      // ~X
-        uint8_t     r : 1;      // ~R
+        ND_UINT8    m : 5;      // m0, m1, m2, m3, m4
+        ND_UINT8    b : 1;      // ~B
+        ND_UINT8    x : 1;      // ~X
+        ND_UINT8    r : 1;      // ~R
 
-        uint8_t     p : 2;      // p0, p1
-        uint8_t     l : 1;      // L
-        uint8_t     v : 4;      // ~v0, ~v1, ~v2, ~v3
-        uint8_t     w : 1;      // W
+        ND_UINT8    p : 2;      // p0, p1
+        ND_UINT8    l : 1;      // L
+        ND_UINT8    v : 4;      // ~v0, ~v1, ~v2, ~v3
+        ND_UINT8    w : 1;      // W
     };
 } ND_VEX3;
 
@@ -1023,20 +1024,20 @@ typedef union _ND_VEX3
 //
 typedef union _ND_XOP
 {
-    uint8_t         Xop[3];
+    ND_UINT8        Xop[3];
     struct
     {
-        uint8_t     op;         // 0x8F
+        ND_UINT8    op;         // 0x8F
 
-        uint8_t     m : 5;      // m0, m1, m2, m3, m4
-        uint8_t     b : 1;      // ~B
-        uint8_t     x : 1;      // ~X
-        uint8_t     r : 1;      // ~R
+        ND_UINT8    m : 5;      // m0, m1, m2, m3, m4
+        ND_UINT8    b : 1;      // ~B
+        ND_UINT8    x : 1;      // ~X
+        ND_UINT8    r : 1;      // ~R
 
-        uint8_t     p : 2;      // p0, p1
-        uint8_t     l : 1;      // L
-        uint8_t     v : 4;      // ~v0, ~v1, ~v2, ~v3
-        uint8_t     w : 1;      // W
+        ND_UINT8    p : 2;      // p0, p1
+        ND_UINT8    l : 1;      // L
+        ND_UINT8    v : 4;      // ~v0, ~v1, ~v2, ~v3
+        ND_UINT8    w : 1;      // W
     };
 } ND_XOP;
 
@@ -1046,28 +1047,28 @@ typedef union _ND_XOP
 //
 typedef union _ND_EVEX
 {
-    uint8_t         Evex[4];
+    ND_UINT8        Evex[4];
     struct
     {
-        uint8_t     op;         // 0x62
-
-        uint8_t     m : 3;      // m0, m1, m2. Indicates opcode map.
-        uint8_t     zero : 1;   // 0, must be 0.
-        uint8_t     rp : 1;     // ~R'
-        uint8_t     b : 1;      // ~B
-        uint8_t     x : 1;      // ~X
-        uint8_t     r : 1;      // ~R
-
-        uint8_t     p : 2;      // p0, p1
-        uint8_t     one : 1;    // 1
-        uint8_t     v : 4;      // ~v0, ~v1, ~v2, ~v3
-        uint8_t     w : 1;      // W
-
-        uint8_t     a : 3;      // a0, a1, a2
-        uint8_t     vp : 1;     // ~V'
-        uint8_t     bm : 1;     // b
-        uint8_t     l : 2;      // L'L
-        uint8_t     z : 1;      // z
+        ND_UINT8    op;         // 0x62
+
+        ND_UINT8    m : 3;      // m0, m1, m2. Indicates opcode map.
+        ND_UINT8    zero : 1;   // 0, must be 0.
+        ND_UINT8    rp : 1;     // ~R'
+        ND_UINT8    b : 1;      // ~B
+        ND_UINT8    x : 1;      // ~X
+        ND_UINT8    r : 1;      // ~R
+
+        ND_UINT8    p : 2;      // p0, p1
+        ND_UINT8    one : 1;    // 1
+        ND_UINT8    v : 4;      // ~v0, ~v1, ~v2, ~v3
+        ND_UINT8    w : 1;      // W
+
+        ND_UINT8    a : 3;      // a0, a1, a2
+        ND_UINT8    vp : 1;     // ~V'
+        ND_UINT8    bm : 1;     // b
+        ND_UINT8    l : 2;      // L'L
+        ND_UINT8    z : 1;      // z
     };
 } ND_EVEX;
 
@@ -1079,13 +1080,13 @@ typedef union _ND_EVEX
 //
 typedef union _ND_CPUID_FLAG
 {
-    uint64_t       Flag;
+    ND_UINT64       Flag;
     struct
     {
-        uint32_t   Leaf;          // CPUID leaf. ND_CFF_NO_LEAF if not applicable.
-        uint32_t   SubLeaf : 24;  // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable.
-        uint32_t   Reg : 3;       // The register that contains info regarding the instruction.
-        uint32_t   Bit : 5;       // Bit inside the register that indicates whether the instruction is present.
+        ND_UINT32   Leaf;          // CPUID leaf. ND_CFF_NO_LEAF if not applicable.
+        ND_UINT32   SubLeaf : 24;  // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable.
+        ND_UINT32   Reg : 3;       // The register that contains info regarding the instruction.
+        ND_UINT32   Bit : 5;       // Bit inside the register that indicates whether the instruction is present.
     };
 } ND_CPUID_FLAG;
 
@@ -1096,19 +1097,19 @@ typedef union _ND_CPUID_FLAG
 //
 typedef union _ND_VALID_PREFIXES
 {
-    uint16_t     Raw;
+    ND_UINT16       Raw;
     struct
     {
-        uint16_t Rep : 1;        // The instruction supports REP prefix.
-        uint16_t RepCond : 1;    // The instruction supports REPZ/REPNZ prefixes.
-        uint16_t Lock : 1;       // The instruction supports LOCK prefix.
-        uint16_t Hle : 1;        // The instruction supports XACQUIRE/XRELEASE prefixes.
-        uint16_t Xacquire : 1;   // The instruction supports only XACQUIRE.
-        uint16_t Xrelease : 1;   // The instruction supports only XRELEASE.
-        uint16_t Bnd : 1;        // The instruction supports BND prefix.
-        uint16_t Bhint : 1;      // The instruction supports branch hints.
-        uint16_t HleNoLock : 1;  // HLE prefix is accepted without LOCK.
-        uint16_t Dnt : 1;        // The instruction supports the DNT (Do Not Track) CET prefix.
+        ND_UINT16   Rep : 1;        // The instruction supports REP prefix.
+        ND_UINT16   RepCond : 1;    // The instruction supports REPZ/REPNZ prefixes.
+        ND_UINT16   Lock : 1;       // The instruction supports LOCK prefix.
+        ND_UINT16   Hle : 1;        // The instruction supports XACQUIRE/XRELEASE prefixes.
+        ND_UINT16   Xacquire : 1;   // The instruction supports only XACQUIRE.
+        ND_UINT16   Xrelease : 1;   // The instruction supports only XRELEASE.
+        ND_UINT16   Bnd : 1;        // The instruction supports BND prefix.
+        ND_UINT16   Bhint : 1;      // The instruction supports branch hints.
+        ND_UINT16   HleNoLock : 1;  // HLE prefix is accepted without LOCK.
+        ND_UINT16   Dnt : 1;        // The instruction supports the DNT (Do Not Track) CET prefix.
     };
 } ND_VALID_PREFIXES, *PND_VALID_PREFIXES;
 
@@ -1119,14 +1120,14 @@ typedef union _ND_VALID_PREFIXES
 //
 typedef union _ND_VALID_DECORATORS
 {
-    uint8_t     Raw;
+    ND_UINT8        Raw;
     struct
     {
-        uint8_t Er : 1;         // The instruction supports embedded rounding mode.
-        uint8_t Sae : 1;        // The instruction supports suppress all exceptions mode.
-        uint8_t Zero : 1;       // The instruction supports zeroing.
-        uint8_t Mask : 1;       // The instruction supports mask registers.
-        uint8_t Broadcast : 1;  // The instruction supports broadcast.
+        ND_UINT8    Er : 1;         // The instruction supports embedded rounding mode.
+        ND_UINT8    Sae : 1;        // The instruction supports suppress all exceptions mode.
+        ND_UINT8    Zero : 1;       // The instruction supports zeroing.
+        ND_UINT8    Mask : 1;       // The instruction supports mask registers.
+        ND_UINT8    Broadcast : 1;  // The instruction supports broadcast.
     };
 } ND_VALID_DECORATORS, *PND_VALID_DECORATORS;
 
@@ -1137,38 +1138,38 @@ typedef union _ND_VALID_DECORATORS
 //
 typedef union _ND_VALID_MODES
 {
-    uint32_t     Raw;
+    ND_UINT32       Raw;
     struct
     {
         // Group 1: privilege level.
-        uint32_t Ring0 : 1;     // The instruction is valid in ring 0.
-        uint32_t Ring1 : 1;     // The instruction is valid in ring 1.
-        uint32_t Ring2 : 1;     // The instruction is valid in ring 2.
-        uint32_t Ring3 : 1;     // The instruction is valid in ring 3.
+        ND_UINT32   Ring0 : 1;     // The instruction is valid in ring 0.
+        ND_UINT32   Ring1 : 1;     // The instruction is valid in ring 1.
+        ND_UINT32   Ring2 : 1;     // The instruction is valid in ring 2.
+        ND_UINT32   Ring3 : 1;     // The instruction is valid in ring 3.
 
         // Group 2: operating mode - the CPU can be on only one of these modes at any moment.
-        uint32_t Real : 1;      // The instruction is valid in real mode.
-        uint32_t V8086 : 1;     // The instruction is valid in Virtual 8086 mode.
-        uint32_t Protected : 1; // The instruction is valid in protected mode (32 bit).
-        uint32_t Compat : 1;    // The instruction is valid in compatibility mode (32 bit in 64 bit).
-        uint32_t Long : 1;      // The instruction is valid in long mode.
+        ND_UINT32   Real : 1;      // The instruction is valid in real mode.
+        ND_UINT32   V8086 : 1;     // The instruction is valid in Virtual 8086 mode.
+        ND_UINT32   Protected : 1; // The instruction is valid in protected mode (32 bit).
+        ND_UINT32   Compat : 1;    // The instruction is valid in compatibility mode (32 bit in 64 bit).
+        ND_UINT32   Long : 1;      // The instruction is valid in long mode.
 
-        uint32_t Reserved : 3;  // Reserved for padding/future use.
+        ND_UINT32   Reserved : 3;  // Reserved for padding/future use.
 
         // Group 3: special modes - these may be active inside other modes (example: TSX in Long mode).
-        uint32_t Smm : 1;       // The instruction is valid in System Management Mode.
-        uint32_t SmmOff : 1;    // The instruction is valid outside SMM.
-        uint32_t Sgx : 1;       // The instruction is valid in SGX mode.
-        uint32_t SgxOff : 1;    // The instruction is valid outside SGX.
-        uint32_t Tsx : 1;       // The instruction is valid in transactional regions.
-        uint32_t TsxOff : 1;    // The instruction is valid outside TSX.
+        ND_UINT32   Smm : 1;       // The instruction is valid in System Management Mode.
+        ND_UINT32   SmmOff : 1;    // The instruction is valid outside SMM.
+        ND_UINT32   Sgx : 1;       // The instruction is valid in SGX mode.
+        ND_UINT32   SgxOff : 1;    // The instruction is valid outside SGX.
+        ND_UINT32   Tsx : 1;       // The instruction is valid in transactional regions.
+        ND_UINT32   TsxOff : 1;    // The instruction is valid outside TSX.
 
         // Group 4: VMX mode - they engulf all the other modes.
-        uint32_t VmxRoot : 1;   // The instruction is valid in VMX root mode.
-        uint32_t VmxNonRoot : 1;// The instruction is valid in VMX non root mode.
-        uint32_t VmxRootSeam : 1;   // The instruction is valid in VMX root SEAM.
-        uint32_t VmxNonRootSeam : 1;// The instruction is valid in VMX non-root SEAM.
-        uint32_t VmxOff : 1;    // The instruction is valid outside VMX operation.
+        ND_UINT32   VmxRoot : 1;   // The instruction is valid in VMX root mode.
+        ND_UINT32   VmxNonRoot : 1;// The instruction is valid in VMX non root mode.
+        ND_UINT32   VmxRootSeam : 1;   // The instruction is valid in VMX root SEAM.
+        ND_UINT32   VmxNonRootSeam : 1;// The instruction is valid in VMX non-root SEAM.
+        ND_UINT32   VmxOff : 1;    // The instruction is valid outside VMX operation.
         
     };
 } ND_VALID_MODES, *PND_VALID_MODES;
@@ -1180,30 +1181,30 @@ typedef union _ND_VALID_MODES
 //
 typedef union _ND_RFLAGS
 {
-    uint32_t        Raw;
+    ND_UINT32       Raw;
     struct
     {
-        uint32_t    CF : 1;         // Carry flag.
-        uint32_t    Reserved1 : 1;  // Reserved, must be 1.
-        uint32_t    PF : 1;         // Parity flag.
-        uint32_t    Reserved2 : 1;  // Reserved.
-        uint32_t    AF : 1;         // Auxiliary flag.
-        uint32_t    Reserved3 : 1;  // Reserved.
-        uint32_t    ZF : 1;         // Zero flag.
-        uint32_t    SF : 1;         // Sign flag.
-        uint32_t    TF : 1;         // Trap flag.
-        uint32_t    IF : 1;         // Interrupt flag.
-        uint32_t    DF : 1;         // Direction flag.
-        uint32_t    OF : 1;         // Overflow flag.
-        uint32_t    IOPL : 2;       // I/O privilege level flag.
-        uint32_t    NT : 1;         // Nested task flag.
-        uint32_t    Reserved4 : 1;  // Reserved.
-        uint32_t    RF : 1;         // Resume flag.
-        uint32_t    VM : 1;         // Virtual mode flag.
-        uint32_t    AC : 1;         // Alignment check flag.
-        uint32_t    VIF : 1;        // Virtual interrupts flag.
-        uint32_t    VIP : 1;        // Virtual interrupt pending flag.
-        uint32_t    ID : 1;         // CPUID identification flag.
+        ND_UINT32   CF : 1;         // Carry flag.
+        ND_UINT32   Reserved1 : 1;  // Reserved, must be 1.
+        ND_UINT32   PF : 1;         // Parity flag.
+        ND_UINT32   Reserved2 : 1;  // Reserved.
+        ND_UINT32   AF : 1;         // Auxiliary flag.
+        ND_UINT32   Reserved3 : 1;  // Reserved.
+        ND_UINT32   ZF : 1;         // Zero flag.
+        ND_UINT32   SF : 1;         // Sign flag.
+        ND_UINT32   TF : 1;         // Trap flag.
+        ND_UINT32   IF : 1;         // Interrupt flag.
+        ND_UINT32   DF : 1;         // Direction flag.
+        ND_UINT32   OF : 1;         // Overflow flag.
+        ND_UINT32   IOPL : 2;       // I/O privilege level flag.
+        ND_UINT32   NT : 1;         // Nested task flag.
+        ND_UINT32   Reserved4 : 1;  // Reserved.
+        ND_UINT32   RF : 1;         // Resume flag.
+        ND_UINT32   VM : 1;         // Virtual mode flag.
+        ND_UINT32   AC : 1;         // Alignment check flag.
+        ND_UINT32   VIF : 1;        // Virtual interrupts flag.
+        ND_UINT32   VIP : 1;        // Virtual interrupt pending flag.
+        ND_UINT32   ID : 1;         // CPUID identification flag.
     };
 } ND_RFLAGS, *PND_RFLAGS;
 
@@ -1218,10 +1219,10 @@ typedef union _ND_RFLAGS
 //
 typedef struct _ND_FPU_FLAGS
 {
-    uint8_t         C0 : 2;     // C0 flag access mode. See ND_FPU_FLAG_*.
-    uint8_t         C1 : 2;     // C1 flag access mode. See ND_FPU_FLAG_*.
-    uint8_t         C2 : 2;     // C2 flag access mode. See ND_FPU_FLAG_*.
-    uint8_t         C3 : 2;     // C3 flag access mode. See ND_FPU_FLAG_*.
+    ND_UINT8        C0 : 2;     // C0 flag access mode. See ND_FPU_FLAG_*.
+    ND_UINT8        C1 : 2;     // C1 flag access mode. See ND_FPU_FLAG_*.
+    ND_UINT8        C2 : 2;     // C2 flag access mode. See ND_FPU_FLAG_*.
+    ND_UINT8        C3 : 2;     // C3 flag access mode. See ND_FPU_FLAG_*.
 } ND_FPU_FLAGS, *PND_FPU_FLAGS;
 
 
@@ -1230,10 +1231,10 @@ typedef struct _ND_FPU_FLAGS
 //
 typedef struct _ND_BRANCH_INFO
 {
-    uint8_t         IsBranch : 1;
-    uint8_t         IsConditional : 1;
-    uint8_t         IsIndirect : 1;
-    uint8_t         IsFar : 1;
+    ND_UINT8        IsBranch : 1;
+    ND_UINT8        IsConditional : 1;
+    ND_UINT8        IsIndirect : 1;
+    ND_UINT8        IsFar : 1;
 } ND_BRANCH_INFO;
 
 
@@ -1243,101 +1244,101 @@ typedef struct _ND_BRANCH_INFO
 //
 typedef struct _INSTRUX
 {
-    uint8_t             DefCode:4;                  // ND_CODE_*. Indicates disassembly mode.
-    uint8_t             DefData:4;                  // ND_DATA_*. Indicates default data size.
-    uint8_t             DefStack:4;                 // ND_STACK_*. Indicates default stack pointer width.
-    uint8_t             VendMode:4;                 // ND_VEND_*. Indicates vendor mode.
-    uint8_t             FeatMode;                   // ND_FEAT_*. Indicates which features are enabled.
-    uint8_t             EncMode:4;                  // ND_ENCM_*. Indicates encoding mode.
-    uint8_t             VexMode:4;                  // ND_VEX_*.  Indicates the VEX mode, if any.
-    uint8_t             AddrMode:4;                 // ND_ADDR_*. Indicates addressing mode.
-    uint8_t             OpMode:4;                   // ND_OPSZ_*. Indicates operand mode/size.
-    uint8_t             EfOpMode:4;                 // ND_OPSZ_*. Indicates effective operand mode/size.
-    uint8_t             VecMode:4;                  // ND_VECM_*. Indicates vector length.
-    uint8_t             EfVecMode:4;                // ND_VECM_*. Indicates effective vector length.
+    ND_UINT8            DefCode:4;                  // ND_CODE_*. Indicates disassembly mode.
+    ND_UINT8            DefData:4;                  // ND_DATA_*. Indicates default data size.
+    ND_UINT8            DefStack:4;                 // ND_STACK_*. Indicates default stack pointer width.
+    ND_UINT8            VendMode:4;                 // ND_VEND_*. Indicates vendor mode.
+    ND_UINT8            FeatMode;                   // ND_FEAT_*. Indicates which features are enabled.
+    ND_UINT8            EncMode:4;                  // ND_ENCM_*. Indicates encoding mode.
+    ND_UINT8            VexMode:4;                  // ND_VEX_*.  Indicates the VEX mode, if any.
+    ND_UINT8            AddrMode:4;                 // ND_ADDR_*. Indicates addressing mode.
+    ND_UINT8            OpMode:4;                   // ND_OPSZ_*. Indicates operand mode/size.
+    ND_UINT8            EfOpMode:4;                 // ND_OPSZ_*. Indicates effective operand mode/size.
+    ND_UINT8            VecMode:4;                  // ND_VECM_*. Indicates vector length.
+    ND_UINT8            EfVecMode:4;                // ND_VECM_*. Indicates effective vector length.
     
     // Prefixes.
-    bool                HasRex:1;                   // TRUE - REX is present.
-    bool                HasVex:1;                   // TRUE - VEX is present.
-    bool                HasXop:1;                   // TRUE - XOP is present.
-    bool                HasEvex:1;                  // TRUE - EVEX is present.
-    bool                HasMvex:1;                  // TRUE - MVEX is present.
-    bool                HasOpSize:1;                // TRUE - 0x66 present.
-    bool                HasAddrSize:1;              // TRUE - 0x67 present.
-    bool                HasLock:1;                  // TRUE - 0xF0 present.
-    bool                HasRepnzXacquireBnd:1;      // TRUE - 0xF2 present.
-    bool                HasRepRepzXrelease:1;       // TRUE - 0xF3 present.
-    bool                HasSeg:1;                   // TRUE - segment override present.
+    ND_BOOL             HasRex:1;                   // TRUE - REX is present.
+    ND_BOOL             HasVex:1;                   // TRUE - VEX is present.
+    ND_BOOL             HasXop:1;                   // TRUE - XOP is present.
+    ND_BOOL             HasEvex:1;                  // TRUE - EVEX is present.
+    ND_BOOL             HasMvex:1;                  // TRUE - MVEX is present.
+    ND_BOOL             HasOpSize:1;                // TRUE - 0x66 present.
+    ND_BOOL             HasAddrSize:1;              // TRUE - 0x67 present.
+    ND_BOOL             HasLock:1;                  // TRUE - 0xF0 present.
+    ND_BOOL             HasRepnzXacquireBnd:1;      // TRUE - 0xF2 present.
+    ND_BOOL             HasRepRepzXrelease:1;       // TRUE - 0xF3 present.
+    ND_BOOL             HasSeg:1;                   // TRUE - segment override present.
 
     // Indicators for prefix activation.
-    bool                IsRepeated:1;               // TRUE - the instruction is REPed up to RCX times.
-    bool                IsXacquireEnabled:1;        // TRUE - the instruction is XACQUIRE enabled.
-    bool                IsXreleaseEnabled:1;        // TRUE - the instruction is XRELEASE enabled.
-    bool                IsRipRelative:1;            // TRUE - the instruction uses RIP relative addressing.
-    bool                IsCetTracked:1;             // TRUE - this is an indirect CALL/JMP that is CET tracked.
+    ND_BOOL             IsRepeated:1;               // TRUE - the instruction is REPed up to RCX times.
+    ND_BOOL             IsXacquireEnabled:1;        // TRUE - the instruction is XACQUIRE enabled.
+    ND_BOOL             IsXreleaseEnabled:1;        // TRUE - the instruction is XRELEASE enabled.
+    ND_BOOL             IsRipRelative:1;            // TRUE - the instruction uses RIP relative addressing.
+    ND_BOOL             IsCetTracked:1;             // TRUE - this is an indirect CALL/JMP that is CET tracked.
 
     // Instruction chunks.
-    bool                HasModRm:1;                 // TRUE - we have valid MODRM.
-    bool                HasSib:1;                   // TRUE - we have valid SIB.
-    bool                HasDrex:1;                  // TRUE - we have valid DREX.
-    bool                HasDisp:1;                  // TRUE - the instruction has displacement.
-    bool                HasAddr:1;                  // TRUE - the instruction contains a direct address (ie, CALL far 0x9A)
-    bool                HasMoffset:1;               // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0)
-    bool                HasImm1:1;                  // TRUE - immediate present.
-    bool                HasImm2:1;                  // TRUE - second immediate present.
-    bool                HasImm3:1;                  // TRUE - third immediate present.
-    bool                HasRelOffs:1;               // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x).
-    bool                HasSseImm:1;                // TRUE - SSE immediate that encodes additional registers is present.
-    bool                HasCompDisp:1;              // TRUE - the instruction uses compressed displacement
-    bool                HasBroadcast:1;             // TRUE - the instruction uses broadcast addressing
-    bool                HasMask:1;                  // TRUE - the instruction has mask.
-    bool                HasZero:1;                  // TRUE - the instruction uses zeroing.
-    bool                HasEr:1;                    // TRUE - the instruction has embedded rounding.
-    bool                HasSae:1;                   // TRUE - the instruction has SAE.
-    bool                HasIgnEr:1;                 // TRUE - the instruction ignores embedded rounding.
-
-    bool                SignDisp:1;                 // Displacement sign. 0 is positive, 1 is negative.
+    ND_BOOL             HasModRm:1;                 // TRUE - we have valid MODRM.
+    ND_BOOL             HasSib:1;                   // TRUE - we have valid SIB.
+    ND_BOOL             HasDrex:1;                  // TRUE - we have valid DREX.
+    ND_BOOL             HasDisp:1;                  // TRUE - the instruction has displacement.
+    ND_BOOL             HasAddr:1;                  // TRUE - the instruction contains a direct address (ie, CALL far 0x9A)
+    ND_BOOL             HasMoffset:1;               // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0)
+    ND_BOOL             HasImm1:1;                  // TRUE - immediate present.
+    ND_BOOL             HasImm2:1;                  // TRUE - second immediate present.
+    ND_BOOL             HasImm3:1;                  // TRUE - third immediate present.
+    ND_BOOL             HasRelOffs:1;               // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x).
+    ND_BOOL             HasSseImm:1;                // TRUE - SSE immediate that encodes additional registers is present.
+    ND_BOOL             HasCompDisp:1;              // TRUE - the instruction uses compressed displacement
+    ND_BOOL             HasBroadcast:1;             // TRUE - the instruction uses broadcast addressing
+    ND_BOOL             HasMask:1;                  // TRUE - the instruction has mask.
+    ND_BOOL             HasZero:1;                  // TRUE - the instruction uses zeroing.
+    ND_BOOL             HasEr:1;                    // TRUE - the instruction has embedded rounding.
+    ND_BOOL             HasSae:1;                   // TRUE - the instruction has SAE.
+    ND_BOOL             HasIgnEr:1;                 // TRUE - the instruction ignores embedded rounding.
+
+    ND_BOOL             SignDisp:1;                 // Displacement sign. 0 is positive, 1 is negative.
 
     // Encoding specifics.
-    bool                HasMandatory66:1;           // 0x66 is mandatory prefix. Does not behave as size-changing prefix.
-    bool                HasMandatoryF2:1;           // 0x66 is mandatory prefix. Does not behave as REP prefix.
-    bool                HasMandatoryF3:1;           // 0x66 is mandatory prefix. Does not behave as REP prefix.
+    ND_BOOL             HasMandatory66:1;           // 0x66 is mandatory prefix. Does not behave as size-changing prefix.
+    ND_BOOL             HasMandatoryF2:1;           // 0x66 is mandatory prefix. Does not behave as REP prefix.
+    ND_BOOL             HasMandatoryF3:1;           // 0x66 is mandatory prefix. Does not behave as REP prefix.
 
     // Instruction components lengths. Will be 0 if the given field is not present.
-    uint8_t             Length;                     // 1-15 valid. Instructions longer than 15 bytes will cause #GP.
+    ND_UINT8            Length;                     // 1-15 valid. Instructions longer than 15 bytes will cause #GP.
 
-    uint8_t             WordLength:4;               // The length of the instruction word. 2, 4 or 8.
-    uint8_t             PrefLength:4;               // The total number of bytes consumed by prefixes. This will also be 
+    ND_UINT8            WordLength:4;               // The length of the instruction word. 2, 4 or 8.
+    ND_UINT8            PrefLength:4;               // The total number of bytes consumed by prefixes. This will also be 
                                                     // the offset to the first opcode. The primary opcode will always be 
                                                     // the last one, so at offset PrefixesLength + OpcodeLength - 1
-    uint8_t             OpLength:4;                 // Number of opcode bytes. Max 3.
-    uint8_t             DispLength:4;               // Displacement length, in bytes. Maximum 4.
-    uint8_t             AddrLength:4;               // Absolute address length, in bytes. Maximum 8 bytes.
-    uint8_t             MoffsetLength:4;            // Memory offset length, in bytes. Maximum 8 bytes.
-    uint8_t             Imm1Length:4;               // First immediate length, in bytes. Maximum 8 bytes.
-    uint8_t             Imm2Length:4;               // Second immediate length, in bytes. Maximum 8 bytes.
-    uint8_t             Imm3Length:4;               // Third immediate length, in bytes. Maximum 8 bytes.
-    uint8_t             RelOffsLength:4;            // Relative offset length, in bytes. Maximum 4 bytes.
+    ND_UINT8            OpLength:4;                 // Number of opcode bytes. Max 3.
+    ND_UINT8            DispLength:4;               // Displacement length, in bytes. Maximum 4.
+    ND_UINT8            AddrLength:4;               // Absolute address length, in bytes. Maximum 8 bytes.
+    ND_UINT8            MoffsetLength:4;            // Memory offset length, in bytes. Maximum 8 bytes.
+    ND_UINT8            Imm1Length:4;               // First immediate length, in bytes. Maximum 8 bytes.
+    ND_UINT8            Imm2Length:4;               // Second immediate length, in bytes. Maximum 8 bytes.
+    ND_UINT8            Imm3Length:4;               // Third immediate length, in bytes. Maximum 8 bytes.
+    ND_UINT8            RelOffsLength:4;            // Relative offset length, in bytes. Maximum 4 bytes.
 
     // Instruction components offsets. Will be 0 if the given field is not present. Prefixes ALWAYS start at offset 0.
-    uint8_t             OpOffset:4;                 // The offset of the first opcode, inside the instruction.
-    uint8_t             MainOpOffset:4;             // The offset of the nominal opcode, inside the instruction.
-    uint8_t             DispOffset:4;               // The offset of the displacement, inside the instruction
-    uint8_t             AddrOffset:4;               // The offset of the hard-coded address.
-    uint8_t             MoffsetOffset:4;            // The offset of the absolute address, inside the instruction
-    uint8_t             Imm1Offset:4;               // The offset of the immediate, inside the instruction
-    uint8_t             Imm2Offset:4;               // The offset of the second immediate, if any, inside the instruction
-    uint8_t             Imm3Offset:4;               // The offset of the third immediate, if any, inside the instruction
-    uint8_t             RelOffsOffset:4;            // The offset of the relative offset used in instruction.
-    uint8_t             SseImmOffset:4;             // The offset of the SSE immediate, if any, inside the instruction.
-    uint8_t             ModRmOffset:4;              // The offset of the mod rm byte inside the instruction, if any.
+    ND_UINT8            OpOffset:4;                 // The offset of the first opcode, inside the instruction.
+    ND_UINT8            MainOpOffset:4;             // The offset of the nominal opcode, inside the instruction.
+    ND_UINT8            DispOffset:4;               // The offset of the displacement, inside the instruction
+    ND_UINT8            AddrOffset:4;               // The offset of the hard-coded address.
+    ND_UINT8            MoffsetOffset:4;            // The offset of the absolute address, inside the instruction
+    ND_UINT8            Imm1Offset:4;               // The offset of the immediate, inside the instruction
+    ND_UINT8            Imm2Offset:4;               // The offset of the second immediate, if any, inside the instruction
+    ND_UINT8            Imm3Offset:4;               // The offset of the third immediate, if any, inside the instruction
+    ND_UINT8            RelOffsOffset:4;            // The offset of the relative offset used in instruction.
+    ND_UINT8            SseImmOffset:4;             // The offset of the SSE immediate, if any, inside the instruction.
+    ND_UINT8            ModRmOffset:4;              // The offset of the mod rm byte inside the instruction, if any.
                                                     // If SIB is also present, it will always be at ModRmOffset + 1.
 
-    uint8_t             StackWords;                 // Number of words accessed on/from the stack.
+    ND_UINT8            StackWords;                 // Number of words accessed on/from the stack.
 
-    uint8_t             Rep;                        // The last rep/repz/repnz prefix. 0 if none.
-    uint8_t             Seg;                        // The last segment override prefix. 0 if none. FS/GS if 64 bit.
-    uint8_t             Bhint;                      // The last segment override indicating a branch hint.
+    ND_UINT8            Rep;                        // The last rep/repz/repnz prefix. 0 if none.
+    ND_UINT8            Seg;                        // The last segment override prefix. 0 if none. FS/GS if 64 bit.
+    ND_UINT8            Bhint;                      // The last segment override indicating a branch hint.
     ND_REX              Rex;                        // REX prefix.
     ND_MODRM            ModRm;                      // ModRM byte.
     ND_SIB              Sib;                        // SIB byte.
@@ -1356,60 +1357,60 @@ typedef struct _INSTRUX
     // fields directly from here, regardless the actual encoding mode.
     struct
     {
-        uint32_t        w:1;                        // REX/XOP/VEX/EVEX/MVEX.W field
-        uint32_t        r:1;                        // REX/XOP/VEX/EVEX/MVEX.R field (reg extension)
-        uint32_t        x:1;                        // REX/XOP/VEX/EVEX/MVEX.X field (index extension)
-        uint32_t        b:1;                        // REX/XOP/VEX/EVEX/MVEX.B field (base extension)
-        uint32_t        rp:1;                       // EVEX/MVEX.R' (reg extension)
-        uint32_t        p:2;                        // XOP/VEX/EVEX/MVEX.pp (embedded prefix)
-        uint32_t        m:5;                        // XOP/VEX/EVEX/MVEX.mmmmm (decoding table)
-        uint32_t        l:2;                        // XOP/VEX.L or EVEX.L'L (vector length)
-        uint32_t        v:4;                        // XOP/VEX.VVVV or EVEX/MVEX.VVVV (additional operand)
-        uint32_t        vp:1;                       // EVEX/MVEX.V' (vvvv extension)
-        uint32_t        bm:1;                       // EVEX.b (broadcast)
-        uint32_t        e:1;                        // MVEX.e (eviction hint)
-        uint32_t        z:1;                        // EVEX.z (zero)
-        uint32_t        k:3;                        // EVEX.aaa/MVEX.kkk (mask registers)
-        uint32_t        s:3;                        // MVEX.sss (swizzle)
+        ND_UINT32       w:1;                        // REX/XOP/VEX/EVEX/MVEX.W field
+        ND_UINT32       r:1;                        // REX/XOP/VEX/EVEX/MVEX.R field (reg extension)
+        ND_UINT32       x:1;                        // REX/XOP/VEX/EVEX/MVEX.X field (index extension)
+        ND_UINT32       b:1;                        // REX/XOP/VEX/EVEX/MVEX.B field (base extension)
+        ND_UINT32       rp:1;                       // EVEX/MVEX.R' (reg extension)
+        ND_UINT32       p:2;                        // XOP/VEX/EVEX/MVEX.pp (embedded prefix)
+        ND_UINT32       m:5;                        // XOP/VEX/EVEX/MVEX.mmmmm (decoding table)
+        ND_UINT32       l:2;                        // XOP/VEX.L or EVEX.L'L (vector length)
+        ND_UINT32       v:4;                        // XOP/VEX.VVVV or EVEX/MVEX.VVVV (additional operand)
+        ND_UINT32       vp:1;                       // EVEX/MVEX.V' (vvvv extension)
+        ND_UINT32       bm:1;                       // EVEX.b (broadcast)
+        ND_UINT32       e:1;                        // MVEX.e (eviction hint)
+        ND_UINT32       z:1;                        // EVEX.z (zero)
+        ND_UINT32       k:3;                        // EVEX.aaa/MVEX.kkk (mask registers)
+        ND_UINT32       s:3;                        // MVEX.sss (swizzle)
     } Exs;
 
     union
     {
         struct
         {
-            uint32_t    Ip;
-            uint16_t    Cs;
+            ND_UINT32   Ip;
+            ND_UINT16   Cs;
         };
     } Address;                                      // seg:offset address.
 
-    uint64_t            Moffset;                    // Offset. Used by 'O' operands. It's an absolute address.
-    uint32_t            Displacement;               // Displacement. Max 4 bytes. Used in ModRM instructions.
-    uint32_t            RelativeOffset;             // Relative offset, used for branches. Max 4 bytes.
-    uint64_t            Immediate1;                 // Can be 8 bytes on x64
-    uint8_t             Immediate2;                 // For enter, mainly. Can only be 1 byte.
-    uint8_t             Immediate3;                 // Third additional immediate. Limited to 1 byte for now.
-    uint8_t             SseImmediate;               // This immediate actually selects a register.
-    uint8_t             SseCondition;               // Condition code encoded in additional byte.
-    uint8_t             Condition;                  // Condition code encoded in low 4 bit of the opcode.
-    uint8_t             Predicate;                  // Same as Condition, kept for backwards compatibility.
-
-    uint8_t             OperandsCount;              // Number of operands.
-    uint8_t             ExpOperandsCount;           // Number of explicit operands. Use this if you want to ignore
+    ND_UINT64           Moffset;                    // Offset. Used by 'O' operands. It's an absolute address.
+    ND_UINT32           Displacement;               // Displacement. Max 4 bytes. Used in ModRM instructions.
+    ND_UINT32           RelativeOffset;             // Relative offset, used for branches. Max 4 bytes.
+    ND_UINT64           Immediate1;                 // Can be 8 bytes on x64
+    ND_UINT8            Immediate2;                 // For enter, mainly. Can only be 1 byte.
+    ND_UINT8            Immediate3;                 // Third additional immediate. Limited to 1 byte for now.
+    ND_UINT8            SseImmediate;               // This immediate actually selects a register.
+    ND_UINT8            SseCondition;               // Condition code encoded in additional byte.
+    ND_UINT8            Condition;                  // Condition code encoded in low 4 bit of the opcode.
+    ND_UINT8            Predicate;                  // Same as Condition, kept for backwards compatibility.
+
+    ND_UINT8            OperandsCount;              // Number of operands.
+    ND_UINT8            ExpOperandsCount;           // Number of explicit operands. Use this if you want to ignore
                                                     // implicit operands such as stack, flags, etc.
-    uint16_t            OperandsEncodingMap;        // What parts of the instruction encode operands.
+    ND_UINT16           OperandsEncodingMap;        // What parts of the instruction encode operands.
     ND_OPERAND          Operands[ND_MAX_OPERAND];   // Instruction operands.
 
     // As extracted from the operands themselves.
-    uint8_t             CsAccess;                   // CS access mode (read/write). Includes only implicit CS accesses.
-    uint8_t             RipAccess;                  // RIP access mode (read/write).
-    uint8_t             StackAccess;                // Stack access mode (push/pop).
-    uint8_t             MemoryAccess;               // Memory access mode (read/write, including stack or shadow stack).
+    ND_UINT8            CsAccess;                   // CS access mode (read/write). Includes only implicit CS accesses.
+    ND_UINT8            RipAccess;                  // RIP access mode (read/write).
+    ND_UINT8            StackAccess;                // Stack access mode (push/pop).
+    ND_UINT8            MemoryAccess;               // Memory access mode (read/write, including stack or shadow stack).
 
     ND_BRANCH_INFO      BranchInfo;                 // Branch information.
 
     struct
     {
-        uint8_t         RegAccess;                  // RFLAGS access mode (read/write), as per the entire register.
+        ND_UINT8        RegAccess;                  // RFLAGS access mode (read/write), as per the entire register.
         ND_RFLAGS       Tested;                     // Tested flags.
         ND_RFLAGS       Modified;                   // Modified (according to the result) flags.
         ND_RFLAGS       Set;                        // Flags that are always set to 1.
@@ -1419,14 +1420,14 @@ typedef struct _INSTRUX
 
     ND_FPU_FLAGS        FpuFlagsAccess;             // FPU status word C0-C3 bits access. Valid only for FPU instructions!
 
-    uint8_t             ExceptionClass;             // ND_EX_CLASS_TYPE, indicates the exception class type.
-    uint8_t             ExceptionType;              // Exception type. Depends on ExceptionClass.
-    uint8_t             TupleType;                  // EVEX tuple type, if EVEX. Check out ND_TUPLE.
-    uint8_t             RoundingMode;               // EVEX rounding mode, if present. Check out ND_ROUNDING.
+    ND_UINT8            ExceptionClass;             // ND_EX_CLASS_TYPE, indicates the exception class type.
+    ND_UINT8            ExceptionType;              // Exception type. Depends on ExceptionClass.
+    ND_UINT8            TupleType;                  // EVEX tuple type, if EVEX. Check out ND_TUPLE.
+    ND_UINT8            RoundingMode;               // EVEX rounding mode, if present. Check out ND_ROUNDING.
 
     // Stored inside the instruction entry as well. These are specific for an instruction and do not depend on
     // encoding. Use the flags definitions (ND_FLAG_*, ND_PREF_*, ND_DECO_*, ND_EXOP_*) to access specific bits.
-    uint32_t            Attributes;                 // Instruction attributes/flags. A collection of ND_FLAG_*.
+    ND_UINT32           Attributes;                 // Instruction attributes/flags. A collection of ND_FLAG_*.
     union
     {
         ND_INS_CLASS    Instruction;                // One of the ND_INS_*
@@ -1439,9 +1440,9 @@ typedef struct _INSTRUX
     ND_VALID_PREFIXES   ValidPrefixes;              // Indicates which prefixes are valid for this instruction.
     ND_VALID_DECORATORS ValidDecorators;            // What decorators are accepted by the instruction.
     char                Mnemonic[ND_MAX_MNEMONIC_LENGTH];   // Instruction mnemonic.
-    uint8_t             OpCodeBytes[3];             // Opcode bytes - escape codes and main op code
-    uint8_t             PrimaryOpCode;              // Main/nominal opcode
-    uint8_t             InstructionBytes[16];       // The entire instruction.
+    ND_UINT8            OpCodeBytes[3];             // Opcode bytes - escape codes and main op code
+    ND_UINT8            PrimaryOpCode;              // Main/nominal opcode
+    ND_UINT8            InstructionBytes[16];       // The entire instruction.
 
 } INSTRUX, *PINSTRUX;
 
@@ -1452,12 +1453,12 @@ typedef struct _INSTRUX
 //
 typedef struct _ND_CONTEXT
 {
-    uint64_t DefCode : 4;       // Decode mode - one of the ND_CODE_* values.
-    uint64_t DefData : 4;       // Data mode - one of the ND_DATA_* values.
-    uint64_t DefStack : 4;      // Stack mode - one of the ND_STACK_* values.
-    uint64_t VendMode : 4;      // Prefered vendor - one of the ND_VEND_* values.
-    uint64_t FeatMode : 8;      // Supported features mask. A combination of ND_FEAT_* values.
-    uint64_t Reserved : 40;     // Reserved for future use.
+    ND_UINT64   DefCode : 4;       // Decode mode - one of the ND_CODE_* values.
+    ND_UINT64   DefData : 4;       // Data mode - one of the ND_DATA_* values.
+    ND_UINT64   DefStack : 4;      // Stack mode - one of the ND_STACK_* values.
+    ND_UINT64   VendMode : 4;      // Prefered vendor - one of the ND_VEND_* values.
+    ND_UINT64   FeatMode : 8;      // Supported features mask. A combination of ND_FEAT_* values.
+    ND_UINT64   Reserved : 40;     // Reserved for future use.
 } ND_CONTEXT;
 
 
@@ -1467,26 +1468,26 @@ typedef struct _ND_CONTEXT
 //
 typedef struct _ND_ACCESS_MAP
 {
-    uint8_t         RipAccess;
-    uint8_t         FlagsAccess;
-    uint8_t         StackAccess;
-    uint8_t         MemAccess;
-    uint8_t         MxcsrAccess;
-    uint8_t         PkruAccess;
-    uint8_t         SspAccess;
-    uint8_t         GprAccess[ND_MAX_GPR_REGS];
-    uint8_t         SegAccess[ND_MAX_SEG_REGS];
-    uint8_t         FpuAccess[ND_MAX_FPU_REGS];
-    uint8_t         MmxAccess[ND_MAX_MMX_REGS];
-    uint8_t         SseAccess[ND_MAX_SSE_REGS];
-    uint8_t         CrAccess [ND_MAX_CR_REGS ];
-    uint8_t         DrAccess [ND_MAX_DR_REGS ];
-    uint8_t         TrAccess [ND_MAX_TR_REGS ];
-    uint8_t         BndAccess[ND_MAX_BND_REGS];
-    uint8_t         MskAccess[ND_MAX_MSK_REGS];
-    uint8_t         TmmAccess[ND_MAX_TILE_REGS];
-    uint8_t         SysAccess[ND_MAX_SYS_REGS];
-    uint8_t         X87Access[ND_MAX_X87_REGS];
+    ND_UINT8    RipAccess;
+    ND_UINT8    FlagsAccess;
+    ND_UINT8    StackAccess;
+    ND_UINT8    MemAccess;
+    ND_UINT8    MxcsrAccess;
+    ND_UINT8    PkruAccess;
+    ND_UINT8    SspAccess;
+    ND_UINT8    GprAccess[ND_MAX_GPR_REGS];
+    ND_UINT8    SegAccess[ND_MAX_SEG_REGS];
+    ND_UINT8    FpuAccess[ND_MAX_FPU_REGS];
+    ND_UINT8    MmxAccess[ND_MAX_MMX_REGS];
+    ND_UINT8    SseAccess[ND_MAX_SSE_REGS];
+    ND_UINT8    CrAccess [ND_MAX_CR_REGS ];
+    ND_UINT8    DrAccess [ND_MAX_DR_REGS ];
+    ND_UINT8    TrAccess [ND_MAX_TR_REGS ];
+    ND_UINT8    BndAccess[ND_MAX_BND_REGS];
+    ND_UINT8    MskAccess[ND_MAX_MSK_REGS];
+    ND_UINT8    TmmAccess[ND_MAX_TILE_REGS];
+    ND_UINT8    SysAccess[ND_MAX_SYS_REGS];
+    ND_UINT8    X87Access[ND_MAX_X87_REGS];
 } ND_ACCESS_MAP, *PND_ACCESS_MAP;
 
 
@@ -1540,9 +1541,9 @@ extern "C" {
 //
 void
 NdGetVersion(
-    uint32_t *Major,
-    uint32_t *Minor,
-    uint32_t *Revision,
+    ND_UINT32 *Major,
+    ND_UINT32 *Minor,
+    ND_UINT32 *Revision,
     char **BuildDate,
     char **BuildTime
     );
@@ -1556,9 +1557,9 @@ NdGetVersion(
 NDSTATUS
 NdDecode(
     INSTRUX *Instrux,       // Output decoded instruction.
-    const uint8_t *Code,    // Buffer containing the instruction bytes.
-    uint8_t DefCode,        // Decode mode - one of the ND_CODE_* values.
-    uint8_t DefData         // Data mode - one of the ND_DATA_* value.
+    const ND_UINT8 *Code,    // Buffer containing the instruction bytes.
+    ND_UINT8 DefCode,        // Decode mode - one of the ND_CODE_* values.
+    ND_UINT8 DefData         // Data mode - one of the ND_DATA_* value.
     );
 
 //
@@ -1571,10 +1572,10 @@ NdDecode(
 NDSTATUS
 NdDecodeEx(
     INSTRUX *Instrux,       // Output decoded instruction.
-    const uint8_t *Code,    // Buffer containing the instruction bytes.
-    size_t Size,            // Maximum size of the Code buffer.
-    uint8_t DefCode,        // Decode mode - one of the ND_CODE_* values.
-    uint8_t DefData         // Data mode - one of the ND_DATA_* value.
+    const ND_UINT8 *Code,      // Buffer containing the instruction bytes.
+    ND_SIZET Size,          // Maximum size of the Code buffer.
+    ND_UINT8 DefCode,          // Decode mode - one of the ND_CODE_* values.
+    ND_UINT8 DefData           // Data mode - one of the ND_DATA_* value.
     );
 
 //
@@ -1583,12 +1584,12 @@ NdDecodeEx(
 NDSTATUS
 NdDecodeEx2(
     INSTRUX *Instrux,       // Output decoded instruction.
-    const uint8_t *Code,    // Buffer containing the instruction bytes.
-    size_t Size,            // Maximum size of the Code buffer.
-    uint8_t DefCode,        // Decode mode - one of the ND_CODE_* values.
-    uint8_t DefData,        // Data mode - one of the ND_DATA_* value.
-    uint8_t DefStack,       // Stack mode - one of the ND_STACK_* values.
-    uint8_t PreferedVendor  // Preferred vendor - one of the ND_VEND_* values.
+    const ND_UINT8 *Code,      // Buffer containing the instruction bytes.
+    ND_SIZET Size,          // Maximum size of the Code buffer.
+    ND_UINT8 DefCode,          // Decode mode - one of the ND_CODE_* values.
+    ND_UINT8 DefData,          // Data mode - one of the ND_DATA_* value.
+    ND_UINT8 DefStack,         // Stack mode - one of the ND_STACK_* values.
+    ND_UINT8 PreferedVendor    // Preferred vendor - one of the ND_VEND_* values.
     );
 
 //
@@ -1603,8 +1604,8 @@ NdDecodeEx2(
 NDSTATUS
 NdDecodeWithContext(
     INSTRUX *Instrux,       // Output decoded instruction.
-    const uint8_t *Code,    // Buffer containing the instruction bytes.
-    size_t Size,            // Maximum size of the Code buffer.
+    const ND_UINT8 *Code,      // Buffer containing the instruction bytes.
+    ND_SIZET Size,          // Maximum size of the Code buffer.
     ND_CONTEXT *Context     // Context describing decode mode, vendor mode and supported features.
     );
 
@@ -1614,8 +1615,8 @@ NdDecodeWithContext(
 NDSTATUS
 NdToText(
     const INSTRUX *Instrux,
-    uint64_t Rip,
-    uint32_t BufferSize,
+    ND_UINT64 Rip,
+    ND_UINT32 BufferSize,
     char *Buffer
     );
 
@@ -1623,7 +1624,7 @@ NdToText(
 // Returns true if the instruction is RIP relative. Note that this function is kept for backwards compatibility, since
 // there already is a IsRipRelative field inside INSTRUX.
 //
-bool
+ND_BOOL
 NdIsInstruxRipRelative(
     const INSTRUX *Instrux
     );
diff --git a/inc/bdshemu.h b/inc/bdshemu.h
index 5e9cd15..b1b6bf0 100644
--- a/inc/bdshemu.h
+++ b/inc/bdshemu.h
@@ -27,13 +27,13 @@ typedef void
 // Note that by using the ShemuContext, the integrator knows whether the access is user or supervisor (the Ring field
 // inside ShemuContext), and he knows whether it is 16/32/64 bit mode (Mode field inside ShemuContext).
 // 
-typedef bool
+typedef ND_BOOL
 (*ShemuMemAccess)(
     void *ShemuContext, // Shemu emulation context.
-    uint64_t Gla,       // Linear address to be accessed.
-    size_t Size,        // Number of bytes to access.
-    uint8_t *Buffer,    // Contains the read content (if Store is false), or the value to be stored at Gla.
-    bool Store          // If false, read content at Gla. Otherwise, write content at Gla.
+    ND_UINT64 Gla,      // Linear address to be accessed.
+    ND_SIZET Size,      // Number of bytes to access.
+    ND_UINT8 *Buffer,   // Contains the read content (if Store is false), or the value to be stored at Gla.
+    ND_BOOL Store       // If false, read content at Gla. Otherwise, write content at Gla.
     );
 
 
@@ -51,36 +51,35 @@ typedef bool
 //
 typedef struct _SHEMU_GPR_REGS
 {
-    uint64_t RegRax;
-    uint64_t RegRcx;
-    uint64_t RegRdx;
-    uint64_t RegRbx;
-    uint64_t RegRsp;
-    uint64_t RegRbp;
-    uint64_t RegRsi;
-    uint64_t RegRdi;
-    uint64_t RegR8;
-    uint64_t RegR9;
-    uint64_t RegR10;
-    uint64_t RegR11;
-    uint64_t RegR12;
-    uint64_t RegR13;
-    uint64_t RegR14;
-    uint64_t RegR15;
-    uint64_t RegCr2;
-    uint64_t RegFlags;
-    uint64_t RegDr7;
-    uint64_t RegRip;
-    uint64_t RegCr0;
-    uint64_t RegCr4;
-    uint64_t RegCr3;
-    uint64_t RegCr8;
-    uint64_t RegIdtBase;
-    uint64_t RegIdtLimit;
-    uint64_t RegGdtBase;
-    uint64_t RegGdtLimit;
-
-    uint64_t FpuRip;
+    ND_UINT64   RegRax;
+    ND_UINT64   RegRcx;
+    ND_UINT64   RegRdx;
+    ND_UINT64   RegRbx;
+    ND_UINT64   RegRsp;
+    ND_UINT64   RegRbp;
+    ND_UINT64   RegRsi;
+    ND_UINT64   RegRdi;
+    ND_UINT64   RegR8;
+    ND_UINT64   RegR9;
+    ND_UINT64   RegR10;
+    ND_UINT64   RegR11;
+    ND_UINT64   RegR12;
+    ND_UINT64   RegR13;
+    ND_UINT64   RegR14;
+    ND_UINT64   RegR15;
+    ND_UINT64   RegCr2;
+    ND_UINT64   RegFlags;
+    ND_UINT64   RegDr7;
+    ND_UINT64   RegRip;
+    ND_UINT64   RegCr0;
+    ND_UINT64   RegCr4;
+    ND_UINT64   RegCr3;
+    ND_UINT64   RegCr8;
+    ND_UINT64   RegIdtBase;
+    ND_UINT64   RegIdtLimit;
+    ND_UINT64   RegGdtBase;
+    ND_UINT64   RegGdtLimit;
+    ND_UINT64   FpuRip;
 } SHEMU_GPR_REGS, *PSHEMU_GPR_REGS;
 
 
@@ -89,10 +88,10 @@ typedef struct _SHEMU_GPR_REGS
 //
 typedef struct _SHEMU_SEG
 {
-    uint64_t    Base;
-    uint64_t    Limit;
-    uint64_t    Selector;
-    uint64_t    AccessRights;
+    ND_UINT64   Base;
+    ND_UINT64   Limit;
+    ND_UINT64   Selector;
+    ND_UINT64   AccessRights;
 } SHEMU_SEG, *PSHEMU_SEG;
 
 
@@ -127,85 +126,85 @@ typedef struct _SHEMU_CONTEXT
     SHEMU_SEG_REGS  Segments;
 
     // MMX register state. 8 x 8 bytes = 64 bytes for the MMX registers. Can be provided on input, if needed.
-    uint64_t        MmxRegisters[ND_MAX_MMX_REGS];
+    ND_UINT64       MmxRegisters[ND_MAX_MMX_REGS];
 
     // SSE registers state. 32 x 64 bytes = 2048 bytes for the SSE registers. Can be provided on input, if needed.
-    uint8_t         SseRegisters[ND_MAX_SSE_REGS * ND_MAX_REGISTER_SIZE];
+    ND_UINT8        SseRegisters[ND_MAX_SSE_REGS * ND_MAX_REGISTER_SIZE];
 
     // General purpose registers write bitmap. After the first write, a register will be marked dirty in here. 
     // Should be 0 on input.
-    uint16_t        DirtyGprBitmap;
+    ND_UINT16       DirtyGprBitmap;
 
     // Operating mode (ND_CODE_16, ND_CODE_32 or ND_CODE_64). Must be provided as input.
-    uint8_t         Mode;
+    ND_UINT8        Mode;
 
     // Operating ring (0, 1, 2, 3). Must be provided as input.
-    uint8_t         Ring;
+    ND_UINT8        Ring;
 
     // The suspicious code to be emulated. Must be provided as input.
-    uint8_t         *Shellcode;
+    ND_UINT8        *Shellcode;
 
     // Virtual stack. RSP will point somewhere inside. Must be allocated as input, and it can be initialized with
     // actual stack contents. Can also be 0-filled.
-    uint8_t         *Stack;
+    ND_UINT8        *Stack;
 
     // Internal use. Must be at least the size of the shell + stack. Needs not be initialized, but must be allocated
     // and accessible on input.
-    uint8_t         *Intbuf;
+    ND_UINT8        *Intbuf;
 
     // Shellcode base address (the address the shellcode would see). Must be provided as input.
-    uint64_t        ShellcodeBase;
+    ND_UINT64       ShellcodeBase;
 
     // Stack base address (the RSP the shellcode would see). Must be provided as input.
-    uint64_t        StackBase;
+    ND_UINT64       StackBase;
 
     // Shellcode size. Must be provided as input. Usually just a page in size, but can be larger.
-    uint32_t        ShellcodeSize;
+    ND_UINT32       ShellcodeSize;
 
     // Stack size. Must be provided as input. Minimum two pages.
-    uint32_t        StackSize;
+    ND_UINT32       StackSize;
 
     // Internal buffer size. Must be provided as input. Must be at least the size of the shell + stack.
-    uint32_t        IntbufSize;
+    ND_UINT32       IntbufSize;
 
     // Number of NOPs encountered. Should be 0 on input.
-    uint32_t        NopCount;
+    ND_UINT32       NopCount;
 
     // The length of the string constructed on the stack, if any. Should be 0 on input.
-    uint32_t        StrLength;
+    ND_UINT32       StrLength;
 
     // Number of external memory access (outside stack/shellcode). Should be 0 on input.
-    uint32_t        ExtMemAccess;
+    ND_UINT32       ExtMemAccess;
 
     // Number of emulated instructions. Should be 0 on input. Once InstructionsCount reaches MaxInstructionsCount,
     // emulation will stop.
-    uint32_t        InstructionsCount;
+    ND_UINT32       InstructionsCount;
 
     // Max number of instructions that should be emulated. Once this limit has been reached, emulation will stop. 
     // Lower values will mean faster processing, but less chances of detection. Higher values mean low performance,
     // but very high chances of yielding useful results. Must be provided as input. 
-    uint32_t        MaxInstructionsCount;
+    ND_UINT32       MaxInstructionsCount;
 
     // Base address of the Thread Information Block (the TIB the shellcode would normally see). Must be provided as 
     // input.
-    uint64_t        TibBase;
+    ND_UINT64       TibBase;
 
     // Shellcode Flags (see SHEMU_FLAG_*). Must be provided as input.
-    uint64_t        Flags;
+    ND_UINT64       Flags;
 
     // Emulation options. See SHEMU_OPT_* for possible options. Must be provided as input.
-    uint32_t        Options;
+    ND_UINT32       Options;
 
     // Percent of NOPs (out of total instructions emulated) that trigger NOP sled detection. Must be provided as input. 
-    uint32_t        NopThreshold;
+    ND_UINT32       NopThreshold;
 
     // Stack string length threshold. Stack-constructed strings must be at least this long to trigger stack string
     // detection. Must be provided as input.
-    uint32_t        StrThreshold;
+    ND_UINT32       StrThreshold;
 
     // Number of external mem accesses threshold. No more than this number of external accesses will be issued. Must 
     // be provided as input.
-    uint32_t        MemThreshold;
+    ND_UINT32       MemThreshold;
 
     // Optional auxiliary data, provided by the integrator. Can be NULL, or can point to integrator specific data.
     // Shemu will not use this data in any way, but callbacks that receive a SHEMU_CONTEXT pointer (such as
diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h
index 5950072..dd330ff 100644
--- a/inc/cpuidflags.h
+++ b/inc/cpuidflags.h
@@ -5,7 +5,7 @@
 #define ND_CFF_NO_SUBLEAF 0x00FFFFFF
 
 
-#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59))
+#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))
 
 #define ND_CFF_FPU                      ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 0)
 #define ND_CFF_MSR                      ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 5)
diff --git a/inc/disasmstatus.h b/inc/disasmstatus.h
index dbb9a53..050a632 100644
--- a/inc/disasmstatus.h
+++ b/inc/disasmstatus.h
@@ -8,7 +8,7 @@
 //
 // Return statuses.
 //
-typedef unsigned int NDSTATUS;
+typedef ND_UINT32 NDSTATUS;
 
 // Success codes are all < 0x80000000.
 #define ND_STATUS_SUCCESS                               0x00000000 // All good.
diff --git a/inc/disasmtypes.h b/inc/disasmtypes.h
index 08a973c..2e51c0c 100644
--- a/inc/disasmtypes.h
+++ b/inc/disasmtypes.h
@@ -5,35 +5,96 @@
 #ifndef DISASM_TYPES_H
 #define DISASM_TYPES_H
 
-#if defined(_KERNEL_MODE) && defined(_MSC_VER)
-# include <ntddk.h>
-# include <Ntstrsafe.h>
-# include <basetsd.h>
 
-typedef UINT8 uint8_t;
-typedef UINT16 uint16_t;
-typedef UINT32 uint32_t;
-typedef UINT64 uint64_t;
+#if defined(_MSC_VER) || defined(__ICC) || defined(__INTEL_COMPILER)
 
-typedef INT8 int8_t;
-typedef INT16 int16_t;
-typedef INT32 int32_t;
-typedef INT64 int64_t;
+// Microsoft VC compiler.
 
-typedef _Bool bool;
-#define false 0
-#define true 1
+typedef unsigned __int8 ND_UINT8;
+typedef unsigned __int16 ND_UINT16;
+typedef unsigned __int32 ND_UINT32;
+typedef unsigned __int64 ND_UINT64;
+typedef signed __int8 ND_SINT8;
+typedef signed __int16 ND_SINT16;
+typedef signed __int32 ND_SINT32;
+typedef signed __int64 ND_SINT64;
 
-#elif defined(__KERNEL__) && defined(__GNUC__)
+#elif defined(__GNUC__) || defined(__GNUG__) || defined(__clang__)
 
-# include <linux/types.h>
+// clang/GCC compiler.
+
+typedef __UINT8_TYPE__ ND_UINT8;
+typedef __UINT16_TYPE__ ND_UINT16;
+typedef __UINT32_TYPE__ ND_UINT32;
+typedef __UINT64_TYPE__ ND_UINT64;
+typedef __INT8_TYPE__ ND_SINT8;
+typedef __INT16_TYPE__ ND_SINT16;
+typedef __INT32_TYPE__ ND_SINT32;
+typedef __INT64_TYPE__ ND_SINT64;
 
 #else
 
-# include <stddef.h>
-# include <stdint.h>
-# include <stdbool.h>
+// other compilers, assume stdint is present.
+
+#include <stdint.h>
+
+typedef uint8_t ND_UINT8;
+typedef uint16_t ND_UINT16;
+typedef uint32_t ND_UINT32;
+typedef uint64_t ND_UINT64;
+typedef int8_t ND_SINT8;
+typedef int16_t ND_SINT16;
+typedef int32_t ND_SINT32;
+typedef int64_t ND_SINT64;
 
 #endif
 
+
+
+#if defined(_M_AMD64) || defined(__x86_64__)
+
+#define ND_ARCH_X64
+
+#elif defined(_M_IX86) || defined(__i386__)
+
+#define ND_ARCH_X86
+
+#elif defined(_M_ARM64) || defined(__aarch64__)
+
+#define ND_ARCH_AARCH64
+
+#elif defined(_M_ARM) || defined(__arm__)
+
+#define ND_ARCH_ARM
+
+#else
+
+#error "Unknown architecture!"
+
+#endif
+
+
+// Handle architecture definitions.
+#if defined(ND_ARCH_X64) || defined(ND_ARCH_AARCH64)
+
+typedef ND_UINT64 ND_SIZET;
+
+#elif defined(ND_ARCH_X86) || defined(ND_ARCH_ARM)
+
+typedef ND_UINT32 ND_SIZET;
+
+#else
+
+#error "Unknown architecture!"
+
+#endif
+
+
+// Common definitions.
+typedef ND_UINT8 ND_BOOL;
+
+#define ND_NULL		((void *)(0))
+#define ND_TRUE		(1)
+#define ND_FALSE	(0)
+
 #endif
diff --git a/inc/version.h b/inc/version.h
index e96c8ce..f91a7a2 100644
--- a/inc/version.h
+++ b/inc/version.h
@@ -7,6 +7,6 @@
 
 #define DISASM_VERSION_MAJOR        1
 #define DISASM_VERSION_MINOR        34
-#define DISASM_VERSION_REVISION     9
+#define DISASM_VERSION_REVISION     10
 
 #endif // DISASM_VER_H
diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py
index fa0fff1..6d195ac 100644
--- a/isagenerator/generate_tables.py
+++ b/isagenerator/generate_tables.py
@@ -1215,7 +1215,7 @@ def dump_translation_tree_c(t, hname, f):
         i = 0
         for p in pointers:
             if not p:
-                res += '        /* %02x */ NULL,\n' % i
+                res += '        /* %02x */ ND_NULL,\n' % i
             else:
                 res += '        /* %02x */ (const void *)&%s,\n' % (i, p)
             i += 1
@@ -1250,7 +1250,7 @@ def generate_features(features, fname):
     f.write('#define ND_CFF_NO_SUBLEAF 0x00FFFFFF\n')
     f.write('\n')
     f.write('\n')
-    f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59))\n')
+    f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))\n')
     f.write('\n')
 
     for c in features:
diff --git a/isagenerator/instructions/table_0F_38.dat b/isagenerator/instructions/table_0F_38.dat
index 275658d..fb160a5 100644
--- a/isagenerator/instructions/table_0F_38.dat
+++ b/isagenerator/instructions/table_0F_38.dat
@@ -125,8 +125,8 @@ MOVBE               Mv,Gv                 nil               [            0x0F 0x
 MOVBE               Mv,Gv                 nil               [       0x66 0x0F 0x38 0xF1 /r:mem]     s:MOVBE, t:DATAXFER, w:W|R, a:S66
 CRC32               Gy,Ev                 nil               [       0xF2 0x0F 0x38 0xF1 /r]         s:SSE42, t:SSE, w:RW|R
 CRC32               Gy,Ev                 nil               [  0x66 0xF2 0x0F 0x38 0xF1 /r]         s:SSE42, t:SSE, w:RW|R, a:S66
-WRUSSD              My,Gy                 nil               [       0x66 0x0F 0x38 0xF5 /r:mem]     s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
-WRUSSQ              My,Gy                 nil               [  rexw 0x66 0x0F 0x38 0xF5 /r:mem]     s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
+WRUSSD              My,Gy                 nil               [       0x66 0x0F 0x38 0xF5 /r:mem]     s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R, m:KERNEL
+WRUSSQ              My,Gy                 nil               [  rexw 0x66 0x0F 0x38 0xF5 /r:mem]     s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R, m:KERNEL
 WRSSD               My,Gy                 nil               [         NP 0x0F 0x38 0xF6 /r:mem]     s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
 WRSSQ               My,Gy                 nil               [    rexw NP 0x0F 0x38 0xF6 /r:mem]     s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
 ADCX                Gy,Ey                 Fv                [       0x66 0x0F 0x38 0xF6 /r]         s:ADX, t:ARITH, w:RW|R|RW, f:CF=m
diff --git a/isagenerator/isagenerator.vcxproj b/isagenerator/isagenerator.vcxproj
index 5134d36..766a83b 100644
--- a/isagenerator/isagenerator.vcxproj
+++ b/isagenerator/isagenerator.vcxproj
@@ -1,10 +1,18 @@
 <?xml version="1.0" encoding="utf-8"?>
 <Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
   <ItemGroup Label="ProjectConfigurations">
+    <ProjectConfiguration Include="Debug|ARM64">
+      <Configuration>Debug</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Debug|Win32">
       <Configuration>Debug</Configuration>
       <Platform>Win32</Platform>
     </ProjectConfiguration>
+    <ProjectConfiguration Include="Release|ARM64">
+      <Configuration>Release</Configuration>
+      <Platform>ARM64</Platform>
+    </ProjectConfiguration>
     <ProjectConfiguration Include="Release|Win32">
       <Configuration>Release</Configuration>
       <Platform>Win32</Platform>
@@ -43,6 +51,12 @@
     <PlatformToolset>v142</PlatformToolset>
     <CharacterSet>MultiByte</CharacterSet>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="Configuration">
+    <ConfigurationType>Application</ConfigurationType>
+    <UseDebugLibraries>true</UseDebugLibraries>
+    <PlatformToolset>v142</PlatformToolset>
+    <CharacterSet>MultiByte</CharacterSet>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="Configuration">
     <ConfigurationType>Application</ConfigurationType>
     <UseDebugLibraries>false</UseDebugLibraries>
@@ -50,6 +64,13 @@
     <WholeProgramOptimization>true</WholeProgramOptimization>
     <CharacterSet>MultiByte</CharacterSet>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="Configuration">
+    <ConfigurationType>Application</ConfigurationType>
+    <UseDebugLibraries>false</UseDebugLibraries>
+    <PlatformToolset>v142</PlatformToolset>
+    <WholeProgramOptimization>true</WholeProgramOptimization>
+    <CharacterSet>MultiByte</CharacterSet>
+  </PropertyGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
   <ImportGroup Label="ExtensionSettings">
   </ImportGroup>
@@ -64,9 +85,15 @@
   <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
     <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
   </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+  </ImportGroup>
   <PropertyGroup Label="UserMacros" />
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
@@ -80,10 +107,18 @@
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
     <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
     <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
   </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <OutDir>$(SolutionDir)bin\$(Platform)\$(Configuration)\</OutDir>
+    <IntDir>$(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\</IntDir>
+  </PropertyGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
     <ClCompile>
       <WarningLevel>Level3</WarningLevel>
@@ -104,6 +139,16 @@
       <Command>generate_tables.py instructions</Command>
     </PreBuildEvent>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|ARM64'">
+    <ClCompile>
+      <WarningLevel>Level3</WarningLevel>
+      <Optimization>Disabled</Optimization>
+      <SDLCheck>true</SDLCheck>
+    </ClCompile>
+    <PreBuildEvent>
+      <Command>generate_tables.py instructions</Command>
+    </PreBuildEvent>
+  </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
     <ClCompile>
       <WarningLevel>Level3</WarningLevel>
@@ -136,6 +181,22 @@
       <Command>generate_tables.py instructions</Command>
     </PreBuildEvent>
   </ItemDefinitionGroup>
+  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|ARM64'">
+    <ClCompile>
+      <WarningLevel>Level3</WarningLevel>
+      <Optimization>MaxSpeed</Optimization>
+      <FunctionLevelLinking>true</FunctionLevelLinking>
+      <IntrinsicFunctions>true</IntrinsicFunctions>
+      <SDLCheck>true</SDLCheck>
+    </ClCompile>
+    <Link>
+      <EnableCOMDATFolding>true</EnableCOMDATFolding>
+      <OptimizeReferences>true</OptimizeReferences>
+    </Link>
+    <PreBuildEvent>
+      <Command>generate_tables.py instructions</Command>
+    </PreBuildEvent>
+  </ItemDefinitionGroup>
   <ItemGroup>
     <None Include="disasmlib.py" />
     <None Include="generate_tables.py" />