diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c
index 1e92172..f1dae1e 100644
--- a/bddisasm/bddisasm.c
+++ b/bddisasm/bddisasm.c
@@ -13,6 +13,10 @@
 #define RET_GE(x, y, z)     if ((x) >= (y)) { return (z); }
 #define RET_GT(x, y, z)     if ((x) >  (y)) { return (z); }
 
+#ifndef UNREFERENCED_PARAMETER
+#define UNREFERENCED_PARAMETER(P) ((void)(P))
+#endif
+
 
 static const char *gReg8Bit[] =
 {
@@ -291,7 +295,7 @@ NdGetVersion(
 //
 // Do not use __TIME__ and __DATE__ macros when compiling against a kernel tree.
 //
-#if defined(__KERNEL__) && defined(__GNUC__)
+#if defined(__KERNEL__)
 
     if (NULL != BuildDate)
     {
@@ -319,10 +323,10 @@ NdGetVersion(
 
 }
 
-#ifndef KERNEL_MODE
 //
 // NdSprintf
 //
+#ifndef BDDISASM_NO_FORMAT
 static NDSTATUS
 NdSprintf(
     char *Destination,
@@ -364,12 +368,7 @@ NdSprintf(
 
     return ND_STATUS_SUCCESS;
 }
-#else
-#define NdSprintf(Destination, DestinationSize, Formatstring, ...) RtlStringCbPrintfA(Destination,                  \
-                                                                                      DestinationSize,              \
-                                                                                      Formatstring,                 \
-                                                                                      __VA_ARGS__);
-#endif
+#endif // !BDDISASM_NO_FORMAT
 
 
 //
@@ -1688,13 +1687,17 @@ NdParseOperand(
     case ND_OPS_v2:
     case ND_OPS_v3:
     case ND_OPS_v4:
+    case ND_OPS_v5:
     case ND_OPS_v8:
         // Multiple words accessed.
         {
             static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
             uint8_t scale = 1;
 
-            scale = (ops == ND_OPS_v2) ? 2 : ((ops == ND_OPS_v3) ? 3 : ((ops == ND_OPS_v4) ? 4 : 8));
+            scale = (ops == ND_OPS_v2) ? 2 : 
+                    (ops == ND_OPS_v3) ? 3 : 
+                    (ops == ND_OPS_v4) ? 4 : 
+                    (ops == ND_OPS_v5) ? 5 : 8;
 
             size =  scale * szLut[Instrux->EfOpMode];
         }
@@ -4179,6 +4182,7 @@ NdDecode(
 //
 // NdToText
 //
+#ifndef BDDISASM_NO_FORMAT
 NDSTATUS
 NdToText(
     const INSTRUX *Instrux,
@@ -5030,6 +5034,29 @@ NdToText(
 
    return ND_STATUS_SUCCESS;
 }
+#else
+NDSTATUS
+NdToText(
+    const INSTRUX *Instrux,
+    uint64_t Rip,
+    uint32_t BufferSize,
+    char *Buffer
+    )
+{
+    UNREFERENCED_PARAMETER(Instrux);
+    UNREFERENCED_PARAMETER(Rip);
+
+    // At least make sure the buffer is NULL-terminated so integrators can use NdToText without checking if the
+    // BDDISASM_NO_FORMAT macro is defined. This makes switching between versions with formatting and versions without
+    // formatting easier.
+    if (Buffer != NULL && BufferSize >= 1)
+    {
+        *Buffer = '\0';
+    }
+
+    return ND_STATUS_SUCCESS;
+}
+#endif // !BDDISASM_NO_FORMAT
 
 
 //
diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
index b517715..69b4097 100644
--- a/bddisasm/include/instructions.h
+++ b/bddisasm/include/instructions.h
@@ -5,7 +5,7 @@
 #ifndef INSTRUCTIONS_H
 #define INSTRUCTIONS_H
 
-const ND_INSTRUCTION gInstructions[2585] = 
+const ND_INSTRUCTION gInstructions[2589] = 
 {
     // Pos:0 Instruction:"AAA" Encoding:"0x37"/""
     {
@@ -3981,9 +3981,51 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:239 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
+    // Pos:239 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/""
     {
-        ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 169, 
+        ND_INS_ERETS, ND_CAT_FRED, ND_SET_FRED, 169, 
+        0, 
+        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), 
+        },
+    }, 
+
+    // Pos:240 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/""
+    {
+        ND_INS_ERETU, ND_CAT_FRED, ND_SET_FRED, 170, 
+        0, 
+        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), 
+            OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+        },
+    }, 
+
+    // Pos:241 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
+    {
+        ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 171, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -3998,9 +4040,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:240 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII"
+    // Pos:242 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII"
     {
-        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, 
+        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 172, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -4015,9 +4057,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:241 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
+    // Pos:243 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
     {
-        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, 
+        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 172, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -4031,9 +4073,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:242 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
+    // Pos:244 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
     {
-        ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 171, 
+        ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 173, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4046,9 +4088,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:243 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
+    // Pos:245 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
     {
-        ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 172, 
+        ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 174, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4061,9 +4103,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:244 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
+    // Pos:246 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4078,9 +4120,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:245 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
+    // Pos:247 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4095,9 +4137,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:246 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
+    // Pos:248 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4112,9 +4154,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:247 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
+    // Pos:249 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4129,9 +4171,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:248 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
+    // Pos:250 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
     {
-        ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 174, 
+        ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 176, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4146,9 +4188,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:249 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
+    // Pos:251 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
     {
-        ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
+        ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 177, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4163,9 +4205,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:250 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
+    // Pos:252 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
     {
-        ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 176, 
+        ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 178, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4180,9 +4222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:251 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
+    // Pos:253 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
     {
-        ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 177, 
+        ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 179, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4195,9 +4237,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:252 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
+    // Pos:254 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
     {
-        ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 178, 
+        ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 180, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4213,9 +4255,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:253 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
+    // Pos:255 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
     {
-        ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 181, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4231,9 +4273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:254 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
+    // Pos:256 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
     {
-        ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 180, 
+        ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 182, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4249,9 +4291,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:255 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
+    // Pos:257 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
     {
-        ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 181, 
+        ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 183, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4267,9 +4309,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:256 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
+    // Pos:258 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
     {
-        ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 182, 
+        ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 184, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4285,9 +4327,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:257 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
+    // Pos:259 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
     {
-        ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 183, 
+        ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 185, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4303,9 +4345,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:258 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
+    // Pos:260 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
     {
-        ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 184, 
+        ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 186, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4321,9 +4363,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:259 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
+    // Pos:261 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
     {
-        ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 185, 
+        ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 187, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4339,9 +4381,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:260 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
+    // Pos:262 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4356,9 +4398,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:261 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
+    // Pos:263 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4373,9 +4415,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:262 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
+    // Pos:264 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4390,9 +4432,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:263 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
+    // Pos:265 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4407,9 +4449,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:264 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
+    // Pos:266 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
     {
-        ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 187, 
+        ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4425,9 +4467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:265 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
+    // Pos:267 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
     {
-        ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 188, 
+        ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 190, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4443,9 +4485,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:266 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
+    // Pos:268 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4460,9 +4502,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:267 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
+    // Pos:269 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4477,9 +4519,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:268 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
+    // Pos:270 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4494,9 +4536,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:269 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
+    // Pos:271 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4511,9 +4553,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:270 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
+    // Pos:272 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4528,9 +4570,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:271 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
+    // Pos:273 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
     {
-        ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 190, 
+        ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 192, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4543,9 +4585,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:272 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
+    // Pos:274 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
     {
-        ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 191, 
+        ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 193, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4558,9 +4600,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:273 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
+    // Pos:275 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
     {
-        ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 192, 
+        ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 194, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4573,9 +4615,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:274 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
+    // Pos:276 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4590,9 +4632,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:275 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
+    // Pos:277 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4607,9 +4649,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:276 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
+    // Pos:278 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4624,9 +4666,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:277 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
+    // Pos:279 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4641,9 +4683,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:278 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
+    // Pos:280 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
     {
-        ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 194, 
+        ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 196, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4658,9 +4700,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:279 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
+    // Pos:281 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4675,9 +4717,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:280 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
+    // Pos:282 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4692,9 +4734,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:281 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
+    // Pos:283 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4709,9 +4751,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:282 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
+    // Pos:284 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4726,9 +4768,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:283 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
+    // Pos:285 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
     {
-        ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 196, 
+        ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 198, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4743,9 +4785,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:284 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
+    // Pos:286 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
     {
-        ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 197, 
+        ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 199, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, 
@@ -4758,9 +4800,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:285 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
+    // Pos:287 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
     {
-        ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 198, 
+        ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 200, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4774,9 +4816,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:286 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
+    // Pos:288 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
     {
-        ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 199, 
+        ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 201, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4790,9 +4832,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:287 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
+    // Pos:289 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
     {
-        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, 
+        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 202, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4807,9 +4849,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:288 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
+    // Pos:290 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
     {
-        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, 
+        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 202, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4824,9 +4866,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:289 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
+    // Pos:291 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
     {
-        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, 
+        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 203, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4841,9 +4883,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:290 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
+    // Pos:292 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
     {
-        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, 
+        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 203, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4858,9 +4900,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:291 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
+    // Pos:293 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
     {
-        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, 
+        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 204, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4875,9 +4917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:292 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
+    // Pos:294 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
     {
-        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, 
+        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 204, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4892,9 +4934,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:293 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
+    // Pos:295 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
     {
-        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 205, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4909,9 +4951,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:294 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
+    // Pos:296 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
     {
-        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 205, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4926,9 +4968,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:295 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
+    // Pos:297 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
     {
-        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, 
+        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 206, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4943,9 +4985,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:296 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
+    // Pos:298 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
     {
-        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, 
+        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 206, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4960,9 +5002,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:297 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
+    // Pos:299 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4977,9 +5019,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:298 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
+    // Pos:300 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4994,9 +5036,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:299 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
+    // Pos:301 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5011,9 +5053,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:300 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
+    // Pos:302 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
     {
-        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, 
+        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 208, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5028,9 +5070,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:301 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
+    // Pos:303 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
     {
-        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, 
+        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 208, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5045,9 +5087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:302 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
+    // Pos:304 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
     {
-        ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 207, 
+        ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5060,9 +5102,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:303 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
+    // Pos:305 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
     {
-        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, 
+        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 210, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5077,9 +5119,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:304 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
+    // Pos:306 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
     {
-        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, 
+        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 210, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5094,9 +5136,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:305 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
+    // Pos:307 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5111,9 +5153,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:306 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
+    // Pos:308 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5128,9 +5170,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:307 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
+    // Pos:309 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5145,9 +5187,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:308 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
+    // Pos:310 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5162,9 +5204,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:309 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
+    // Pos:311 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5179,9 +5221,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:310 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
+    // Pos:312 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5196,9 +5238,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:311 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
+    // Pos:313 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
     {
-        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, 
+        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5213,9 +5255,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:312 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
+    // Pos:314 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
     {
-        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, 
+        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5230,9 +5272,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:313 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
+    // Pos:315 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
     {
-        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, 
+        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 214, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5247,9 +5289,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:314 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
+    // Pos:316 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
     {
-        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, 
+        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 214, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5264,9 +5306,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:315 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
+    // Pos:317 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5281,9 +5323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:316 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
+    // Pos:318 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5298,9 +5340,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:317 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
+    // Pos:319 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5315,9 +5357,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:318 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
+    // Pos:320 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5332,9 +5374,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:319 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
+    // Pos:321 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
     {
-        ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 214, 
+        ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 216, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5347,9 +5389,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:320 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
+    // Pos:322 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
     {
-        ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 215, 
+        ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 217, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5364,9 +5406,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:321 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
+    // Pos:323 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
     {
-        ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 216, 
+        ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 218, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5380,9 +5422,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:322 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
+    // Pos:324 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
     {
-        ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 217, 
+        ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 219, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5395,9 +5437,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:323 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
+    // Pos:325 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
     {
-        ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 218, 
+        ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 220, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5410,9 +5452,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:324 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
+    // Pos:326 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
     {
-        ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 219, 
+        ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 221, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5425,9 +5467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:325 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
+    // Pos:327 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
     {
-        ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 220, 
+        ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 222, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5440,9 +5482,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:326 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
+    // Pos:328 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
     {
-        ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 221, 
+        ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 223, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5455,9 +5497,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:327 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
+    // Pos:329 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
     {
-        ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 222, 
+        ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 224, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5470,9 +5512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:328 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
+    // Pos:330 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5487,9 +5529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:329 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
+    // Pos:331 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5504,9 +5546,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:330 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
+    // Pos:332 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5521,9 +5563,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:331 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
+    // Pos:333 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5538,9 +5580,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:332 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
+    // Pos:334 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
     {
-        ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 224, 
+        ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 226, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5555,9 +5597,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:333 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
+    // Pos:335 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
     {
-        ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 225, 
+        ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 227, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5570,9 +5612,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:334 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
+    // Pos:336 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
     {
-        ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 226, 
+        ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 228, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5585,9 +5627,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:335 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
+    // Pos:337 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
     {
-        ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 227, 
+        ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 229, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5602,9 +5644,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:336 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
+    // Pos:338 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5617,9 +5659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:337 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
+    // Pos:339 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5632,9 +5674,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:338 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
+    // Pos:340 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5647,9 +5689,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:339 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
+    // Pos:341 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
     {
-        ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 229, 
+        ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 231, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5665,9 +5707,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:340 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
+    // Pos:342 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
     {
-        ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 230, 
+        ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 232, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5682,9 +5724,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:341 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
+    // Pos:343 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
     {
-        ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 231, 
+        ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 233, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5698,9 +5740,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:342 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
+    // Pos:344 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
     {
-        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, 
+        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 234, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5714,9 +5756,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:343 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
+    // Pos:345 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
     {
-        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, 
+        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 234, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5730,9 +5772,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:344 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
+    // Pos:346 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
     {
-        ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 233, 
+        ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 235, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5745,9 +5787,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:345 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
+    // Pos:347 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
     {
-        ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 234, 
+        ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 236, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5760,9 +5802,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:346 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
+    // Pos:348 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
     {
-        ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 235, 
+        ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 237, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5775,9 +5817,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:347 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
+    // Pos:349 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
     {
-        ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 238, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5790,9 +5832,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:348 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
+    // Pos:350 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
     {
-        ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 237, 
+        ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 239, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5805,9 +5847,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:349 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
+    // Pos:351 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
     {
-        ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 238, 
+        ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 240, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5820,9 +5862,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:350 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
+    // Pos:352 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
     {
-        ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 239, 
+        ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 241, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5836,9 +5878,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:351 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
+    // Pos:353 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
     {
-        ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 240, 
+        ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 242, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5851,9 +5893,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:352 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
+    // Pos:354 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
     {
-        ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 241, 
+        ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 243, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5866,9 +5908,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:353 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
+    // Pos:355 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
     {
-        ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 242, 
+        ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 244, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5881,9 +5923,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:354 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
+    // Pos:356 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
     {
-        ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 243, 
+        ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 245, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5896,9 +5938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:355 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
+    // Pos:357 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5913,9 +5955,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:356 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
+    // Pos:358 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5930,9 +5972,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:357 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
+    // Pos:359 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5947,9 +5989,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:358 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
+    // Pos:360 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
     {
-        ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 245, 
+        ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -5962,9 +6004,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:359 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
+    // Pos:361 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5979,9 +6021,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:360 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
+    // Pos:362 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5996,9 +6038,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:361 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
+    // Pos:363 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6013,9 +6055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:362 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
+    // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6030,9 +6072,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:363 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
+    // Pos:365 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6047,9 +6089,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
+    // Pos:366 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6064,9 +6106,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:365 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
+    // Pos:367 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
     {
-        ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 247, 
+        ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 249, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6081,9 +6123,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:366 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
+    // Pos:368 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
     {
-        ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 248, 
+        ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 250, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6096,9 +6138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:367 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
+    // Pos:369 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6113,9 +6155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:368 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
+    // Pos:370 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6130,9 +6172,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:369 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
+    // Pos:371 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6147,9 +6189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:370 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
+    // Pos:372 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6164,9 +6206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:371 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
+    // Pos:373 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
     {
-        ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 250, 
+        ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 252, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6181,9 +6223,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:372 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
+    // Pos:374 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6198,9 +6240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:373 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
+    // Pos:375 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6215,9 +6257,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:374 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
+    // Pos:376 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6232,9 +6274,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:375 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
+    // Pos:377 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6249,9 +6291,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:376 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
+    // Pos:378 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
     {
-        ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 252, 
+        ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 254, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6266,9 +6308,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:377 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
+    // Pos:379 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
     {
-        ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 253, 
+        ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 255, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6281,9 +6323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:378 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
+    // Pos:380 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
     {
-        ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 254, 
+        ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 256, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6298,9 +6340,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:379 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
+    // Pos:381 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
     {
-        ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 255, 
+        ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 257, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6316,9 +6358,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:380 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
+    // Pos:382 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
     {
-        ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 256, 
+        ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 258, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6334,9 +6376,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:381 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
+    // Pos:383 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
     {
-        ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 257, 
+        ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 259, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6351,9 +6393,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:382 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
+    // Pos:384 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
     {
-        ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 258, 
+        ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 260, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6366,9 +6408,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:383 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
+    // Pos:385 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
     {
-        ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 259, 
+        ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 261, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6381,9 +6423,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:384 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
+    // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6398,9 +6440,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:385 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
+    // Pos:387 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6415,9 +6457,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
+    // Pos:388 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6432,9 +6474,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:387 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
+    // Pos:389 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
     {
-        ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 261, 
+        ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 263, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6448,9 +6490,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:388 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
+    // Pos:390 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
     {
-        ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 262, 
+        ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 264, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6464,9 +6506,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:389 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
+    // Pos:391 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
     {
-        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 263, 
+        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 265, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6480,9 +6522,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:390 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
+    // Pos:392 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
     {
-        ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 264, 
+        ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 266, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6496,9 +6538,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:391 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
+    // Pos:393 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
     {
-        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 265, 
+        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 267, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6511,9 +6553,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:392 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
+    // Pos:394 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
     {
-        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 266, 
+        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 268, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6526,9 +6568,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:393 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
+    // Pos:395 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
     {
-        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 267, 
+        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 269, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6541,9 +6583,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:394 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
+    // Pos:396 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
     {
-        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 268, 
+        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 270, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, 
@@ -6557,9 +6599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:395 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
+    // Pos:397 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 269, 
+        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 271, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6574,9 +6616,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:396 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
+    // Pos:398 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 270, 
+        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 272, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6591,9 +6633,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:397 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
+    // Pos:399 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
     {
-        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 271, 
+        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 273, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6607,9 +6649,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:398 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
+    // Pos:400 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 272, 
+        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 274, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6623,9 +6665,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:399 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
+    // Pos:401 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 273, 
+        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 275, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6639,9 +6681,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:400 Instruction:"HLT" Encoding:"0xF4"/""
+    // Pos:402 Instruction:"HLT" Encoding:"0xF4"/""
     {
-        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 274, 
+        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 276, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6654,9 +6696,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:401 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I"
+    // Pos:403 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I"
     {
-        ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 275, 
+        ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 277, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_HRESET, 
@@ -6670,9 +6712,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:402 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
+    // Pos:404 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 276, 
+        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6686,9 +6728,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:403 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
+    // Pos:405 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 277, 
+        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 279, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6702,9 +6744,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:404 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
+    // Pos:406 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 278, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6721,9 +6763,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:405 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
+    // Pos:407 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 278, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6739,9 +6781,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:406 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
+    // Pos:408 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 279, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6756,9 +6798,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:407 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
+    // Pos:409 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 279, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6774,9 +6816,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:408 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
+    // Pos:410 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 279, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6792,9 +6834,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:409 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
+    // Pos:411 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 279, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6810,9 +6852,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:410 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
+    // Pos:412 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 279, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6828,9 +6870,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:411 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
+    // Pos:413 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 280, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6845,9 +6887,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:412 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
+    // Pos:414 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 280, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6862,9 +6904,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:413 Instruction:"IN AL,DX" Encoding:"0xEC"/""
+    // Pos:415 Instruction:"IN AL,DX" Encoding:"0xEC"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 280, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6879,9 +6921,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:414 Instruction:"IN eAX,DX" Encoding:"0xED"/""
+    // Pos:416 Instruction:"IN eAX,DX" Encoding:"0xED"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 280, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6896,9 +6938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:415 Instruction:"INC Zv" Encoding:"0x40"/"O"
+    // Pos:417 Instruction:"INC Zv" Encoding:"0x40"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6912,9 +6954,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:416 Instruction:"INC Zv" Encoding:"0x41"/"O"
+    // Pos:418 Instruction:"INC Zv" Encoding:"0x41"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6928,9 +6970,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:417 Instruction:"INC Zv" Encoding:"0x42"/"O"
+    // Pos:419 Instruction:"INC Zv" Encoding:"0x42"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6944,9 +6986,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:418 Instruction:"INC Zv" Encoding:"0x43"/"O"
+    // Pos:420 Instruction:"INC Zv" Encoding:"0x43"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6960,9 +7002,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:419 Instruction:"INC Zv" Encoding:"0x44"/"O"
+    // Pos:421 Instruction:"INC Zv" Encoding:"0x44"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6976,9 +7018,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:420 Instruction:"INC Zv" Encoding:"0x45"/"O"
+    // Pos:422 Instruction:"INC Zv" Encoding:"0x45"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6992,9 +7034,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:421 Instruction:"INC Zv" Encoding:"0x46"/"O"
+    // Pos:423 Instruction:"INC Zv" Encoding:"0x46"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7008,9 +7050,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:422 Instruction:"INC Zv" Encoding:"0x47"/"O"
+    // Pos:424 Instruction:"INC Zv" Encoding:"0x47"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7024,9 +7066,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:423 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
+    // Pos:425 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -7040,9 +7082,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:424 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
+    // Pos:426 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 281, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -7056,9 +7098,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:425 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
+    // Pos:427 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 282, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 284, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -7073,9 +7115,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:426 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
+    // Pos:428 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 283, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 285, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -7090,9 +7132,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:427 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
+    // Pos:429 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7108,9 +7150,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:428 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
+    // Pos:430 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7127,9 +7169,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:429 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
+    // Pos:431 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 285, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7145,9 +7187,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:430 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
+    // Pos:432 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 285, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7164,9 +7206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:431 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
+    // Pos:433 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 286, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 288, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -7181,9 +7223,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:432 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
+    // Pos:434 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 286, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 288, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -7198,9 +7240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:433 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
+    // Pos:435 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 287, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 289, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -7216,9 +7258,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:434 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
+    // Pos:436 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 287, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 289, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -7232,9 +7274,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:435 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
+    // Pos:437 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 288, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 290, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7250,9 +7292,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:436 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
+    // Pos:438 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 288, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 290, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7269,9 +7311,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:437 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
+    // Pos:439 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
     {
-        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 289, 
+        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7289,9 +7331,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:438 Instruction:"INT1" Encoding:"0xF1"/""
+    // Pos:440 Instruction:"INT1" Encoding:"0xF1"/""
     {
-        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 290, 
+        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 292, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7307,9 +7349,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:439 Instruction:"INT3" Encoding:"0xCC"/""
+    // Pos:441 Instruction:"INT3" Encoding:"0xCC"/""
     {
-        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 291, 
+        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7326,9 +7368,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:440 Instruction:"INTO" Encoding:"0xCE"/""
+    // Pos:442 Instruction:"INTO" Encoding:"0xCE"/""
     {
-        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 292, 
+        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7345,9 +7387,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:441 Instruction:"INVD" Encoding:"0x0F 0x08"/""
+    // Pos:443 Instruction:"INVD" Encoding:"0x0F 0x08"/""
     {
-        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 293, 
+        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 295, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -7360,9 +7402,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:442 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
+    // Pos:444 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
     {
-        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 294, 
+        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 296, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -7377,9 +7419,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:443 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
+    // Pos:445 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
     {
-        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 295, 
+        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 297, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
@@ -7392,9 +7434,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:444 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
+    // Pos:446 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
     {
-        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 296, 
+        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 298, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -7408,9 +7450,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:445 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
+    // Pos:447 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
     {
-        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 297, 
+        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 299, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
@@ -7425,9 +7467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:446 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
+    // Pos:448 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
     {
-        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 298, 
+        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 300, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, 
@@ -7441,9 +7483,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:447 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
+    // Pos:449 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
     {
-        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 299, 
+        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 301, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -7458,45 +7500,7 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:448 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
-    {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 300, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-        },
-    }, 
-
-    // Pos:449 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
-    {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 301, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-        },
-    }, 
-
-    // Pos:450 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
+    // Pos:450 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
     {
         ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 302, 
         0, 
@@ -7515,9 +7519,47 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:451 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
+    // Pos:451 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 303, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+        },
+    }, 
+
+    // Pos:452 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
+    {
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 304, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+        },
+    }, 
+
+    // Pos:453 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
+    {
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7532,9 +7574,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:452 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
+    // Pos:454 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7549,9 +7591,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:453 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
+    // Pos:455 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7566,9 +7608,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:454 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
+    // Pos:456 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7583,9 +7625,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:455 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
+    // Pos:457 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 305, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 307, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7600,9 +7642,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:456 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
+    // Pos:458 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 306, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 308, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7617,9 +7659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:457 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
+    // Pos:459 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7634,9 +7676,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:458 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
+    // Pos:460 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7651,9 +7693,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:459 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
+    // Pos:461 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7668,9 +7710,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:460 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
+    // Pos:462 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7685,9 +7727,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:461 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
+    // Pos:463 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 309, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 311, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7701,9 +7743,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:462 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
+    // Pos:464 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 309, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 311, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7717,9 +7759,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:463 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
+    // Pos:465 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
     {
-        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 309, 
+        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 311, 
         ND_PREF_BND|ND_PREF_DNT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -7733,9 +7775,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:464 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M"
+    // Pos:466 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M"
     {
-        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 310, 
+        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -7749,9 +7791,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:465 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
+    // Pos:467 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
     {
-        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 310, 
+        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7765,9 +7807,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:466 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
+    // Pos:468 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
     {
-        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 311, 
+        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7782,9 +7824,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:467 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
+    // Pos:469 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
     {
-        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 311, 
+        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -7799,9 +7841,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:468 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
+    // Pos:470 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7816,9 +7858,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:469 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
+    // Pos:471 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7833,9 +7875,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:470 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
+    // Pos:472 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7850,9 +7892,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:471 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
+    // Pos:473 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7867,9 +7909,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:472 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
+    // Pos:474 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7884,9 +7926,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:473 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
+    // Pos:475 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7901,9 +7943,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:474 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
+    // Pos:476 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7918,9 +7960,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:475 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
+    // Pos:477 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7935,80 +7977,80 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:476 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
-    {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
-        ND_PREF_BND|ND_PREF_BHINT, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
-        0|NDR_RFLAG_OF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:477 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
-    {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
-        ND_PREF_BND|ND_PREF_BHINT, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
-        0|NDR_RFLAG_OF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:478 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
-    {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
-        ND_PREF_BND|ND_PREF_BHINT, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
-        0|NDR_RFLAG_PF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:479 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
-    {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
-        ND_PREF_BND|ND_PREF_BHINT, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
-        0|NDR_RFLAG_PF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:480 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
+    // Pos:478 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
     {
         ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
+        0|NDR_RFLAG_OF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:479 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
+    {
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, 
+        ND_PREF_BND|ND_PREF_BHINT, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
+        0|NDR_RFLAG_OF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:480 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
+    {
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
+        ND_PREF_BND|ND_PREF_BHINT, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
+        0|NDR_RFLAG_PF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:481 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
+    {
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
+        ND_PREF_BND|ND_PREF_BHINT, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
+        0|NDR_RFLAG_PF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:482 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
+    {
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
+        ND_PREF_BND|ND_PREF_BHINT, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|NDR_RFLAG_SF,
         0,
         0,
@@ -8020,9 +8062,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:481 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
+    // Pos:483 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8037,9 +8079,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:482 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
+    // Pos:484 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8054,9 +8096,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:483 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
+    // Pos:485 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8071,9 +8113,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:484 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
+    // Pos:486 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8088,9 +8130,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:485 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
+    // Pos:487 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8105,9 +8147,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:486 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
+    // Pos:488 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8122,9 +8164,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:487 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
+    // Pos:489 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8139,9 +8181,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:488 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
+    // Pos:490 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 322, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 324, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -8156,9 +8198,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:489 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
+    // Pos:491 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8173,9 +8215,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:490 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
+    // Pos:492 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8190,9 +8232,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:491 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
+    // Pos:493 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 324, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8207,9 +8249,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:492 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
+    // Pos:494 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 324, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8224,9 +8266,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:493 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:495 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 325, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8241,9 +8283,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:494 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:496 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 326, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8258,9 +8300,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:495 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:497 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8275,9 +8317,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:496 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:498 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8292,9 +8334,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:497 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:499 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 329, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 331, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8309,9 +8351,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:498 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:500 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8326,9 +8368,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:499 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:501 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 331, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8343,9 +8385,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:500 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:502 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 332, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8360,9 +8402,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:501 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:503 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 333, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8377,9 +8419,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:502 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:504 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 334, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8394,9 +8436,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:503 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:505 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 335, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8411,9 +8453,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:504 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:506 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 336, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8428,9 +8470,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:505 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
+    // Pos:507 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 337, 
+        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -8444,9 +8486,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:506 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
+    // Pos:508 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 338, 
+        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -8460,9 +8502,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:507 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:509 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8476,9 +8518,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:508 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:510 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8492,9 +8534,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:509 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:511 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8508,9 +8550,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:510 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:512 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8524,9 +8566,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:511 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:513 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8540,9 +8582,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:512 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:514 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8556,9 +8598,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:513 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:515 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8572,9 +8614,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:514 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:516 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8588,9 +8630,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:515 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:517 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8604,9 +8646,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:516 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:518 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8620,9 +8662,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:517 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:519 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8636,9 +8678,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:518 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:520 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8652,9 +8694,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:519 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:521 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8668,9 +8710,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:520 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
+    // Pos:522 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8684,9 +8726,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:521 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
+    // Pos:523 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8700,9 +8742,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:522 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:524 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8716,9 +8758,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:523 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:525 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8732,9 +8774,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:524 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:526 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8748,9 +8790,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:525 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:527 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8764,9 +8806,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:526 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:528 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8780,9 +8822,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:527 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:529 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 343, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8796,9 +8838,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:528 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:530 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 344, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8812,9 +8854,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:529 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:531 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 345, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8828,9 +8870,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:530 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:532 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 346, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8844,9 +8886,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:531 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:533 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 347, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8861,9 +8903,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:532 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:534 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8878,9 +8920,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:533 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:535 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8895,9 +8937,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:534 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:536 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8912,9 +8954,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:535 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:537 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8929,9 +8971,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:536 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:538 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 352, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8946,9 +8988,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:537 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:539 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 353, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8963,9 +9005,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:538 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:540 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 354, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8980,9 +9022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:539 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
+    // Pos:541 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 355, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 357, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8997,9 +9039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:540 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
+    // Pos:542 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 356, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9014,9 +9056,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:541 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
+    // Pos:543 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 359, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9031,9 +9073,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:542 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
+    // Pos:544 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 358, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9048,9 +9090,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:543 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
+    // Pos:545 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 359, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9065,9 +9107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:544 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
+    // Pos:546 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9082,9 +9124,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:545 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
+    // Pos:547 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 361, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9099,9 +9141,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:546 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
+    // Pos:548 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 362, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9116,9 +9158,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:547 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:549 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 363, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9132,9 +9174,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:548 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:550 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 364, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9148,9 +9190,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:549 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:551 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 365, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9164,9 +9206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:550 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:552 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 366, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9180,9 +9222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:551 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:553 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 367, 
+        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 369, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9197,9 +9239,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:552 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
+    // Pos:554 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 368, 
+        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9214,9 +9256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:553 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:555 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 369, 
+        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9231,9 +9273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:554 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:556 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 370, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9248,9 +9290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:555 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:557 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9265,9 +9307,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:556 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:558 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 372, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9282,9 +9324,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:557 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:559 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 373, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 375, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9299,9 +9341,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:558 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:560 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 374, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 376, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9316,9 +9358,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:559 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:561 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 375, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9333,9 +9375,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:560 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:562 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 376, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9350,9 +9392,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:561 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:563 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 377, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9367,9 +9409,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:562 Instruction:"LAHF" Encoding:"0x9F"/""
+    // Pos:564 Instruction:"LAHF" Encoding:"0x9F"/""
     {
-        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 378, 
+        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 380, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9383,9 +9425,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:563 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
+    // Pos:565 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 379, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9400,9 +9442,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:564 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
+    // Pos:566 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 379, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9417,9 +9459,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:565 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
+    // Pos:567 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
     {
-        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 380, 
+        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 382, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -9433,9 +9475,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:566 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
+    // Pos:568 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
     {
-        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 381, 
+        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 383, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -9449,9 +9491,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:567 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
+    // Pos:569 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
     {
-        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 382, 
+        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 384, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -9466,9 +9508,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:568 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:570 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 383, 
+        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -9481,9 +9523,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:569 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
+    // Pos:571 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
     {
-        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 384, 
+        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 386, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
@@ -9497,9 +9539,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:570 Instruction:"LEAVE" Encoding:"0xC9"/""
+    // Pos:572 Instruction:"LEAVE" Encoding:"0xC9"/""
     {
-        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 385, 
+        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 387, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -9515,9 +9557,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:571 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
+    // Pos:573 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
     {
-        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 386, 
+        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 388, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -9532,9 +9574,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:572 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
+    // Pos:574 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
     {
-        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 387, 
+        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 389, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -9547,9 +9589,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:573 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
+    // Pos:575 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
     {
-        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 388, 
+        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9564,9 +9606,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:574 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
+    // Pos:576 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
     {
-        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 389, 
+        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 391, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9580,9 +9622,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:575 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
+    // Pos:577 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
     {
-        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 390, 
+        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 392, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9597,9 +9639,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:576 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
+    // Pos:578 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
     {
-        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 391, 
+        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 393, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9613,9 +9655,41 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:577 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
+    // Pos:579 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M"
     {
-        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 392, 
+        ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 394, 
+        0, 
+        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:580 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M"
+    {
+        ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 394, 
+        0, 
+        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:581 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
+    {
+        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 395, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9629,9 +9703,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:578 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
+    // Pos:582 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
     {
-        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 393, 
+        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 396, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9644,9 +9718,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:579 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
+    // Pos:583 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
     {
-        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 394, 
+        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 397, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9660,9 +9734,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:580 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM"
+    // Pos:584 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM"
     {
-        ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 395, 
+        ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 398, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
@@ -9679,9 +9753,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:581 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
+    // Pos:585 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9697,9 +9771,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:582 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
+    // Pos:586 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9716,9 +9790,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:583 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
+    // Pos:587 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9734,9 +9808,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:584 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
+    // Pos:588 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9753,9 +9827,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:585 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
+    // Pos:589 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 401, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9771,9 +9845,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:586 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
+    // Pos:590 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 401, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9790,9 +9864,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:587 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
+    // Pos:591 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 402, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9808,9 +9882,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:588 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
+    // Pos:592 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 402, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9827,9 +9901,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:589 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
+    // Pos:593 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
     {
-        ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 400, 
+        ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 403, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9845,9 +9919,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:590 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
+    // Pos:594 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
     {
-        ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 401, 
+        ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 404, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9863,9 +9937,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:591 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
+    // Pos:595 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
     {
-        ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 402, 
+        ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 405, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9881,9 +9955,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:592 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
+    // Pos:596 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
     {
-        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 403, 
+        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9898,9 +9972,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:593 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
+    // Pos:597 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
     {
-        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 403, 
+        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9915,9 +9989,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:594 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
+    // Pos:598 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
     {
-        ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 404, 
+        ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9932,9 +10006,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:595 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
+    // Pos:599 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
     {
-        ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 405, 
+        ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 408, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9948,9 +10022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:596 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
+    // Pos:600 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
     {
-        ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 406, 
+        ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9965,9 +10039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:597 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
+    // Pos:601 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
     {
-        ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 407, 
+        ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9982,9 +10056,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:598 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM"
+    // Pos:602 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM"
     {
-        ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 408, 
+        ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 411, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, 
@@ -9999,9 +10073,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:599 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
+    // Pos:603 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
     {
-        ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 409, 
+        ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 412, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10016,9 +10090,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:600 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
+    // Pos:604 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
     {
-        ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 410, 
+        ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 413, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -10033,9 +10107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:601 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
+    // Pos:605 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 411, 
+        ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 414, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10049,9 +10123,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:602 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
+    // Pos:606 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 412, 
+        ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 415, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10065,9 +10139,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:603 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
+    // Pos:607 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 413, 
+        ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 416, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10081,9 +10155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:604 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
+    // Pos:608 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 414, 
+        ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 417, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10097,9 +10171,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:605 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
+    // Pos:609 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
     {
-        ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 415, 
+        ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 418, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, 
@@ -10112,9 +10186,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:606 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
+    // Pos:610 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
     {
-        ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 416, 
+        ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 419, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -10127,9 +10201,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:607 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
+    // Pos:611 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 417, 
+        ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 420, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10143,9 +10217,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:608 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
+    // Pos:612 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 418, 
+        ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 421, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10159,9 +10233,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:609 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
+    // Pos:613 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 419, 
+        ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 422, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10175,9 +10249,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:610 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
+    // Pos:614 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 420, 
+        ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10191,9 +10265,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:611 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
+    // Pos:615 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
     {
-        ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 421, 
+        ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 424, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 
@@ -10208,9 +10282,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:612 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
+    // Pos:616 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
     {
-        ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 422, 
+        ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 425, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10225,9 +10299,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:613 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/""
+    // Pos:617 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/""
     {
-        ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 423, 
+        ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 426, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10240,9 +10314,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:614 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
+    // Pos:618 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
     {
-        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10256,9 +10330,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:615 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
+    // Pos:619 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
     {
-        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10272,9 +10346,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:616 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
+    // Pos:620 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
     {
-        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -10288,9 +10362,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:617 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
+    // Pos:621 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
     {
-        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -10304,9 +10378,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:618 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
+    // Pos:622 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
     {
-        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -10320,9 +10394,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:619 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
+    // Pos:623 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
     {
-        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -10336,9 +10410,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:620 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
+    // Pos:624 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10352,9 +10426,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:621 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
+    // Pos:625 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10368,9 +10442,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:622 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
+    // Pos:626 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10384,9 +10458,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:623 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
+    // Pos:627 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10400,9 +10474,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:624 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
+    // Pos:628 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10416,9 +10490,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:625 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
+    // Pos:629 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10432,9 +10506,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:626 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
+    // Pos:630 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10448,9 +10522,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:627 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
+    // Pos:631 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10464,9 +10538,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:628 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
+    // Pos:632 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10480,9 +10554,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:629 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
+    // Pos:633 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10496,9 +10570,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:630 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
+    // Pos:634 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10512,9 +10586,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:631 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
+    // Pos:635 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10528,9 +10602,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:632 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
+    // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10544,9 +10618,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:633 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
+    // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10560,9 +10634,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:634 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
+    // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10576,9 +10650,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:635 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
+    // Pos:639 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10592,9 +10666,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
+    // Pos:640 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10608,9 +10682,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
+    // Pos:641 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10624,9 +10698,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
+    // Pos:642 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10640,9 +10714,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:639 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
+    // Pos:643 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10656,9 +10730,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:640 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
+    // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10672,9 +10746,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:641 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
+    // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10688,9 +10762,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:642 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
+    // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10704,9 +10778,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:643 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
+    // Pos:647 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10720,9 +10794,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
+    // Pos:648 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10736,9 +10810,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
+    // Pos:649 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10752,9 +10826,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
+    // Pos:650 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10768,9 +10842,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:647 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
+    // Pos:651 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10784,9 +10858,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:648 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
+    // Pos:652 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10800,9 +10874,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:649 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
+    // Pos:653 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 424, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10816,9 +10890,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:650 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
+    // Pos:654 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
     {
-        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 425, 
+        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10832,9 +10906,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:651 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
+    // Pos:655 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
     {
-        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 425, 
+        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10848,9 +10922,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:652 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
+    // Pos:656 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
     {
-        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 426, 
+        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10864,9 +10938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:653 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
+    // Pos:657 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
     {
-        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 426, 
+        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10880,9 +10954,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:654 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM"
+    // Pos:658 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 427, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10896,9 +10970,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:655 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
+    // Pos:659 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 427, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10912,9 +10986,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:656 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR"
+    // Pos:660 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 427, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10928,9 +11002,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:657 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
+    // Pos:661 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 427, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10944,9 +11018,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:658 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
+    // Pos:662 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 428, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 431, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -10960,9 +11034,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:659 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
+    // Pos:663 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 431, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10976,9 +11050,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:660 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
+    // Pos:664 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 428, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 431, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -10992,9 +11066,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:661 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
+    // Pos:665 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 431, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11008,9 +11082,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:662 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
+    // Pos:666 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 429, 
+        ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 432, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -11024,9 +11098,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:663 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
+    // Pos:667 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
     {
-        ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 430, 
+        ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 433, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, 
@@ -11040,9 +11114,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:664 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
+    // Pos:668 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
     {
-        ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 431, 
+        ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 434, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, 
@@ -11056,9 +11130,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:665 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
+    // Pos:669 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
     {
-        ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 
+        ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 435, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11072,9 +11146,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:666 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
+    // Pos:670 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
+        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 436, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11088,9 +11162,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:667 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
+    // Pos:671 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
+        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 436, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11104,9 +11178,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:668 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
+    // Pos:672 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 
+        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 437, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11120,9 +11194,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:669 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
+    // Pos:673 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 
+        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 437, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11136,9 +11210,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:670 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
+    // Pos:674 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 435, 
+        ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 438, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11152,9 +11226,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:671 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
+    // Pos:675 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 436, 
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11168,9 +11242,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:672 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
+    // Pos:676 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 436, 
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11184,9 +11258,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:673 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
+    // Pos:677 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 437, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 440, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11200,9 +11274,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:674 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
+    // Pos:678 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 437, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 440, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11216,9 +11290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:675 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
+    // Pos:679 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
     {
-        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 438, 
+        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 441, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11232,9 +11306,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:676 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
+    // Pos:680 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11248,9 +11322,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:677 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
+    // Pos:681 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11264,9 +11338,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:678 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
+    // Pos:682 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 440, 
+        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 443, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11280,9 +11354,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:679 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
+    // Pos:683 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, 
+        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 444, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11296,9 +11370,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:680 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
+    // Pos:684 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 442, 
+        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 445, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11312,9 +11386,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:681 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
+    // Pos:685 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 443, 
+        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 446, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11328,9 +11402,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:682 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
+    // Pos:686 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
     {
-        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 444, 
+        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 447, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -11344,9 +11418,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:683 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
+    // Pos:687 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
     {
-        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 445, 
+        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 448, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -11360,9 +11434,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:684 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
+    // Pos:688 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 446, 
+        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11376,9 +11450,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:685 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
+    // Pos:689 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 447, 
+        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11392,9 +11466,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:686 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
+    // Pos:690 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 448, 
+        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 451, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11408,9 +11482,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:687 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
+    // Pos:691 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 449, 
+        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 452, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -11424,9 +11498,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:688 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
+    // Pos:692 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 450, 
+        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 453, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -11440,9 +11514,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:689 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
+    // Pos:693 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -11456,9 +11530,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:690 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
+    // Pos:694 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11472,9 +11546,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:691 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
+    // Pos:695 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11488,9 +11562,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:692 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
+    // Pos:696 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11504,9 +11578,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:693 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
+    // Pos:697 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11520,9 +11594,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:694 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
+    // Pos:698 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11536,9 +11610,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:695 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
+    // Pos:699 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11552,9 +11626,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:696 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
+    // Pos:700 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11568,9 +11642,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:697 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
+    // Pos:701 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
     {
-        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 
+        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 455, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11584,9 +11658,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:698 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
+    // Pos:702 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11603,9 +11677,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:699 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
+    // Pos:703 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11623,9 +11697,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:700 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
+    // Pos:704 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11639,9 +11713,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:701 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
+    // Pos:705 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 454, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11655,78 +11729,7 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:702 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
-    {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 454, 
-        ND_PREF_REP, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
-        0|NDR_RFLAG_DF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:703 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
-    {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 454, 
-        ND_PREF_REP, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
-        0|NDR_RFLAG_DF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), 
-            OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), 
-            OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
-            OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
-            OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
-        },
-    }, 
-
-    // Pos:704 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
-    {
-        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 455, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:705 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
-    {
-        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 456, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:706 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
+    // Pos:706 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
     {
         ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 457, 
         ND_PREF_REP, 
@@ -11745,7 +11748,7 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:707 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
+    // Pos:707 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
     {
         ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 457, 
         ND_PREF_REP, 
@@ -11765,9 +11768,80 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:708 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
+    // Pos:708 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 458, 
+        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 458, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:709 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
+    {
+        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 459, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:710 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
+    {
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, 
+        ND_PREF_REP, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
+        0|NDR_RFLAG_DF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:711 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
+    {
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, 
+        ND_PREF_REP, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
+        0|NDR_RFLAG_DF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), 
+            OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), 
+            OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
+            OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
+            OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+        },
+    }, 
+
+    // Pos:712 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
+    {
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 461, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11781,9 +11855,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:709 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
+    // Pos:713 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 458, 
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 461, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11797,9 +11871,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:710 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
+    // Pos:714 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 459, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 462, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11816,9 +11890,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:711 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
+    // Pos:715 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 459, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 462, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11836,9 +11910,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:712 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
+    // Pos:716 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 460, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 463, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11852,9 +11926,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:713 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
+    // Pos:717 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 460, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 463, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11868,9 +11942,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:714 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM"
+    // Pos:718 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM"
     {
-        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 461, 
+        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 464, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -11884,9 +11958,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:715 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
+    // Pos:719 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 465, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11900,9 +11974,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:716 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
+    // Pos:720 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 465, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11916,9 +11990,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:717 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
+    // Pos:721 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 463, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 466, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11932,9 +12006,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:718 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
+    // Pos:722 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 463, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 466, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11948,9 +12022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:719 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
+    // Pos:723 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 464, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 467, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11964,9 +12038,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:720 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
+    // Pos:724 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 464, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 467, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11980,9 +12054,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:721 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
+    // Pos:725 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
     {
-        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 465, 
+        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 468, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -11997,9 +12071,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:722 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
+    // Pos:726 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 466, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 469, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12015,9 +12089,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:723 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
+    // Pos:727 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 466, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 469, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12033,9 +12107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:724 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
+    // Pos:728 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 467, 
+        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 470, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -12049,9 +12123,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:725 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
+    // Pos:729 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 468, 
+        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 471, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -12065,9 +12139,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:726 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
+    // Pos:730 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 469, 
+        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 472, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -12081,9 +12155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:727 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
+    // Pos:731 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 470, 
+        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 473, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -12097,9 +12171,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:728 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
+    // Pos:732 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
     {
-        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 471, 
+        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -12115,9 +12189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:729 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
+    // Pos:733 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
     {
-        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 472, 
+        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 475, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 
@@ -12131,9 +12205,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:730 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
+    // Pos:734 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
     {
-        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 473, 
+        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 476, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12148,9 +12222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:731 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
+    // Pos:735 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 474, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 477, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12164,9 +12238,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:732 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
+    // Pos:736 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 474, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 477, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12180,9 +12254,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:733 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
+    // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12196,9 +12270,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:734 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
+    // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12212,9 +12286,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:735 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
+    // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12228,9 +12302,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:736 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
+    // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12244,9 +12318,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
+    // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12260,9 +12334,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
+    // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12276,9 +12350,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
+    // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12292,9 +12366,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
+    // Pos:744 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12308,9 +12382,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:741 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
+    // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12323,9 +12397,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:742 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
+    // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12338,9 +12412,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:743 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
+    // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12353,9 +12427,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:744 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
+    // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12368,9 +12442,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
+    // Pos:749 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12383,9 +12457,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
+    // Pos:750 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12398,9 +12472,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
+    // Pos:751 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12413,9 +12487,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
+    // Pos:752 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12428,9 +12502,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:749 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
+    // Pos:753 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12443,9 +12517,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:750 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM"
+    // Pos:754 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12459,9 +12533,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:751 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
+    // Pos:755 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12475,9 +12549,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
+    // Pos:756 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12491,9 +12565,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
+    // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12507,9 +12581,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
+    // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12523,9 +12597,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:755 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
+    // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12539,9 +12613,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:756 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM"
+    // Pos:760 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12555,9 +12629,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:757 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM"
+    // Pos:761 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12571,9 +12645,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:758 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
+    // Pos:762 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12587,9 +12661,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
+    // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12603,9 +12677,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
+    // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12619,9 +12693,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
+    // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12635,9 +12709,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
+    // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12651,9 +12725,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
+    // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12667,9 +12741,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
+    // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12683,9 +12757,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
+    // Pos:769 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12699,9 +12773,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
+    // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12715,9 +12789,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
+    // Pos:771 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12731,9 +12805,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
+    // Pos:772 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12747,9 +12821,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:769 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
+    // Pos:773 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12763,9 +12837,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:770 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR"
+    // Pos:774 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12779,9 +12853,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:771 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
+    // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12795,9 +12869,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
+    // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12811,9 +12885,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR"
+    // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12827,9 +12901,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
+    // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12843,9 +12917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
+    // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12859,9 +12933,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
+    // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12875,9 +12949,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
+    // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12891,9 +12965,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
+    // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12907,9 +12981,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
+    // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12923,9 +12997,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
+    // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12939,9 +13013,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
+    // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12955,9 +13029,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
+    // Pos:786 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12971,9 +13045,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
+    // Pos:787 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12987,9 +13061,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
+    // Pos:788 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13003,9 +13077,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
+    // Pos:789 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13019,9 +13093,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:786 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
+    // Pos:790 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 475, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13035,9 +13109,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:787 Instruction:"NOP" Encoding:"0x90"/""
+    // Pos:791 Instruction:"NOP" Encoding:"0x90"/""
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 475, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -13050,9 +13124,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:788 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
+    // Pos:792 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 476, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 479, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13065,9 +13139,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:789 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
+    // Pos:793 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 476, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 479, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13080,9 +13154,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:790 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
+    // Pos:794 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13097,9 +13171,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:791 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
+    // Pos:795 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13114,9 +13188,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:792 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
+    // Pos:796 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13131,9 +13205,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:793 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
+    // Pos:797 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13148,9 +13222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:794 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
+    // Pos:798 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -13165,9 +13239,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:795 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
+    // Pos:799 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -13182,9 +13256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:796 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
+    // Pos:800 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13199,9 +13273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:797 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
+    // Pos:801 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13216,9 +13290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:798 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
+    // Pos:802 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -13233,9 +13307,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:799 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
+    // Pos:803 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 477, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13250,9 +13324,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:800 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
+    // Pos:804 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 478, 
+        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 481, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13266,9 +13340,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:801 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
+    // Pos:805 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 479, 
+        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 482, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -13282,9 +13356,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:802 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
+    // Pos:806 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 480, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13299,9 +13373,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:803 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
+    // Pos:807 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 480, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13316,9 +13390,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:804 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
+    // Pos:808 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 480, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13333,9 +13407,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:805 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
+    // Pos:809 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 480, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13350,9 +13424,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:806 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
+    // Pos:810 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13368,9 +13442,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:807 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
+    // Pos:811 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13387,9 +13461,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:808 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
+    // Pos:812 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 485, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13405,9 +13479,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:809 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
+    // Pos:813 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 485, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13424,9 +13498,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:810 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
+    // Pos:814 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 483, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 486, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13442,9 +13516,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:811 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
+    // Pos:815 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 483, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 486, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13461,9 +13535,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:812 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
+    // Pos:816 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 484, 
+        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 487, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13477,9 +13551,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:813 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
+    // Pos:817 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 484, 
+        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 487, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13493,9 +13567,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:814 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
+    // Pos:818 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 485, 
+        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 488, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13509,9 +13583,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:815 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
+    // Pos:819 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 485, 
+        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 488, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13525,9 +13599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:816 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
+    // Pos:820 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 486, 
+        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 489, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13541,9 +13615,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:817 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
+    // Pos:821 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 486, 
+        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 489, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13557,9 +13631,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:818 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
+    // Pos:822 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 487, 
+        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 490, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13573,9 +13647,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:819 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
+    // Pos:823 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 487, 
+        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 490, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13589,9 +13663,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:820 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
+    // Pos:824 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 488, 
+        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 491, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13605,9 +13679,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:821 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
+    // Pos:825 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 488, 
+        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 491, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13621,9 +13695,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:822 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
+    // Pos:826 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
     {
-        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 489, 
+        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 492, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -13637,9 +13711,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:823 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
+    // Pos:827 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 490, 
+        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 493, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13653,9 +13727,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:824 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
+    // Pos:828 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 490, 
+        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 493, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13669,9 +13743,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:825 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
+    // Pos:829 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 491, 
+        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 494, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13685,9 +13759,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:826 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
+    // Pos:830 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 491, 
+        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 494, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13701,9 +13775,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:827 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
+    // Pos:831 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 492, 
+        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 495, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13717,9 +13791,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:828 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
+    // Pos:832 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 492, 
+        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 495, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13733,9 +13807,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:829 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
+    // Pos:833 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 493, 
+        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 496, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -13749,9 +13823,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:830 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
+    // Pos:834 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 493, 
+        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 496, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13765,9 +13839,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:831 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
+    // Pos:835 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 494, 
+        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 497, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13781,9 +13855,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:832 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
+    // Pos:836 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 494, 
+        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 497, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13797,9 +13871,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:833 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
+    // Pos:837 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 495, 
+        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 498, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13813,9 +13887,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:834 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
+    // Pos:838 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 495, 
+        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 498, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13829,9 +13903,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:835 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
+    // Pos:839 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 496, 
+        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 499, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13845,9 +13919,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:836 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
+    // Pos:840 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 496, 
+        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 499, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13861,9 +13935,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:837 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
+    // Pos:841 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 497, 
+        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 500, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13877,9 +13951,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:838 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
+    // Pos:842 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 497, 
+        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 500, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13893,9 +13967,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:839 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
+    // Pos:843 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 498, 
+        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 501, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13909,9 +13983,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:840 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
+    // Pos:844 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 498, 
+        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 501, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13925,9 +13999,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:841 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
+    // Pos:845 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 499, 
+        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 502, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13942,9 +14016,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:842 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
+    // Pos:846 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 499, 
+        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 502, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13959,9 +14033,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:843 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
+    // Pos:847 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 500, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 503, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13975,9 +14049,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:844 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
+    // Pos:848 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 500, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 503, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13991,9 +14065,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:845 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
+    // Pos:849 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 501, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 504, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14007,9 +14081,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:846 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
+    // Pos:850 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 501, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 504, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14023,9 +14097,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:847 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/""
+    // Pos:851 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/""
     {
-        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 502, 
+        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 505, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -14038,9 +14112,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:848 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
+    // Pos:852 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 503, 
+        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 506, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14054,9 +14128,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:849 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
+    // Pos:853 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 503, 
+        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 506, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14070,9 +14144,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:850 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
+    // Pos:854 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
     {
-        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 504, 
+        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 507, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14086,9 +14160,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:851 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
+    // Pos:855 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 505, 
+        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 508, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14102,9 +14176,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:852 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
+    // Pos:856 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 505, 
+        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 508, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14118,9 +14192,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:853 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
+    // Pos:857 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
     {
-        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 506, 
+        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 509, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14135,9 +14209,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:854 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
+    // Pos:858 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
     {
-        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 507, 
+        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 510, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14152,9 +14226,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:855 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
+    // Pos:859 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
     {
-        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 508, 
+        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 511, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 
@@ -14169,9 +14243,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:856 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
+    // Pos:860 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 509, 
+        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 512, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14185,9 +14259,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:857 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
+    // Pos:861 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 509, 
+        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 512, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14201,9 +14275,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:858 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
+    // Pos:862 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 510, 
+        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 513, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14217,9 +14291,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:859 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
+    // Pos:863 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 510, 
+        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 513, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14233,9 +14307,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:860 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
+    // Pos:864 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
     {
-        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 511, 
+        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 514, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14249,9 +14323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:861 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
+    // Pos:865 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 512, 
+        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 515, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14265,9 +14339,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:862 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
+    // Pos:866 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 512, 
+        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 515, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14281,9 +14355,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:863 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
+    // Pos:867 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 513, 
+        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 516, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14302,9 +14376,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:864 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
+    // Pos:868 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 514, 
+        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 517, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14323,9 +14397,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:865 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
+    // Pos:869 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 515, 
+        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 518, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14339,9 +14413,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:866 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
+    // Pos:870 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 515, 
+        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 518, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14355,9 +14429,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:867 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
+    // Pos:871 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 516, 
+        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 519, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14371,9 +14445,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:868 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
+    // Pos:872 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 516, 
+        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 519, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14387,9 +14461,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:869 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
+    // Pos:873 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
     {
-        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 517, 
+        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 520, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14403,9 +14477,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:870 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
+    // Pos:874 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 518, 
+        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 521, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14419,9 +14493,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:871 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
+    // Pos:875 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 518, 
+        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 521, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14435,9 +14509,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:872 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
+    // Pos:876 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 519, 
+        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 522, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14454,9 +14528,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:873 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
+    // Pos:877 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 520, 
+        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 523, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14473,9 +14547,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:874 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
+    // Pos:878 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
     {
-        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 521, 
+        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 
@@ -14491,9 +14565,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:875 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:879 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 522, 
+        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -14508,9 +14582,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:876 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:880 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 523, 
+        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -14525,9 +14599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:877 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
+    // Pos:881 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14542,9 +14616,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:878 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
+    // Pos:882 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14559,9 +14633,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:879 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
+    // Pos:883 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 525, 
+        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 528, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14576,9 +14650,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:880 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
+    // Pos:884 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 526, 
+        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 529, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14593,9 +14667,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:881 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:885 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 527, 
+        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 530, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14610,9 +14684,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:882 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:886 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 527, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 530, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14627,9 +14701,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:883 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
+    // Pos:887 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 530, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14644,9 +14718,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:884 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
+    // Pos:888 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 530, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14661,9 +14735,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:885 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
+    // Pos:889 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
     {
-        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 528, 
+        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14677,9 +14751,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:886 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
+    // Pos:890 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
     {
-        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 529, 
+        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14693,9 +14767,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:887 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
+    // Pos:891 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
     {
-        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 
+        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14709,9 +14783,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:888 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
+    // Pos:892 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
     {
-        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
+        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14725,9 +14799,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:889 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
+    // Pos:893 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
     {
-        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
+        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14741,9 +14815,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:890 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
+    // Pos:894 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
     {
-        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
+        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14757,9 +14831,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:891 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
+    // Pos:895 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
     {
-        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
+        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14773,9 +14847,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:892 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
+    // Pos:896 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
     {
-        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
+        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 538, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14789,9 +14863,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:893 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
+    // Pos:897 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
     {
-        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 
+        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 539, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14805,9 +14879,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:894 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
+    // Pos:898 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
     {
-        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 
+        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 540, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14821,9 +14895,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:895 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
+    // Pos:899 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
     {
-        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 538, 
+        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 541, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14837,9 +14911,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:896 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
+    // Pos:900 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
     {
-        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 539, 
+        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 542, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14853,9 +14927,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:897 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
+    // Pos:901 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
     {
-        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 540, 
+        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14869,9 +14943,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:898 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
+    // Pos:902 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
     {
-        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 541, 
+        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 544, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14885,9 +14959,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:899 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
+    // Pos:903 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
     {
-        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 542, 
+        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14901,9 +14975,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:900 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
+    // Pos:904 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
     {
-        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 
+        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 
@@ -14917,9 +14991,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:901 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
+    // Pos:905 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
     {
-        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 544, 
+        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 547, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14933,9 +15007,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:902 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
+    // Pos:906 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
     {
-        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 
+        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 548, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14949,9 +15023,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:903 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
+    // Pos:907 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
     {
-        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 
+        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 549, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 
@@ -14965,9 +15039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:904 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
+    // Pos:908 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
     {
-        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 547, 
+        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14981,9 +15055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:905 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
+    // Pos:909 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
     {
-        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 548, 
+        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14997,9 +15071,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:906 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:910 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 549, 
+        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 552, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15013,9 +15087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:907 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:911 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 549, 
+        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 552, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15029,9 +15103,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:908 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:912 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 550, 
+        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15045,9 +15119,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:909 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:913 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 550, 
+        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15061,9 +15135,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:910 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:914 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 551, 
+        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15077,9 +15151,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:911 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:915 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 551, 
+        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15093,9 +15167,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:912 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
+    // Pos:916 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
     {
-        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 552, 
+        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 555, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15109,9 +15183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:913 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:917 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 553, 
+        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 556, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15125,9 +15199,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:914 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:918 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 553, 
+        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 556, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15141,9 +15215,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:915 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:919 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 554, 
+        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15157,9 +15231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:916 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:920 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 554, 
+        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15173,9 +15247,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:917 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:921 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 555, 
+        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15189,9 +15263,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:918 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:922 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 555, 
+        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15205,9 +15279,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:919 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
+    // Pos:923 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
     {
-        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 
+        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15221,9 +15295,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:920 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
+    // Pos:924 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
     {
-        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 
+        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15237,9 +15311,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:921 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
+    // Pos:925 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15254,9 +15328,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:922 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
+    // Pos:926 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15271,9 +15345,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:923 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:927 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 559, 
+        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 562, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15288,9 +15362,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:924 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:928 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 560, 
+        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 563, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15305,9 +15379,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:925 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:929 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15322,9 +15396,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:926 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:930 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15339,9 +15413,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:927 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:931 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15356,9 +15430,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:928 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:932 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15373,9 +15447,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:929 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:933 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 562, 
+        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15389,9 +15463,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:930 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:934 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 562, 
+        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15405,9 +15479,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:931 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
+    // Pos:935 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 563, 
+        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15421,9 +15495,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:932 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
+    // Pos:936 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 563, 
+        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15437,9 +15511,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:933 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
+    // Pos:937 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
     {
-        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 564, 
+        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15453,9 +15527,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:934 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
+    // Pos:938 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
     {
-        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 565, 
+        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 568, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15469,9 +15543,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:935 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
+    // Pos:939 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 566, 
+        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15485,9 +15559,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:936 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
+    // Pos:940 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 566, 
+        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15501,9 +15575,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:937 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
+    // Pos:941 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 567, 
+        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 570, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15517,9 +15591,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:938 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
+    // Pos:942 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 567, 
+        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 570, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15533,9 +15607,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:939 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
+    // Pos:943 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
     {
-        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 568, 
+        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 571, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15549,9 +15623,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:940 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
+    // Pos:944 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
     {
-        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 569, 
+        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15565,9 +15639,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:941 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
+    // Pos:945 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
     {
-        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 570, 
+        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15581,9 +15655,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:942 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
+    // Pos:946 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
     {
-        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 571, 
+        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15597,9 +15671,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:943 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
+    // Pos:947 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 572, 
+        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15613,9 +15687,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:944 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
+    // Pos:948 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 572, 
+        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15629,9 +15703,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:945 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
+    // Pos:949 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 573, 
+        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15645,9 +15719,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:946 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
+    // Pos:950 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 573, 
+        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15661,9 +15735,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:947 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
+    // Pos:951 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
     {
-        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 574, 
+        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 577, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15677,9 +15751,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:948 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
+    // Pos:952 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
     {
-        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 575, 
+        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 578, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15693,9 +15767,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:949 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:953 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 576, 
+        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -15709,9 +15783,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:950 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:954 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 576, 
+        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15725,9 +15799,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:951 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
+    // Pos:955 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
     {
-        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 577, 
+        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 580, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15741,9 +15815,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:952 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
+    // Pos:956 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
     {
-        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 578, 
+        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 581, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15757,9 +15831,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:953 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
+    // Pos:957 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
     {
-        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 579, 
+        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 582, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15773,9 +15847,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:954 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
+    // Pos:958 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
     {
-        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 580, 
+        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 583, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15789,9 +15863,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:955 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
+    // Pos:959 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
     {
-        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 581, 
+        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 584, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15805,9 +15879,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:956 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
+    // Pos:960 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
     {
-        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 582, 
+        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15821,9 +15895,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:957 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
+    // Pos:961 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
     {
-        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 583, 
+        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 586, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15837,9 +15911,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:958 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
+    // Pos:962 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
     {
-        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 584, 
+        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 587, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15853,9 +15927,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:959 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
+    // Pos:963 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
     {
-        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 585, 
+        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 588, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15869,9 +15943,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:960 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
+    // Pos:964 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
     {
-        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 586, 
+        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 589, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15885,9 +15959,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:961 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
+    // Pos:965 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
     {
-        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 587, 
+        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 590, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15901,9 +15975,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:962 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
+    // Pos:966 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
     {
-        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 588, 
+        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 591, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15917,9 +15991,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:963 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
+    // Pos:967 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
     {
-        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 589, 
+        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 592, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15933,9 +16007,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:964 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:968 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 590, 
+        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 593, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15949,9 +16023,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:965 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:969 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 590, 
+        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 593, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15965,9 +16039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:966 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
+    // Pos:970 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
     {
-        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 591, 
+        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 594, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15981,9 +16055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:967 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
+    // Pos:971 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 592, 
+        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 595, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15997,9 +16071,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:968 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
+    // Pos:972 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 592, 
+        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 595, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16013,9 +16087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:969 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
+    // Pos:973 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 593, 
+        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16029,9 +16103,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:970 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
+    // Pos:974 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 593, 
+        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16045,9 +16119,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:971 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
+    // Pos:975 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
     {
-        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 594, 
+        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16061,9 +16135,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:972 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
+    // Pos:976 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 595, 
+        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 598, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16077,9 +16151,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:973 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
+    // Pos:977 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 595, 
+        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 598, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16093,9 +16167,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:974 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
+    // Pos:978 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 596, 
+        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 599, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -16109,9 +16183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:975 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
+    // Pos:979 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 596, 
+        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 599, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16125,9 +16199,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:976 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
+    // Pos:980 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16141,9 +16215,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:977 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
+    // Pos:981 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16157,9 +16231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:978 Instruction:"POP ES" Encoding:"0x07"/""
+    // Pos:982 Instruction:"POP ES" Encoding:"0x07"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16173,9 +16247,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:979 Instruction:"POP SS" Encoding:"0x17"/""
+    // Pos:983 Instruction:"POP SS" Encoding:"0x17"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16189,9 +16263,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:980 Instruction:"POP DS" Encoding:"0x1F"/""
+    // Pos:984 Instruction:"POP DS" Encoding:"0x1F"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16205,9 +16279,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:981 Instruction:"POP Zv" Encoding:"0x58"/"O"
+    // Pos:985 Instruction:"POP Zv" Encoding:"0x58"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16221,9 +16295,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:982 Instruction:"POP Zv" Encoding:"0x59"/"O"
+    // Pos:986 Instruction:"POP Zv" Encoding:"0x59"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16237,9 +16311,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:983 Instruction:"POP Zv" Encoding:"0x5A"/"O"
+    // Pos:987 Instruction:"POP Zv" Encoding:"0x5A"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16253,9 +16327,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:984 Instruction:"POP Zv" Encoding:"0x5B"/"O"
+    // Pos:988 Instruction:"POP Zv" Encoding:"0x5B"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16269,9 +16343,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:985 Instruction:"POP Zv" Encoding:"0x5C"/"O"
+    // Pos:989 Instruction:"POP Zv" Encoding:"0x5C"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16285,9 +16359,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:986 Instruction:"POP Zv" Encoding:"0x5D"/"O"
+    // Pos:990 Instruction:"POP Zv" Encoding:"0x5D"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16301,9 +16375,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:987 Instruction:"POP Zv" Encoding:"0x5E"/"O"
+    // Pos:991 Instruction:"POP Zv" Encoding:"0x5E"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16317,9 +16391,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:988 Instruction:"POP Zv" Encoding:"0x5F"/"O"
+    // Pos:992 Instruction:"POP Zv" Encoding:"0x5F"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16333,9 +16407,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:989 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
+    // Pos:993 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -16349,9 +16423,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:990 Instruction:"POPA" Encoding:"ds16 0x61"/""
+    // Pos:994 Instruction:"POPA" Encoding:"ds16 0x61"/""
     {
-        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 598, 
+        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 601, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16365,9 +16439,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:991 Instruction:"POPAD" Encoding:"ds32 0x61"/""
+    // Pos:995 Instruction:"POPAD" Encoding:"ds32 0x61"/""
     {
-        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 599, 
+        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 602, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16381,9 +16455,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:992 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
+    // Pos:996 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
     {
-        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 600, 
+        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 603, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 
@@ -16398,9 +16472,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:993 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
+    // Pos:997 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 601, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 604, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16414,9 +16488,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:994 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
+    // Pos:998 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 602, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16430,9 +16504,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:995 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
+    // Pos:999 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 603, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 606, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16446,9 +16520,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:996 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+    // Pos:1000 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 604, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 607, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16462,9 +16536,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:997 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
+    // Pos:1001 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 604, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 607, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16478,9 +16552,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:998 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
+    // Pos:1002 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16493,9 +16567,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:999 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
+    // Pos:1003 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16508,9 +16582,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1000 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
+    // Pos:1004 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16523,9 +16597,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1001 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
+    // Pos:1005 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16538,9 +16612,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1002 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
+    // Pos:1006 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
     {
-        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 606, 
+        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 609, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16553,9 +16627,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1003 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
+    // Pos:1007 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
     {
-        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 
+        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 610, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16568,9 +16642,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1004 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
+    // Pos:1008 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
     {
-        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 608, 
+        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 611, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16583,9 +16657,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1005 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
+    // Pos:1009 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
     {
-        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 609, 
+        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 612, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16598,9 +16672,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1006 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
+    // Pos:1010 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
     {
-        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 610, 
+        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 613, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16613,9 +16687,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1007 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
+    // Pos:1011 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
     {
-        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 611, 
+        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 614, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16628,9 +16702,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1008 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
+    // Pos:1012 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
     {
-        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 612, 
+        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 615, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16643,9 +16717,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1009 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
+    // Pos:1013 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
     {
-        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 613, 
+        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 616, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16658,9 +16732,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1010 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
+    // Pos:1014 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 614, 
+        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 617, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16674,9 +16748,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1011 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
+    // Pos:1015 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 614, 
+        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 617, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16690,9 +16764,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1012 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1016 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 615, 
+        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 618, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16706,9 +16780,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1013 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1017 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 615, 
+        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 618, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16722,9 +16796,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1014 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1018 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 616, 
+        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 619, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16739,9 +16813,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1015 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1019 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 617, 
+        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 620, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16756,9 +16830,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1016 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1020 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16773,9 +16847,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1017 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1021 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 619, 
+        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 622, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16790,9 +16864,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1018 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1022 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 620, 
+        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16806,9 +16880,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1019 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1023 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 620, 
+        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16822,9 +16896,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1020 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1024 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 621, 
+        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 624, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16838,9 +16912,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1021 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1025 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 621, 
+        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 624, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16854,9 +16928,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1022 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1026 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 622, 
+        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16870,9 +16944,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1023 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1027 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 622, 
+        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16886,9 +16960,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1024 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1028 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16902,9 +16976,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1025 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1029 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16918,9 +16992,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1026 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
+    // Pos:1030 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16934,9 +17008,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1027 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
+    // Pos:1031 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16950,9 +17024,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1028 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
+    // Pos:1032 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
     {
-        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 624, 
+        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 627, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16966,9 +17040,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1029 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1033 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16982,9 +17056,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1030 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1034 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16998,9 +17072,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1031 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
+    // Pos:1035 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17014,9 +17088,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1032 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
+    // Pos:1036 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17030,9 +17104,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1033 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1037 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17046,9 +17120,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1034 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1038 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17062,9 +17136,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1035 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
+    // Pos:1039 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17078,9 +17152,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1036 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
+    // Pos:1040 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17094,9 +17168,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1037 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
+    // Pos:1041 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 627, 
+        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 630, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -17110,9 +17184,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1038 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1042 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 631, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17126,9 +17200,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1039 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1043 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 631, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17142,9 +17216,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1040 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
+    // Pos:1044 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 631, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17158,9 +17232,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1041 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
+    // Pos:1045 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 631, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17174,9 +17248,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1042 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1046 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17190,9 +17264,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1043 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1047 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17206,9 +17280,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1044 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
+    // Pos:1048 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17222,9 +17296,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1045 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
+    // Pos:1049 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17238,9 +17312,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1046 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1050 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17254,9 +17328,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1047 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1051 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17270,9 +17344,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1048 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
+    // Pos:1052 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17286,9 +17360,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1049 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
+    // Pos:1053 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17302,9 +17376,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1050 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
+    // Pos:1054 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
     {
-        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 631, 
+        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 634, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17318,9 +17392,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1051 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1055 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17334,9 +17408,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1052 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1056 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17350,9 +17424,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1053 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
+    // Pos:1057 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17366,9 +17440,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1054 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
+    // Pos:1058 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17382,9 +17456,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1055 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1059 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17398,9 +17472,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1056 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1060 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17414,9 +17488,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1057 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
+    // Pos:1061 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17430,9 +17504,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1058 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
+    // Pos:1062 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17446,9 +17520,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1059 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
+    // Pos:1063 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 634, 
+        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17462,9 +17536,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1060 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
+    // Pos:1064 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 634, 
+        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17478,9 +17552,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1061 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
+    // Pos:1065 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 635, 
+        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 638, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17494,9 +17568,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1062 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
+    // Pos:1066 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 635, 
+        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 638, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17510,9 +17584,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1063 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
+    // Pos:1067 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 636, 
+        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 639, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17526,9 +17600,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1064 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
+    // Pos:1068 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 636, 
+        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 639, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17542,9 +17616,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1065 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
+    // Pos:1069 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 637, 
+        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17558,9 +17632,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1066 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
+    // Pos:1070 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 637, 
+        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17574,9 +17648,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1067 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
+    // Pos:1071 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 638, 
+        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17590,9 +17664,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1068 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
+    // Pos:1072 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 638, 
+        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17606,9 +17680,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1069 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
+    // Pos:1073 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 639, 
+        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 642, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17622,9 +17696,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1070 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
+    // Pos:1074 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 639, 
+        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 642, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17638,9 +17712,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1071 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
+    // Pos:1075 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 640, 
+        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 643, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17654,9 +17728,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1072 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
+    // Pos:1076 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 640, 
+        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 643, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17670,9 +17744,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1073 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
+    // Pos:1077 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 641, 
+        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 644, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17686,9 +17760,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1074 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
+    // Pos:1078 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 641, 
+        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 644, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17702,9 +17776,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1075 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
+    // Pos:1079 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
     {
-        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 642, 
+        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 645, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -17718,9 +17792,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1076 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
+    // Pos:1080 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
     {
-        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 643, 
+        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 646, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -17735,9 +17809,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1077 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
+    // Pos:1081 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
     {
-        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 644, 
+        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 647, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 
@@ -17750,9 +17824,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1078 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
+    // Pos:1082 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 645, 
+        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17766,9 +17840,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1079 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
+    // Pos:1083 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 645, 
+        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17782,9 +17856,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1080 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
+    // Pos:1084 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 646, 
+        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17798,9 +17872,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1081 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
+    // Pos:1085 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 646, 
+        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17814,9 +17888,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1082 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
+    // Pos:1086 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
     {
-        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 647, 
+        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17830,9 +17904,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1083 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
+    // Pos:1087 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 648, 
+        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17846,9 +17920,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1084 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
+    // Pos:1088 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 648, 
+        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17862,9 +17936,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1085 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
+    // Pos:1089 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 649, 
+        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17878,9 +17952,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1086 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
+    // Pos:1090 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 649, 
+        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17894,9 +17968,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1087 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
+    // Pos:1091 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 650, 
+        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17910,9 +17984,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1088 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
+    // Pos:1092 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
+        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17926,9 +18000,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1089 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
+    // Pos:1093 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
     {
-        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 651, 
+        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 654, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17942,9 +18016,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1090 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
+    // Pos:1094 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 652, 
+        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17958,9 +18032,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1091 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
+    // Pos:1095 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 652, 
+        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17974,9 +18048,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1092 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
+    // Pos:1096 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17990,9 +18064,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1093 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
+    // Pos:1097 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18006,9 +18080,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1094 Instruction:"PUSH ES" Encoding:"0x06"/""
+    // Pos:1098 Instruction:"PUSH ES" Encoding:"0x06"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18022,9 +18096,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1095 Instruction:"PUSH CS" Encoding:"0x0E"/""
+    // Pos:1099 Instruction:"PUSH CS" Encoding:"0x0E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18038,9 +18112,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1096 Instruction:"PUSH SS" Encoding:"0x16"/""
+    // Pos:1100 Instruction:"PUSH SS" Encoding:"0x16"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18054,9 +18128,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1097 Instruction:"PUSH DS" Encoding:"0x1E"/""
+    // Pos:1101 Instruction:"PUSH DS" Encoding:"0x1E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18070,9 +18144,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1098 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
+    // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18086,9 +18160,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1099 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
+    // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18102,9 +18176,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1100 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
+    // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18118,9 +18192,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1101 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
+    // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18134,9 +18208,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
+    // Pos:1106 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18150,9 +18224,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
+    // Pos:1107 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18166,9 +18240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
+    // Pos:1108 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18182,9 +18256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
+    // Pos:1109 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18198,9 +18272,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1106 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
+    // Pos:1110 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18214,9 +18288,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1107 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
+    // Pos:1111 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18230,9 +18304,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1108 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
+    // Pos:1112 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -18246,9 +18320,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1109 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
+    // Pos:1113 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
     {
-        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 654, 
+        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 657, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18262,9 +18336,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1110 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
+    // Pos:1114 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
     {
-        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 655, 
+        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 658, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18278,9 +18352,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1111 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
+    // Pos:1115 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 656, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 659, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18294,9 +18368,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1112 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
+    // Pos:1116 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 657, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 660, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18310,9 +18384,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1113 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
+    // Pos:1117 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 658, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18326,9 +18400,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1114 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+    // Pos:1118 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 659, 
+        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 662, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 
@@ -18344,9 +18418,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1115 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
+    // Pos:1119 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 660, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 663, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18360,9 +18434,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1116 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
+    // Pos:1120 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 660, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 663, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18376,9 +18450,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1117 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
+    // Pos:1121 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18393,9 +18467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1118 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
+    // Pos:1122 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18410,9 +18484,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1119 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
+    // Pos:1123 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18427,9 +18501,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1120 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
+    // Pos:1124 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18444,9 +18518,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1121 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
+    // Pos:1125 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18461,9 +18535,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1122 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
+    // Pos:1126 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18478,9 +18552,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1123 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
+    // Pos:1127 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 662, 
+        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 665, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -18494,9 +18568,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1124 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
+    // Pos:1128 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 663, 
+        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 666, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -18510,9 +18584,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1125 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
+    // Pos:1129 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18527,9 +18601,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1126 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
+    // Pos:1130 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18544,9 +18618,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1127 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
+    // Pos:1131 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18561,9 +18635,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1128 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
+    // Pos:1132 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18578,9 +18652,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1129 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
+    // Pos:1133 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18595,9 +18669,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1130 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
+    // Pos:1134 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18612,9 +18686,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1131 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
+    // Pos:1135 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
     {
-        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 665, 
+        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 668, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -18628,9 +18702,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1132 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
+    // Pos:1136 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
     {
-        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 666, 
+        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 669, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -18644,9 +18718,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1133 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
+    // Pos:1137 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
     {
-        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 667, 
+        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 670, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 
@@ -18662,9 +18736,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1134 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1138 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 668, 
+        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 671, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 
@@ -18678,9 +18752,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1135 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
+    // Pos:1139 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
     {
-        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 669, 
+        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 672, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -18696,9 +18770,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1136 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
+    // Pos:1140 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
     {
-        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 670, 
+        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 673, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18714,9 +18788,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1137 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
+    // Pos:1141 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
     {
-        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 671, 
+        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 674, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 
@@ -18732,9 +18806,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1138 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
+    // Pos:1142 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 675, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -18748,9 +18822,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1139 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1143 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 675, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -18764,9 +18838,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1140 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
+    // Pos:1144 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 676, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -18780,9 +18854,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1141 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1145 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 676, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -18796,9 +18870,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1142 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
+    // Pos:1146 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
     {
-        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 674, 
+        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 677, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18811,9 +18885,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1143 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
+    // Pos:1147 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 675, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 678, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -18827,9 +18901,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1144 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
+    // Pos:1148 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 676, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -18843,9 +18917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1145 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
+    // Pos:1149 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
     {
-        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 677, 
+        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 680, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18860,9 +18934,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1146 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
+    // Pos:1150 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
     {
-        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 678, 
+        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 681, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 
@@ -18879,9 +18953,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1147 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
+    // Pos:1151 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 682, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18898,9 +18972,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1148 Instruction:"RETF" Encoding:"0xCB"/""
+    // Pos:1152 Instruction:"RETF" Encoding:"0xCB"/""
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 682, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18916,9 +18990,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1149 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
+    // Pos:1153 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 683, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -18935,9 +19009,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1150 Instruction:"RETN" Encoding:"0xC3"/""
+    // Pos:1154 Instruction:"RETN" Encoding:"0xC3"/""
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 683, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -18952,9 +19026,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1151 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
+    // Pos:1155 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 681, 
+        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 684, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -18970,9 +19044,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1152 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
+    // Pos:1156 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 682, 
+        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 685, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -18987,9 +19061,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1153 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
+    // Pos:1157 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19004,9 +19078,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1154 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
+    // Pos:1158 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19021,9 +19095,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1155 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
+    // Pos:1159 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19038,9 +19112,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1156 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
+    // Pos:1160 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19055,9 +19129,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1157 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
+    // Pos:1161 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19072,9 +19146,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1158 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
+    // Pos:1162 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19089,9 +19163,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1159 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
+    // Pos:1163 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19106,9 +19180,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1160 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
+    // Pos:1164 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19123,9 +19197,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1161 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
+    // Pos:1165 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19140,9 +19214,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1162 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
+    // Pos:1166 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19157,9 +19231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1163 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
+    // Pos:1167 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19174,9 +19248,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1164 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
+    // Pos:1168 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19191,9 +19265,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1165 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
+    // Pos:1169 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
     {
-        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 685, 
+        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 688, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -19208,9 +19282,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1166 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
+    // Pos:1170 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 686, 
+        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 689, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19225,9 +19299,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1167 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
+    // Pos:1171 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 687, 
+        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19242,9 +19316,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1168 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
+    // Pos:1172 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
     {
-        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 688, 
+        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 691, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19259,9 +19333,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1169 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
+    // Pos:1173 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
     {
-        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 689, 
+        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 692, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19276,9 +19350,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1170 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
+    // Pos:1174 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
     {
-        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 690, 
+        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 693, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19292,9 +19366,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1171 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
+    // Pos:1175 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
     {
-        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 691, 
+        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 694, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19307,9 +19381,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1172 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
+    // Pos:1176 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
     {
-        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 692, 
+        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 695, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -19324,9 +19398,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1173 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
+    // Pos:1177 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 693, 
+        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 696, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19340,9 +19414,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1174 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
+    // Pos:1178 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 694, 
+        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 697, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19356,9 +19430,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1175 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
+    // Pos:1179 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
     {
-        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 695, 
+        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19372,9 +19446,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1176 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
+    // Pos:1180 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
     {
-        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 696, 
+        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 699, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19387,9 +19461,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1177 Instruction:"SAHF" Encoding:"0x9E"/""
+    // Pos:1181 Instruction:"SAHF" Encoding:"0x9E"/""
     {
-        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 697, 
+        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19403,9 +19477,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1178 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
+    // Pos:1182 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19420,9 +19494,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1179 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
+    // Pos:1183 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19437,9 +19511,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1180 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
+    // Pos:1184 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19454,9 +19528,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1181 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
+    // Pos:1185 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19471,9 +19545,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1182 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
+    // Pos:1186 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19488,9 +19562,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1183 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
+    // Pos:1187 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19505,9 +19579,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1184 Instruction:"SALC" Encoding:"0xD6"/""
+    // Pos:1188 Instruction:"SALC" Encoding:"0xD6"/""
     {
-        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 699, 
+        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 702, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19521,9 +19595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1185 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
+    // Pos:1189 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19538,9 +19612,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1186 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
+    // Pos:1190 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19555,9 +19629,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1187 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
+    // Pos:1191 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19572,9 +19646,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1188 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
+    // Pos:1192 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19589,9 +19663,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1189 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
+    // Pos:1193 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19606,9 +19680,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1190 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
+    // Pos:1194 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19623,9 +19697,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1191 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1195 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 701, 
+        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 704, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -19640,9 +19714,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1192 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
+    // Pos:1196 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
     {
-        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 
+        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 705, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19656,9 +19730,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1193 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
+    // Pos:1197 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19673,9 +19747,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1194 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
+    // Pos:1198 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19690,9 +19764,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1195 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
+    // Pos:1199 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19707,9 +19781,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1196 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
+    // Pos:1200 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19724,9 +19798,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1197 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
+    // Pos:1201 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19741,9 +19815,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1198 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
+    // Pos:1202 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19758,9 +19832,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1199 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
+    // Pos:1203 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19775,9 +19849,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1200 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
+    // Pos:1204 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19792,9 +19866,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1201 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
+    // Pos:1205 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -19809,9 +19883,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1202 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
+    // Pos:1206 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19826,9 +19900,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1203 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
+    // Pos:1207 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19844,9 +19918,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1204 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
+    // Pos:1208 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19863,9 +19937,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1205 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
+    // Pos:1209 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19881,9 +19955,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1206 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
+    // Pos:1210 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19900,9 +19974,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1207 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
+    // Pos:1211 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19918,9 +19992,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1208 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
+    // Pos:1212 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19937,9 +20011,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1209 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
+    // Pos:1213 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 710, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19955,9 +20029,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1210 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
+    // Pos:1214 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 710, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19974,9 +20048,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1211 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
+    // Pos:1215 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
     {
-        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 708, 
+        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 711, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -19989,9 +20063,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1212 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
+    // Pos:1216 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
     {
-        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 709, 
+        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 712, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -20008,9 +20082,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1213 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
+    // Pos:1217 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
     {
-        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 710, 
+        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 713, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -20023,9 +20097,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1214 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1218 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 711, 
+        ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 714, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -20038,9 +20112,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1215 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
+    // Pos:1219 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 712, 
+        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 715, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, 
@@ -20053,76 +20127,12 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1216 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
-    {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 713, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
-        0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1217 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
-    {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
-        0|NDR_RFLAG_CF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1218 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
-    {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
-        0|NDR_RFLAG_SF|NDR_RFLAG_OF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1219 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
+    // Pos:1220 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
     {
         ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 716, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
-        0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1220 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
-    {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
         0,
         0,
@@ -20133,9 +20143,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1221 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
+    // Pos:1221 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20149,9 +20159,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1222 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+    // Pos:1222 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20165,9 +20175,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1223 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+    // Pos:1223 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20181,12 +20191,76 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1224 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+    // Pos:1224 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
+    {
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
+        0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1225 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
     {
         ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 721, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
+        0|NDR_RFLAG_CF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1226 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+    {
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
+        0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1227 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+    {
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
+        0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1228 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+    {
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|NDR_RFLAG_OF,
         0,
         0,
@@ -20197,9 +20271,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1225 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
+    // Pos:1229 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20213,9 +20287,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1226 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
+    // Pos:1230 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20229,9 +20303,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1227 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
+    // Pos:1231 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 727, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20245,9 +20319,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1228 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
+    // Pos:1232 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20261,9 +20335,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1229 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
+    // Pos:1233 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20277,9 +20351,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1230 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
+    // Pos:1234 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 727, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 730, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20293,9 +20367,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1231 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
+    // Pos:1235 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 728, 
+        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -20309,9 +20383,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1232 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
+    // Pos:1236 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 729, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 732, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20325,9 +20399,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1233 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
+    // Pos:1237 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 730, 
+        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 733, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -20340,9 +20414,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1234 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
+    // Pos:1238 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
     {
-        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 731, 
+        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 734, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20356,9 +20430,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1235 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
+    // Pos:1239 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
     {
-        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 732, 
+        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 735, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20372,9 +20446,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1236 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
+    // Pos:1240 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
     {
-        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 733, 
+        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 736, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20388,9 +20462,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1237 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
+    // Pos:1241 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
     {
-        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 734, 
+        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 737, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20404,9 +20478,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1238 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
+    // Pos:1242 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
     {
-        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 735, 
+        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20421,9 +20495,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1239 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
+    // Pos:1243 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
     {
-        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 736, 
+        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 739, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20437,9 +20511,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1240 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
+    // Pos:1244 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
     {
-        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 737, 
+        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 740, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20453,9 +20527,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1241 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
+    // Pos:1245 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
     {
-        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 738, 
+        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20470,9 +20544,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1242 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
+    // Pos:1246 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20487,9 +20561,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1243 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
+    // Pos:1247 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20504,9 +20578,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1244 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
+    // Pos:1248 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20521,9 +20595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1245 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
+    // Pos:1249 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20538,9 +20612,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1246 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
+    // Pos:1250 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20555,9 +20629,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1247 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
+    // Pos:1251 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 739, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20572,9 +20646,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1248 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
+    // Pos:1252 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 740, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 743, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20590,9 +20664,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1249 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
+    // Pos:1253 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 740, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 743, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20608,9 +20682,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1250 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1254 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 741, 
+        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 744, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -20625,9 +20699,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1251 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
+    // Pos:1255 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20642,9 +20716,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1252 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
+    // Pos:1256 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20659,9 +20733,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1253 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
+    // Pos:1257 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20676,9 +20750,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1254 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
+    // Pos:1258 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20693,9 +20767,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1255 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
+    // Pos:1259 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20710,9 +20784,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1256 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
+    // Pos:1260 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 742, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20727,9 +20801,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1257 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
+    // Pos:1261 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 743, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 746, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20745,9 +20819,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1258 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
+    // Pos:1262 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 743, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 746, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20763,9 +20837,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1259 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1263 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 744, 
+        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 747, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -20780,9 +20854,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1260 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1264 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 745, 
+        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 748, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -20797,9 +20871,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1261 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1265 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 746, 
+        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 749, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20814,9 +20888,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1262 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
+    // Pos:1266 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
     {
-        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 747, 
+        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 750, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20830,9 +20904,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1263 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
+    // Pos:1267 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
     {
-        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 748, 
+        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 751, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -20845,9 +20919,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1264 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
+    // Pos:1268 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 752, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20861,9 +20935,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1265 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
+    // Pos:1269 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 752, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20877,9 +20951,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1266 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
+    // Pos:1270 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
     {
-        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 750, 
+        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 753, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -20892,9 +20966,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1267 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
+    // Pos:1271 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
     {
-        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 751, 
+        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 754, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20907,9 +20981,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1268 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
+    // Pos:1272 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 752, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 755, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20923,9 +20997,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1269 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
+    // Pos:1273 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 752, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 755, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20939,9 +21013,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1270 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
+    // Pos:1274 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
     {
-        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 753, 
+        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 756, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20954,9 +21028,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1271 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
+    // Pos:1275 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 754, 
+        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 757, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -20970,9 +21044,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1272 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
+    // Pos:1276 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 755, 
+        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 758, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20986,9 +21060,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1273 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
+    // Pos:1277 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 756, 
+        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 759, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21002,9 +21076,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1274 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
+    // Pos:1278 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 757, 
+        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 760, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21018,9 +21092,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1275 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
+    // Pos:1279 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
     {
-        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 758, 
+        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 761, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 
@@ -21033,9 +21107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1276 Instruction:"STC" Encoding:"0xF9"/""
+    // Pos:1280 Instruction:"STC" Encoding:"0xF9"/""
     {
-        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 759, 
+        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 762, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21048,9 +21122,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1277 Instruction:"STD" Encoding:"0xFD"/""
+    // Pos:1281 Instruction:"STD" Encoding:"0xFD"/""
     {
-        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 760, 
+        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 763, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21063,9 +21137,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1278 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
+    // Pos:1282 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
     {
-        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 761, 
+        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 764, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -21078,9 +21152,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1279 Instruction:"STI" Encoding:"0xFB"/""
+    // Pos:1283 Instruction:"STI" Encoding:"0xFB"/""
     {
-        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 762, 
+        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 765, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21093,9 +21167,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1280 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
+    // Pos:1284 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
     {
-        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 763, 
+        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 766, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -21109,9 +21183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1281 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
+    // Pos:1285 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21127,9 +21201,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1282 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
+    // Pos:1286 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21146,9 +21220,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1283 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
+    // Pos:1287 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21164,9 +21238,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1284 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
+    // Pos:1288 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21183,9 +21257,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1285 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
+    // Pos:1289 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21201,9 +21275,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1286 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
+    // Pos:1290 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21220,9 +21294,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1287 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
+    // Pos:1291 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 770, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21238,9 +21312,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1288 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
+    // Pos:1292 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 770, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21257,9 +21331,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1289 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
+    // Pos:1293 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 768, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 771, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21273,9 +21347,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1290 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
+    // Pos:1294 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 768, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 771, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21289,9 +21363,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1291 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:1295 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 769, 
+        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 772, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21304,9 +21378,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1292 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
+    // Pos:1296 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 770, 
+        ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 773, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -21319,9 +21393,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1293 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
+    // Pos:1297 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21336,9 +21410,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1294 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
+    // Pos:1298 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21353,9 +21427,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1295 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
+    // Pos:1299 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21370,9 +21444,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1296 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
+    // Pos:1300 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21387,9 +21461,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1297 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
+    // Pos:1301 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21404,9 +21478,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1298 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
+    // Pos:1302 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21421,9 +21495,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1299 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
+    // Pos:1303 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21438,9 +21512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1300 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
+    // Pos:1304 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21455,9 +21529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1301 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
+    // Pos:1305 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -21472,9 +21546,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1302 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
+    // Pos:1306 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 771, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21489,9 +21563,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1303 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
+    // Pos:1307 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 772, 
+        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 775, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21505,9 +21579,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1304 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
+    // Pos:1308 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 773, 
+        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 776, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21521,9 +21595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1305 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
+    // Pos:1309 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 774, 
+        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 777, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21537,9 +21611,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1306 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
+    // Pos:1310 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 775, 
+        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 778, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21553,9 +21627,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1307 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
+    // Pos:1311 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
     {
-        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 776, 
+        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21569,9 +21643,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1308 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
+    // Pos:1312 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
     {
-        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 777, 
+        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 780, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21584,9 +21658,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1309 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
+    // Pos:1313 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
     {
-        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 778, 
+        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 781, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21599,9 +21673,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1310 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
+    // Pos:1314 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
     {
-        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 779, 
+        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 782, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -21615,9 +21689,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1311 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
+    // Pos:1315 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
     {
-        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 780, 
+        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 783, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, 
@@ -21639,9 +21713,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1312 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
+    // Pos:1316 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
     {
-        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 781, 
+        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 784, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, 
@@ -21662,9 +21736,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1313 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
+    // Pos:1317 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
     {
-        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 782, 
+        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 785, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 
@@ -21681,9 +21755,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1314 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
+    // Pos:1318 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
     {
-        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 783, 
+        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 786, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 
@@ -21703,9 +21777,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1315 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
+    // Pos:1319 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
     {
-        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 784, 
+        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 787, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -21719,9 +21793,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1316 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
+    // Pos:1320 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
     {
-        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 785, 
+        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 788, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21734,9 +21808,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1317 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
+    // Pos:1321 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
     {
-        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 786, 
+        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 789, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 
@@ -21751,9 +21825,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1318 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1322 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 787, 
+        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 790, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21768,9 +21842,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1319 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1323 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 788, 
+        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 791, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21785,9 +21859,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1320 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1324 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 789, 
+        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 792, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21802,9 +21876,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1321 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1325 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 790, 
+        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 793, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21819,9 +21893,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1322 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
+    // Pos:1326 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21836,9 +21910,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1323 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
+    // Pos:1327 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21853,9 +21927,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1324 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
+    // Pos:1328 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21870,9 +21944,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1325 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
+    // Pos:1329 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21887,9 +21961,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1326 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
+    // Pos:1330 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21904,9 +21978,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1327 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
+    // Pos:1331 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21921,9 +21995,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1328 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
+    // Pos:1332 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21938,9 +22012,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1329 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
+    // Pos:1333 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 791, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21955,9 +22029,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1330 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
+    // Pos:1334 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
     {
-        ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 792, 
+        ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 795, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -21971,9 +22045,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1331 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1335 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 793, 
+        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 796, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21987,9 +22061,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1332 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1336 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 794, 
+        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 797, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22003,9 +22077,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1333 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
+    // Pos:1337 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
     {
-        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 795, 
+        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 798, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22018,9 +22092,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1334 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1338 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 796, 
+        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 799, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22034,9 +22108,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1335 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
+    // Pos:1339 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
     {
-        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 797, 
+        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 800, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22049,9 +22123,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1336 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
+    // Pos:1340 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
     {
-        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 798, 
+        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 801, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
@@ -22064,9 +22138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1337 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
+    // Pos:1341 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 799, 
+        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 802, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -22082,9 +22156,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1338 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
+    // Pos:1342 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
     {
-        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 800, 
+        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 803, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -22099,9 +22173,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1339 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
+    // Pos:1343 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
     {
-        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 801, 
+        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 804, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -22115,9 +22189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1340 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
+    // Pos:1344 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 802, 
+        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 805, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22132,9 +22206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1341 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
+    // Pos:1345 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 803, 
+        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 806, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22149,9 +22223,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1342 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
+    // Pos:1346 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
     {
-        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 804, 
+        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 807, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22165,9 +22239,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1343 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
+    // Pos:1347 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
     {
-        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 805, 
+        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 808, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22181,9 +22255,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1344 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
+    // Pos:1348 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
     {
-        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 806, 
+        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 809, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22196,9 +22270,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1345 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
+    // Pos:1349 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
     {
-        ND_INS_UIRET, ND_CAT_UINTR, ND_SET_UINTR, 807, 
+        ND_INS_UIRET, ND_CAT_UINTR, ND_SET_UINTR, 810, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -22216,9 +22290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1346 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
+    // Pos:1350 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 808, 
+        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 811, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -22232,9 +22306,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1347 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
+    // Pos:1351 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 809, 
+        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 812, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -22249,9 +22323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1348 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
+    // Pos:1352 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 810, 
+        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 813, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22265,9 +22339,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1349 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
+    // Pos:1353 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 811, 
+        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 814, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22281,9 +22355,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1350 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
+    // Pos:1354 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 812, 
+        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 815, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22297,9 +22371,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1351 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
+    // Pos:1355 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 813, 
+        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 816, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22313,9 +22387,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1352 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
+    // Pos:1356 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 814, 
+        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 817, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22331,9 +22405,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1353 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
+    // Pos:1357 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 815, 
+        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 818, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22349,9 +22423,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1354 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
+    // Pos:1358 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 816, 
+        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 819, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22367,9 +22441,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1355 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
+    // Pos:1359 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 817, 
+        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 820, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22385,9 +22459,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1356 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
+    // Pos:1360 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 818, 
+        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 821, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22403,9 +22477,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1357 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1361 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 818, 
+        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 821, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22420,9 +22494,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1358 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
+    // Pos:1362 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 819, 
+        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 822, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22438,9 +22512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1359 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1363 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 819, 
+        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 822, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22455,9 +22529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1360 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
+    // Pos:1364 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 820, 
+        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 823, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22473,9 +22547,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1361 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1365 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 820, 
+        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 823, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22490,9 +22564,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1362 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
+    // Pos:1366 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 821, 
+        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 824, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22508,9 +22582,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1363 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1367 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 821, 
+        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 824, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22525,9 +22599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1364 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1368 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 822, 
+        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 825, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22542,9 +22616,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1365 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1369 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 823, 
+        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 826, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22559,9 +22633,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1366 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1370 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 824, 
+        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 827, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22576,9 +22650,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1367 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1371 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 824, 
+        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 827, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22593,9 +22667,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1368 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1372 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 825, 
+        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 828, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22610,9 +22684,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1369 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1373 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 825, 
+        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 828, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22627,9 +22701,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1370 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1374 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 826, 
+        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 829, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22644,9 +22718,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1371 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1375 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 826, 
+        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 829, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22661,9 +22735,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1372 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1376 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 827, 
+        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 830, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22678,9 +22752,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1373 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1377 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 827, 
+        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 830, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22695,9 +22769,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1374 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
+    // Pos:1378 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
     {
-        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 828, 
+        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 831, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22711,9 +22785,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1375 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
+    // Pos:1379 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
     {
-        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 829, 
+        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 832, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22728,9 +22802,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1376 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
+    // Pos:1380 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 830, 
+        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 833, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22747,9 +22821,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1377 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
+    // Pos:1381 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 831, 
+        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 834, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22766,9 +22840,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1378 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
+    // Pos:1382 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 832, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 835, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22784,9 +22858,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1379 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1383 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 832, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 835, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22801,9 +22875,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1380 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
+    // Pos:1384 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 833, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 836, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22819,9 +22893,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1381 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1385 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 833, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 836, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22836,9 +22910,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1382 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
+    // Pos:1386 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 834, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 837, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22854,9 +22928,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1383 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1387 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 834, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 837, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22871,9 +22945,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1384 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
+    // Pos:1388 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 835, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 838, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22889,9 +22963,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1385 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1389 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 835, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 838, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22906,9 +22980,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1386 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
+    // Pos:1390 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 836, 
+        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 839, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22924,9 +22998,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1387 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
+    // Pos:1391 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 837, 
+        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 840, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22942,9 +23016,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1388 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
+    // Pos:1392 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 838, 
+        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 841, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22960,9 +23034,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1389 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
+    // Pos:1393 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 839, 
+        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 842, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22978,9 +23052,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1390 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
+    // Pos:1394 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 840, 
+        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 843, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22996,9 +23070,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1391 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
+    // Pos:1395 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 841, 
+        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 844, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23014,9 +23088,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1392 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
+    // Pos:1396 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 842, 
+        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 845, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23030,9 +23104,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1393 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
+    // Pos:1397 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 843, 
+        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 846, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23047,9 +23121,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1394 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
+    // Pos:1398 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 844, 
+        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 847, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23064,9 +23138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1395 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
+    // Pos:1399 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 845, 
+        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 848, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23081,9 +23155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1396 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
+    // Pos:1400 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 846, 
+        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 849, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23098,9 +23172,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1397 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
+    // Pos:1401 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 847, 
+        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 850, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23115,9 +23189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1398 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
+    // Pos:1402 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 848, 
+        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 851, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -23131,9 +23205,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1399 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
+    // Pos:1403 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
     {
-        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 849, 
+        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 852, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23148,9 +23222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1400 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
+    // Pos:1404 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 850, 
+        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 853, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23165,9 +23239,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1401 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
+    // Pos:1405 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 851, 
+        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 854, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23182,9 +23256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1402 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
+    // Pos:1406 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 852, 
+        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 855, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23199,9 +23273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1403 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
+    // Pos:1407 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 853, 
+        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 856, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23216,9 +23290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1404 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
+    // Pos:1408 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 854, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23233,9 +23307,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1405 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
+    // Pos:1409 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 854, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23249,9 +23323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1406 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
+    // Pos:1410 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 855, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 858, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23266,9 +23340,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1407 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
+    // Pos:1411 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 855, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 858, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23282,9 +23356,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1408 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1412 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 856, 
+        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 859, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23301,9 +23375,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1409 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1413 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 856, 
+        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 859, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23319,9 +23393,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1410 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1414 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 857, 
+        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23338,9 +23412,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1411 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1415 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 857, 
+        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23356,9 +23430,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1412 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1416 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 858, 
+        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 861, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23375,9 +23449,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1413 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1417 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 858, 
+        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 861, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23393,9 +23467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1414 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1418 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 859, 
+        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 862, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23412,9 +23486,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1415 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1419 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 859, 
+        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 862, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23430,9 +23504,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1416 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
+    // Pos:1420 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 860, 
+        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 863, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23447,9 +23521,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1417 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
+    // Pos:1421 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 860, 
+        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 863, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23464,9 +23538,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1418 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
+    // Pos:1422 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 861, 
+        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 864, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23481,9 +23555,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1419 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
+    // Pos:1423 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 861, 
+        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 864, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23498,9 +23572,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1420 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
+    // Pos:1424 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 862, 
+        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23515,9 +23589,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1421 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
+    // Pos:1425 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 863, 
+        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 866, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23532,9 +23606,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1422 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
+    // Pos:1426 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 864, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23549,9 +23623,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1423 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
+    // Pos:1427 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 864, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23565,9 +23639,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1424 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
+    // Pos:1428 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 864, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23581,9 +23655,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1425 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1429 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 865, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 868, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23598,9 +23672,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1426 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
+    // Pos:1430 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 865, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 868, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23614,9 +23688,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1427 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
+    // Pos:1431 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
     {
-        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 866, 
+        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 869, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -23632,9 +23706,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1428 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
+    // Pos:1432 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
     {
-        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 867, 
+        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 870, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -23649,9 +23723,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1429 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1433 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 868, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23666,9 +23740,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1430 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1434 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 868, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23682,9 +23756,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1431 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
+    // Pos:1435 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 869, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23699,9 +23773,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1432 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1436 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 869, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23715,9 +23789,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1433 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1437 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 869, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23731,9 +23805,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1434 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
+    // Pos:1438 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 870, 
+        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 873, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23748,9 +23822,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1435 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1439 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
+        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 874, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23765,9 +23839,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1436 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1440 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, 
+        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 875, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23782,9 +23856,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1437 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
+    // Pos:1441 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 873, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 876, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23799,9 +23873,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1438 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
+    // Pos:1442 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 873, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 876, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23815,9 +23889,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1439 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
+    // Pos:1443 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 873, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 876, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23831,9 +23905,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1440 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1444 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 874, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23848,9 +23922,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1441 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
+    // Pos:1445 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 874, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 877, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23864,9 +23938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1442 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
+    // Pos:1446 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 875, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23881,9 +23955,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1443 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1447 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 875, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23897,9 +23971,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1444 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1448 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 875, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23913,9 +23987,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1445 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
+    // Pos:1449 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 876, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23931,9 +24005,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1446 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
+    // Pos:1450 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 876, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23948,9 +24022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1447 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
+    // Pos:1451 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 876, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23965,9 +24039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1448 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
+    // Pos:1452 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 877, 
+        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 880, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23982,9 +24056,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1449 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1453 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 878, 
+        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 881, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23999,9 +24073,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1450 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1454 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 879, 
+        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24016,9 +24090,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1451 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1455 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 880, 
+        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 883, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24033,9 +24107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1452 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
+    // Pos:1456 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 881, 
+        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 884, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24050,9 +24124,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1453 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1457 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 882, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24066,9 +24140,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1454 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1458 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 882, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 885, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24082,9 +24156,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1455 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
+    // Pos:1459 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 886, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24100,9 +24174,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1456 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1460 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 883, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 886, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24117,9 +24191,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1457 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
+    // Pos:1461 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 
+        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24133,9 +24207,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1458 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
+    // Pos:1462 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24150,9 +24224,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1459 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
+    // Pos:1463 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24167,9 +24241,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1460 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1464 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 885, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 888, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24184,9 +24258,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1461 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1465 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 886, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 889, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24201,9 +24275,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1462 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1466 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 886, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 889, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24218,9 +24292,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1463 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
+    // Pos:1467 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24236,9 +24310,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1464 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1468 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 887, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24253,9 +24327,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1465 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1469 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 891, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24269,9 +24343,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1466 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1470 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 888, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 891, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24285,9 +24359,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1467 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
+    // Pos:1471 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 889, 
+        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 892, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24301,9 +24375,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1468 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1472 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 890, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 893, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24318,9 +24392,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1469 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1473 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 890, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 893, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24334,9 +24408,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1470 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1474 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 891, 
+        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 894, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24351,9 +24425,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1471 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1475 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 892, 
+        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 895, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24368,9 +24442,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1472 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1476 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 893, 
+        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 896, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24385,9 +24459,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1473 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1477 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 894, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 897, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24402,9 +24476,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1474 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
+    // Pos:1478 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 894, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 897, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24418,9 +24492,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1475 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1479 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 895, 
+        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 898, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24435,9 +24509,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1476 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1480 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 896, 
+        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 899, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24452,9 +24526,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1477 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1481 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 897, 
+        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 900, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24469,9 +24543,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1478 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1482 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 898, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 901, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24485,9 +24559,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1479 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1483 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 898, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 901, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24501,9 +24575,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1480 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
+    // Pos:1484 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 899, 
+        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24517,9 +24591,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1481 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1485 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 900, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 903, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24533,9 +24607,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1482 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1486 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 900, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 903, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24549,9 +24623,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1483 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
+    // Pos:1487 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 901, 
+        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 904, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24565,9 +24639,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1484 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1488 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 
+        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 905, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24582,9 +24656,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1485 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1489 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 903, 
+        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 906, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24599,9 +24673,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1486 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1490 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 904, 
+        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 907, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24616,9 +24690,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1487 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1491 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 905, 
+        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 908, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24633,9 +24707,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1488 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
+    // Pos:1492 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 906, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 909, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24650,9 +24724,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1489 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
+    // Pos:1493 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 906, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 909, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24667,9 +24741,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1490 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
+    // Pos:1494 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 907, 
+        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 910, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24684,9 +24758,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1491 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
+    // Pos:1495 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
     {
-        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 908, 
+        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 911, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -24703,9 +24777,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1492 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
+    // Pos:1496 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 909, 
+        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 912, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24721,9 +24795,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1493 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1497 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 909, 
+        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 912, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24738,9 +24812,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1494 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
+    // Pos:1498 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 910, 
+        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24756,9 +24830,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1495 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1499 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 910, 
+        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24773,9 +24847,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1496 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
+    // Pos:1500 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 911, 
+        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 914, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24791,9 +24865,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1497 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1501 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 911, 
+        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 914, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24808,9 +24882,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1498 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
+    // Pos:1502 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 912, 
+        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 915, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24826,9 +24900,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1499 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1503 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 912, 
+        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 915, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24843,9 +24917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1500 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:1504 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 913, 
+        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 916, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -24861,9 +24935,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1501 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
+    // Pos:1505 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
     {
-        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 914, 
+        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 917, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24879,9 +24953,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1502 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
+    // Pos:1506 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
     {
-        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 915, 
+        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 918, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24897,9 +24971,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1503 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
+    // Pos:1507 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
     {
-        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 916, 
+        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 919, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -24913,9 +24987,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1504 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
+    // Pos:1508 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
     {
-        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 917, 
+        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 920, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -24929,9 +25003,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1505 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
+    // Pos:1509 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 918, 
+        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 921, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -24946,9 +25020,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1506 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
+    // Pos:1510 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 919, 
+        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 922, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -24963,9 +25037,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1507 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
+    // Pos:1511 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 920, 
+        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 923, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24980,9 +25054,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1508 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
+    // Pos:1512 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 921, 
+        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 924, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24997,9 +25071,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1509 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
+    // Pos:1513 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 922, 
+        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 925, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25014,9 +25088,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1510 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
+    // Pos:1514 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 923, 
+        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 926, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25032,9 +25106,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1511 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
+    // Pos:1515 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 924, 
+        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 927, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25050,9 +25124,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1512 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
+    // Pos:1516 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 925, 
+        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25068,9 +25142,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1513 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
+    // Pos:1517 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 926, 
+        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 929, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25086,9 +25160,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1514 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
+    // Pos:1518 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 927, 
+        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 930, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -25103,9 +25177,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1515 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
+    // Pos:1519 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 928, 
+        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 931, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25121,9 +25195,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1516 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
+    // Pos:1520 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 929, 
+        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 932, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25139,9 +25213,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1517 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
+    // Pos:1521 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 930, 
+        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 933, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25157,9 +25231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1518 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
+    // Pos:1522 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 931, 
+        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 934, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25175,9 +25249,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1519 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1523 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 932, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25192,9 +25266,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1520 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1524 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 932, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25209,9 +25283,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1521 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1525 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 932, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25226,9 +25300,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1522 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1526 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 932, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25243,9 +25317,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1523 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
+    // Pos:1527 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 933, 
+        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 936, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25262,9 +25336,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1524 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
+    // Pos:1528 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 934, 
+        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 937, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25281,9 +25355,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1525 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
+    // Pos:1529 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 935, 
+        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 938, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25300,9 +25374,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1526 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
+    // Pos:1530 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 936, 
+        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 939, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25319,9 +25393,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1527 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
+    // Pos:1531 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 937, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 940, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25337,9 +25411,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1528 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
+    // Pos:1532 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 937, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 940, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25354,9 +25428,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1529 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
+    // Pos:1533 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 938, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 941, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25372,9 +25446,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1530 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
+    // Pos:1534 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 938, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 941, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25389,9 +25463,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1531 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
+    // Pos:1535 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 939, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25407,9 +25481,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1532 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
+    // Pos:1536 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 939, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 942, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25424,9 +25498,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1533 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
+    // Pos:1537 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 940, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25442,9 +25516,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1534 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
+    // Pos:1538 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 940, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 943, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25459,9 +25533,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1535 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
+    // Pos:1539 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 941, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25477,9 +25551,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1536 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
+    // Pos:1540 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 941, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25494,9 +25568,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1537 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
+    // Pos:1541 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 945, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25512,9 +25586,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1538 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
+    // Pos:1542 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 942, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 945, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25529,9 +25603,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1539 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
+    // Pos:1543 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25547,9 +25621,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1540 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
+    // Pos:1544 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 943, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25564,9 +25638,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1541 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
+    // Pos:1545 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 944, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25582,9 +25656,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1542 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
+    // Pos:1546 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 944, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25599,9 +25673,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1543 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
+    // Pos:1547 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 945, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 948, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25617,9 +25691,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1544 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
+    // Pos:1548 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 945, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 948, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25634,9 +25708,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1545 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
+    // Pos:1549 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 946, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25652,9 +25726,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1546 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
+    // Pos:1550 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 946, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25669,9 +25743,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1547 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
+    // Pos:1551 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 947, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 950, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25687,9 +25761,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1548 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
+    // Pos:1552 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 947, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 950, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25704,9 +25778,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1549 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
+    // Pos:1553 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 948, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25722,9 +25796,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1550 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
+    // Pos:1554 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 948, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25739,9 +25813,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1551 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
+    // Pos:1555 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 949, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 952, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25757,9 +25831,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1552 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
+    // Pos:1556 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 949, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 952, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25775,9 +25849,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1553 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
+    // Pos:1557 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 950, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 953, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25793,9 +25867,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1554 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
+    // Pos:1558 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 950, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 953, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25811,9 +25885,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1555 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
+    // Pos:1559 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 951, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 954, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25829,9 +25903,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1556 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
+    // Pos:1560 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 951, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 954, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25847,9 +25921,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1557 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
+    // Pos:1561 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 952, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 955, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25865,9 +25939,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1558 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
+    // Pos:1562 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 952, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 955, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25883,9 +25957,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1559 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
+    // Pos:1563 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 953, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 956, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25901,9 +25975,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1560 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
+    // Pos:1564 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 953, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 956, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25918,9 +25992,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1561 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
+    // Pos:1565 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 954, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 957, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25936,9 +26010,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1562 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
+    // Pos:1566 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 954, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 957, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25953,9 +26027,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1563 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
+    // Pos:1567 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 955, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 958, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25971,9 +26045,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1564 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
+    // Pos:1568 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 955, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 958, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25988,9 +26062,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1565 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
+    // Pos:1569 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 956, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 959, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26006,9 +26080,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1566 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
+    // Pos:1570 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 956, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 959, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26023,9 +26097,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1567 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
+    // Pos:1571 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 957, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 960, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26041,9 +26115,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1568 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
+    // Pos:1572 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 957, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 960, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26058,9 +26132,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1569 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
+    // Pos:1573 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 958, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26076,9 +26150,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1570 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
+    // Pos:1574 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 958, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26093,9 +26167,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1571 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
+    // Pos:1575 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 959, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26111,9 +26185,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1572 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
+    // Pos:1576 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 959, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26129,9 +26203,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1573 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
+    // Pos:1577 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 960, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 963, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26147,9 +26221,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1574 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
+    // Pos:1578 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 960, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 963, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26165,9 +26239,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1575 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
+    // Pos:1579 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 961, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 964, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26183,9 +26257,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1576 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
+    // Pos:1580 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 961, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 964, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26200,9 +26274,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1577 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
+    // Pos:1581 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 962, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26218,9 +26292,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1578 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
+    // Pos:1582 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 962, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26235,9 +26309,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1579 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
+    // Pos:1583 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 963, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 966, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26253,9 +26327,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1580 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
+    // Pos:1584 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 963, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 966, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26270,9 +26344,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1581 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
+    // Pos:1585 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 964, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 967, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26288,9 +26362,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1582 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
+    // Pos:1586 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 964, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 967, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26305,9 +26379,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1583 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
+    // Pos:1587 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 965, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 968, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26323,9 +26397,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1584 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
+    // Pos:1588 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 965, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 968, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26340,9 +26414,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1585 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
+    // Pos:1589 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 966, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26358,9 +26432,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1586 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
+    // Pos:1590 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 966, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26375,9 +26449,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1587 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
+    // Pos:1591 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 967, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26393,9 +26467,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1588 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
+    // Pos:1592 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 967, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 970, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26410,9 +26484,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1589 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
+    // Pos:1593 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 968, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26428,9 +26502,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1590 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
+    // Pos:1594 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 968, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 971, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26445,9 +26519,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1591 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
+    // Pos:1595 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 969, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26463,9 +26537,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1592 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
+    // Pos:1596 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 969, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 972, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26480,9 +26554,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1593 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
+    // Pos:1597 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26498,9 +26572,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1594 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
+    // Pos:1598 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 970, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 973, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26515,9 +26589,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1595 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
+    // Pos:1599 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 974, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26533,9 +26607,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1596 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
+    // Pos:1600 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 971, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 974, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26550,9 +26624,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1597 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
+    // Pos:1601 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 975, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26568,9 +26642,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1598 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
+    // Pos:1602 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 972, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 975, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26585,9 +26659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1599 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
+    // Pos:1603 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 976, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26603,9 +26677,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1600 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
+    // Pos:1604 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 973, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 976, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26620,9 +26694,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1601 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
+    // Pos:1605 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 974, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26638,9 +26712,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1602 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
+    // Pos:1606 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 974, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26655,9 +26729,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1603 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
+    // Pos:1607 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 975, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 978, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26673,9 +26747,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1604 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
+    // Pos:1608 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 975, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 978, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26690,9 +26764,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1605 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
+    // Pos:1609 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 976, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 979, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26708,9 +26782,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1606 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
+    // Pos:1610 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 976, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 979, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26725,9 +26799,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1607 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
+    // Pos:1611 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 977, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 980, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26743,9 +26817,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1608 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
+    // Pos:1612 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 977, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 980, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26760,9 +26834,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1609 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
+    // Pos:1613 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 978, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 981, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26778,9 +26852,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1610 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
+    // Pos:1614 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 978, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 981, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26795,9 +26869,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1611 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
+    // Pos:1615 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 979, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 982, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26813,9 +26887,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1612 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
+    // Pos:1616 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 979, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 982, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26831,9 +26905,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1613 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
+    // Pos:1617 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 980, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26849,9 +26923,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1614 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
+    // Pos:1618 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 980, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26867,9 +26941,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1615 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
+    // Pos:1619 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 981, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 984, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26885,9 +26959,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1616 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
+    // Pos:1620 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 981, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 984, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26903,9 +26977,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1617 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
+    // Pos:1621 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 982, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26921,9 +26995,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1618 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
+    // Pos:1622 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 982, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26939,9 +27013,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1619 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
+    // Pos:1623 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 983, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26957,9 +27031,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1620 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
+    // Pos:1624 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 983, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26975,9 +27049,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1621 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
+    // Pos:1625 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 984, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 987, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26993,9 +27067,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1622 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
+    // Pos:1626 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 984, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 987, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27011,9 +27085,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1623 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
+    // Pos:1627 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 985, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27029,9 +27103,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1624 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
+    // Pos:1628 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 985, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27046,9 +27120,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1625 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
+    // Pos:1629 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 986, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27064,9 +27138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1626 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
+    // Pos:1630 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 986, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 989, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27081,9 +27155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1627 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
+    // Pos:1631 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 987, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 990, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27099,9 +27173,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1628 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
+    // Pos:1632 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 987, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 990, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27116,9 +27190,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1629 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
+    // Pos:1633 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 991, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27134,9 +27208,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1630 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
+    // Pos:1634 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 988, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 991, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27151,9 +27225,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1631 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
+    // Pos:1635 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 992, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27169,9 +27243,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1632 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
+    // Pos:1636 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 989, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 992, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27186,9 +27260,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1633 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
+    // Pos:1637 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 990, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 993, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27204,9 +27278,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1634 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
+    // Pos:1638 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 990, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 993, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27221,9 +27295,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1635 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
+    // Pos:1639 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 991, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 994, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27239,9 +27313,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1636 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
+    // Pos:1640 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 991, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 994, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27256,9 +27330,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1637 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
+    // Pos:1641 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 992, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 995, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27274,9 +27348,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1638 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
+    // Pos:1642 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 992, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 995, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27291,9 +27365,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1639 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
+    // Pos:1643 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 993, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 996, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27309,9 +27383,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1640 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
+    // Pos:1644 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 993, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 996, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27326,9 +27400,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1641 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
+    // Pos:1645 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 994, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 997, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27344,9 +27418,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1642 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
+    // Pos:1646 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 994, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 997, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27361,9 +27435,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1643 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
+    // Pos:1647 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 995, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 998, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27379,9 +27453,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1644 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
+    // Pos:1648 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 995, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 998, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27396,9 +27470,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1645 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
+    // Pos:1649 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 996, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 999, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27414,9 +27488,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1646 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
+    // Pos:1650 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 996, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 999, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27431,9 +27505,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1647 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
+    // Pos:1651 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 997, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27449,9 +27523,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1648 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
+    // Pos:1652 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 997, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27467,9 +27541,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1649 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
+    // Pos:1653 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 998, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1001, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27485,9 +27559,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1650 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
+    // Pos:1654 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 998, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1001, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27503,9 +27577,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1651 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
+    // Pos:1655 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 999, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1002, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27521,9 +27595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1652 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
+    // Pos:1656 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 999, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1002, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27539,9 +27613,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1653 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
+    // Pos:1657 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1003, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27557,9 +27631,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1654 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
+    // Pos:1658 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1003, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27575,9 +27649,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1655 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
+    // Pos:1659 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1001, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1004, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27593,9 +27667,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1656 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
+    // Pos:1660 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1001, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1004, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27610,9 +27684,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1657 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
+    // Pos:1661 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1002, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1005, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27628,9 +27702,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1658 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
+    // Pos:1662 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1002, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1005, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27645,9 +27719,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1659 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
+    // Pos:1663 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1003, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1006, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27663,9 +27737,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1660 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
+    // Pos:1664 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1003, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1006, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27680,9 +27754,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1661 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
+    // Pos:1665 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1004, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1007, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27698,9 +27772,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1662 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
+    // Pos:1666 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1004, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1007, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27715,9 +27789,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1663 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
+    // Pos:1667 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1005, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27733,9 +27807,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1664 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
+    // Pos:1668 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1005, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27750,9 +27824,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1665 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
+    // Pos:1669 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1006, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1009, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27768,9 +27842,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1666 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
+    // Pos:1670 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1006, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1009, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27785,9 +27859,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1667 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
+    // Pos:1671 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1007, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1010, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27803,9 +27877,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1668 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
+    // Pos:1672 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1007, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1010, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27820,9 +27894,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1669 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
+    // Pos:1673 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1008, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1011, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27838,9 +27912,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1670 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
+    // Pos:1674 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1008, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1011, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27855,9 +27929,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1671 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
+    // Pos:1675 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1009, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1012, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27873,9 +27947,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1672 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
+    // Pos:1676 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1009, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1012, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27890,9 +27964,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1673 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
+    // Pos:1677 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1010, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1013, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27908,9 +27982,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1674 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
+    // Pos:1678 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1010, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1013, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27925,9 +27999,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1675 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
+    // Pos:1679 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1011, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1014, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27943,9 +28017,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1676 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
+    // Pos:1680 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1011, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1014, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27960,9 +28034,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1677 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
+    // Pos:1681 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1012, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1015, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27978,9 +28052,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1678 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
+    // Pos:1682 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1012, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1015, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27995,9 +28069,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1679 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
+    // Pos:1683 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1013, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1016, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28013,9 +28087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1680 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
+    // Pos:1684 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1013, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1016, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28031,9 +28105,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1681 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
+    // Pos:1685 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1014, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1017, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28049,9 +28123,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1682 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
+    // Pos:1686 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1014, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1017, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28067,9 +28141,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1683 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
+    // Pos:1687 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1015, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1018, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28085,9 +28159,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1684 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
+    // Pos:1688 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1015, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1018, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28103,9 +28177,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1685 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
+    // Pos:1689 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1016, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1019, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28121,9 +28195,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1686 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
+    // Pos:1690 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1016, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1019, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28139,9 +28213,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1687 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
+    // Pos:1691 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1017, 
+        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1020, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28157,9 +28231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1688 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
+    // Pos:1692 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1018, 
+        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1021, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28175,9 +28249,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1689 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
+    // Pos:1693 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1019, 
+        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1022, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28193,9 +28267,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1690 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
+    // Pos:1694 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1020, 
+        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1023, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28211,9 +28285,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1691 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
+    // Pos:1695 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
     {
-        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1021, 
+        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1024, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -28227,9 +28301,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1692 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
+    // Pos:1696 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
     {
-        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1022, 
+        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1025, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -28243,9 +28317,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1693 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
+    // Pos:1697 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
     {
-        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1023, 
+        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1026, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -28259,9 +28333,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1694 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
+    // Pos:1698 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
     {
-        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1024, 
+        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1027, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -28275,9 +28349,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1695 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
+    // Pos:1699 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1025, 
+        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1028, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28292,9 +28366,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1696 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
+    // Pos:1700 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1025, 
+        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1028, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28309,9 +28383,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1697 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
+    // Pos:1701 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1026, 
+        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1029, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28326,9 +28400,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1698 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
+    // Pos:1702 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1026, 
+        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1029, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28343,9 +28417,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1699 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
+    // Pos:1703 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1027, 
+        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1030, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28359,9 +28433,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1700 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
+    // Pos:1704 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1028, 
+        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1031, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28375,9 +28449,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1701 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
+    // Pos:1705 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1029, 
+        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1032, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28391,9 +28465,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1702 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
+    // Pos:1706 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1030, 
+        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1033, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28407,9 +28481,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1703 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
+    // Pos:1707 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1031, 
+        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1034, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28423,9 +28497,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1704 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
+    // Pos:1708 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1032, 
+        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1035, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28439,9 +28513,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1705 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
+    // Pos:1709 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1033, 
+        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1036, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28455,9 +28529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1706 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
+    // Pos:1710 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1034, 
+        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1037, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28471,9 +28545,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1707 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
+    // Pos:1711 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1035, 
+        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1038, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28488,9 +28562,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1708 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
+    // Pos:1712 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1035, 
+        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1038, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28505,9 +28579,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1709 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
+    // Pos:1713 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1036, 
+        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1039, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28522,9 +28596,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1710 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
+    // Pos:1714 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1036, 
+        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1039, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28539,9 +28613,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1711 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
+    // Pos:1715 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1037, 
+        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1040, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28556,9 +28630,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1712 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
+    // Pos:1716 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1038, 
+        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1041, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28573,9 +28647,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1713 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
+    // Pos:1717 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 
+        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1042, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28591,9 +28665,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1714 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
+    // Pos:1718 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1040, 
+        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28609,9 +28683,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1715 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
+    // Pos:1719 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1041, 
+        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1044, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28627,9 +28701,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1716 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
+    // Pos:1720 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1042, 
+        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1045, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28645,9 +28719,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1717 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
+    // Pos:1721 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 
+        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1046, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28664,9 +28738,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1718 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
+    // Pos:1722 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1044, 
+        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1047, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28683,9 +28757,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1719 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
+    // Pos:1723 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1045, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1048, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28702,9 +28776,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1720 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
+    // Pos:1724 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1045, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1048, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28720,9 +28794,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1721 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
+    // Pos:1725 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1046, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1049, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28739,9 +28813,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1722 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
+    // Pos:1726 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1046, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1049, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28757,9 +28831,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1723 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
+    // Pos:1727 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1047, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1050, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28775,9 +28849,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1724 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
+    // Pos:1728 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1047, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1050, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28792,9 +28866,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1725 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1729 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1048, 
+        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1051, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28809,9 +28883,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1726 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1730 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1049, 
+        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1052, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28826,9 +28900,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1727 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1731 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1050, 
+        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1053, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28843,9 +28917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1728 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1732 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1051, 
+        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1054, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28860,9 +28934,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1729 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
+    // Pos:1733 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1052, 
+        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1055, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28878,9 +28952,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1730 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
+    // Pos:1734 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1053, 
+        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1056, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28897,9 +28971,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1731 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
+    // Pos:1735 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1054, 
+        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1057, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28916,9 +28990,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1732 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
+    // Pos:1736 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1055, 
+        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28935,9 +29009,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1733 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
+    // Pos:1737 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1056, 
+        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1059, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28954,9 +29028,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1734 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
+    // Pos:1738 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1057, 
+        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1060, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -28972,9 +29046,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1735 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
+    // Pos:1739 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1058, 
+        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1061, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28991,9 +29065,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1736 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
+    // Pos:1740 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1059, 
+        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1062, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -29010,9 +29084,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1737 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
+    // Pos:1741 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1060, 
+        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1063, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -29029,9 +29103,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1738 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
+    // Pos:1742 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1061, 
+        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1064, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29048,9 +29122,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1739 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1743 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1062, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29066,9 +29140,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1740 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1744 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1062, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29084,9 +29158,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1741 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1745 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1062, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29102,9 +29176,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1742 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1746 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1062, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29120,9 +29194,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1743 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
+    // Pos:1747 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
     {
-        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1063, 
+        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1066, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29136,9 +29210,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1744 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
+    // Pos:1748 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
     {
-        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1064, 
+        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1067, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -29152,9 +29226,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1745 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
+    // Pos:1749 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
     {
-        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1065, 
+        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1068, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29169,9 +29243,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1746 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
+    // Pos:1750 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1066, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1069, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29186,9 +29260,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1747 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
+    // Pos:1751 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1066, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1069, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29203,9 +29277,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1748 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
+    // Pos:1752 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1067, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1070, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29220,9 +29294,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1749 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
+    // Pos:1753 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1067, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1070, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29237,9 +29311,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1750 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
+    // Pos:1754 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1068, 
+        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1071, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29255,9 +29329,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1751 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1755 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1068, 
+        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1071, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29272,9 +29346,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1752 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
+    // Pos:1756 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1069, 
+        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29290,9 +29364,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1753 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1757 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1069, 
+        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29307,9 +29381,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1754 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
+    // Pos:1758 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1070, 
+        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29325,9 +29399,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1755 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1759 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1070, 
+        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29342,9 +29416,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1756 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
+    // Pos:1760 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1071, 
+        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1074, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29360,9 +29434,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1757 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1761 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1071, 
+        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1074, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29377,9 +29451,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1758 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
+    // Pos:1762 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
     {
-        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1072, 
+        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1075, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29392,9 +29466,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1759 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1763 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1073, 
+        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1076, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29408,9 +29482,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1760 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
+    // Pos:1764 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
     {
-        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1074, 
+        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1077, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29423,9 +29497,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1761 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
+    // Pos:1765 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1075, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29438,9 +29512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1762 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
+    // Pos:1766 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1075, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29453,9 +29527,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1763 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
+    // Pos:1767 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1076, 
+        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29471,9 +29545,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1764 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1768 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1076, 
+        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29488,9 +29562,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1765 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
+    // Pos:1769 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1077, 
+        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29506,9 +29580,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1766 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1770 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1077, 
+        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29523,9 +29597,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1767 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
+    // Pos:1771 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1078, 
+        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29541,9 +29615,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1768 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1772 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1078, 
+        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29558,9 +29632,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1769 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
+    // Pos:1773 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1079, 
+        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29576,9 +29650,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1770 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1774 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1079, 
+        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29593,9 +29667,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1771 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
+    // Pos:1775 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
     {
-        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1080, 
+        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1083, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29608,9 +29682,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1772 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
+    // Pos:1776 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
     {
-        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1081, 
+        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1084, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29623,9 +29697,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1773 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
+    // Pos:1777 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1082, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1085, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29638,9 +29712,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1774 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
+    // Pos:1778 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1082, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1085, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29653,9 +29727,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1775 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+    // Pos:1779 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1083, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29670,9 +29744,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1776 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
+    // Pos:1780 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1083, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29687,9 +29761,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1777 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
+    // Pos:1781 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1083, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29703,9 +29777,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1778 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
+    // Pos:1782 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1083, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29719,9 +29793,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1779 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
+    // Pos:1783 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29736,9 +29810,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1780 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
+    // Pos:1784 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29753,9 +29827,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1781 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
+    // Pos:1785 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29769,9 +29843,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1782 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
+    // Pos:1786 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29785,9 +29859,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1783 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1787 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29801,9 +29875,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1784 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1788 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29817,9 +29891,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1785 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1789 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29833,9 +29907,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1786 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1790 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29849,9 +29923,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1787 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
+    // Pos:1791 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29866,9 +29940,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1788 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
+    // Pos:1792 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29883,9 +29957,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1789 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
+    // Pos:1793 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29900,9 +29974,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1790 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
+    // Pos:1794 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29916,9 +29990,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1791 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
+    // Pos:1795 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29932,9 +30006,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1792 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
+    // Pos:1796 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29948,9 +30022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1793 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
+    // Pos:1797 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29964,9 +30038,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1794 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1798 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29981,9 +30055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1795 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1799 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29998,9 +30072,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1796 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1800 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30015,9 +30089,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1797 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1801 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30032,9 +30106,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1798 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
+    // Pos:1802 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30048,9 +30122,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1799 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
+    // Pos:1803 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30064,9 +30138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1800 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1804 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1091, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1094, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -30081,9 +30155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1801 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1805 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1091, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1094, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -30098,9 +30172,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1802 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1806 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30115,9 +30189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1803 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1807 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30132,9 +30206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1804 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1808 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30149,9 +30223,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1805 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1809 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30166,9 +30240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1806 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1810 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1094, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1097, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -30183,9 +30257,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1807 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1811 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1094, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1097, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -30200,9 +30274,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1808 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
+    // Pos:1812 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
+        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30217,9 +30291,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1809 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
+    // Pos:1813 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1095, 
+        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1098, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30234,9 +30308,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1810 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
+    // Pos:1814 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30251,9 +30325,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1811 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
+    // Pos:1815 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30267,9 +30341,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1812 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1816 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30284,9 +30358,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1813 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1817 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30300,9 +30374,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1814 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
+    // Pos:1818 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1097, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30317,9 +30391,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1815 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
+    // Pos:1819 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1097, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30333,9 +30407,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1816 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1820 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1097, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30350,9 +30424,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1817 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1821 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1097, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30366,9 +30440,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1818 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
+    // Pos:1822 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 
+        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30383,9 +30457,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1819 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
+    // Pos:1823 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1098, 
+        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30400,9 +30474,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1820 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
+    // Pos:1824 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30417,9 +30491,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1821 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
+    // Pos:1825 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30433,9 +30507,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1822 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1826 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30450,9 +30524,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1823 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1827 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30466,9 +30540,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1824 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
+    // Pos:1828 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30483,9 +30557,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1825 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
+    // Pos:1829 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30499,9 +30573,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1826 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1830 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1100, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30516,9 +30590,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1827 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1831 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1100, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30532,9 +30606,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1828 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1832 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1101, 
+        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30548,9 +30622,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1829 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1833 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1102, 
+        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1105, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30564,9 +30638,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1830 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
+    // Pos:1834 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
+        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30580,9 +30654,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1831 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
+    // Pos:1835 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1103, 
+        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30596,9 +30670,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1832 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
+    // Pos:1836 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, 
+        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30612,9 +30686,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1833 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
+    // Pos:1837 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1104, 
+        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30628,9 +30702,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1834 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
+    // Pos:1838 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1105, 
+        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30644,9 +30718,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1835 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1839 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1105, 
+        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30660,9 +30734,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1836 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
+    // Pos:1840 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1106, 
+        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30676,9 +30750,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1837 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1841 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1106, 
+        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30692,9 +30766,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1838 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1842 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30708,9 +30782,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1839 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1843 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30724,9 +30798,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1840 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
+    // Pos:1844 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30740,9 +30814,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1841 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
+    // Pos:1845 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30756,9 +30830,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1842 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1846 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30772,9 +30846,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1843 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1847 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30788,9 +30862,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1844 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
+    // Pos:1848 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30804,9 +30878,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1845 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
+    // Pos:1849 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30820,9 +30894,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1846 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
+    // Pos:1850 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30837,9 +30911,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1847 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
+    // Pos:1851 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30855,9 +30929,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1848 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
+    // Pos:1852 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30872,9 +30946,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1849 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
+    // Pos:1853 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30890,9 +30964,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1850 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1854 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30907,9 +30981,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1851 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1855 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30923,9 +30997,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1852 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1856 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30940,9 +31014,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1853 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1857 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30956,9 +31030,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1854 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
+    // Pos:1858 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 
+        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1112, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30973,9 +31047,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1855 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
+    // Pos:1859 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1109, 
+        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1112, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30989,9 +31063,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1856 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
+    // Pos:1860 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 
+        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31006,9 +31080,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1857 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
+    // Pos:1861 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1110, 
+        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1113, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31022,9 +31096,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1858 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+    // Pos:1862 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31039,9 +31113,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1859 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+    // Pos:1863 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31057,9 +31131,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1860 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+    // Pos:1864 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31074,9 +31148,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1861 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+    // Pos:1865 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31092,9 +31166,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1862 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1866 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31109,9 +31183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1863 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1867 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31125,9 +31199,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1864 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1868 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31142,9 +31216,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1865 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1869 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1111, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31158,9 +31232,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1866 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
+    // Pos:1870 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1112, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31175,9 +31249,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1867 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
+    // Pos:1871 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1112, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31192,9 +31266,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1868 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
+    // Pos:1872 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1112, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31208,9 +31282,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1869 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
+    // Pos:1873 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1112, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31224,9 +31298,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1870 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
+    // Pos:1874 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31241,9 +31315,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1871 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
+    // Pos:1875 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31258,9 +31332,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1872 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
+    // Pos:1876 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31274,9 +31348,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1873 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
+    // Pos:1877 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31290,9 +31364,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1874 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
+    // Pos:1878 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
     {
-        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1114, 
+        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31308,9 +31382,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1875 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1879 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1115, 
+        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1118, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31324,9 +31398,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1876 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
+    // Pos:1880 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
     {
-        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1116, 
+        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1119, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31340,9 +31414,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1877 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
+    // Pos:1881 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
     {
-        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1117, 
+        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1120, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31357,9 +31431,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1878 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
+    // Pos:1882 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
     {
-        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1118, 
+        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1121, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31372,9 +31446,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1879 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
+    // Pos:1883 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
     {
-        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1119, 
+        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1122, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31387,9 +31461,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1880 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
+    // Pos:1884 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
     {
-        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1120, 
+        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1123, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31402,9 +31476,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1881 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
+    // Pos:1885 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1121, 
+        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31420,9 +31494,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1882 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1886 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1121, 
+        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31437,9 +31511,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1883 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
+    // Pos:1887 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1122, 
+        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1125, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31455,9 +31529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1884 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1888 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1122, 
+        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1125, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31472,9 +31546,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1885 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
+    // Pos:1889 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1123, 
+        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1126, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31490,9 +31564,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1886 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1890 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1123, 
+        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1126, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31507,9 +31581,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1887 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
+    // Pos:1891 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1124, 
+        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1127, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31525,9 +31599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1888 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1892 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1124, 
+        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1127, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31542,9 +31616,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1889 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
+    // Pos:1893 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
     {
-        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1125, 
+        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1128, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31559,9 +31633,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1890 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
+    // Pos:1894 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
     {
-        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1126, 
+        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1129, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31574,9 +31648,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1891 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1895 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1127, 
+        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1130, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31590,9 +31664,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1892 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
+    // Pos:1896 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1128, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1131, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31608,9 +31682,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1893 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1897 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1128, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1131, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31625,9 +31699,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1894 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:1898 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1129, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1132, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31643,9 +31717,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1895 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1899 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1129, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1132, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31660,9 +31734,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1896 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
+    // Pos:1900 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1130, 
+        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1133, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -31677,9 +31751,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1897 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
+    // Pos:1901 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1131, 
+        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1134, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -31694,9 +31768,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1898 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
+    // Pos:1902 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1132, 
+        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1135, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -31712,9 +31786,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1899 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
+    // Pos:1903 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1133, 
+        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1136, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -31730,9 +31804,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1900 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
+    // Pos:1904 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, 
+        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1137, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31747,9 +31821,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1901 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
+    // Pos:1905 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1134, 
+        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1137, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31763,9 +31837,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1902 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
+    // Pos:1906 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1135, 
+        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1138, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31780,9 +31854,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1903 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
+    // Pos:1907 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1135, 
+        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1138, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31796,9 +31870,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1904 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
+    // Pos:1908 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
     {
-        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1136, 
+        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1139, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31813,9 +31887,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1905 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
+    // Pos:1909 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1137, 
+        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1140, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31830,9 +31904,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1906 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
+    // Pos:1910 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1137, 
+        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1140, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31846,9 +31920,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1907 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
+    // Pos:1911 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1138, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31864,9 +31938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1908 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
+    // Pos:1912 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1138, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31881,9 +31955,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1909 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
+    // Pos:1913 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1139, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31899,9 +31973,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1910 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
+    // Pos:1914 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1139, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31916,9 +31990,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1911 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
+    // Pos:1915 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1140, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1143, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31934,9 +32008,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1912 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
+    // Pos:1916 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1140, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1143, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31951,9 +32025,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1913 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
+    // Pos:1917 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1141, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1144, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31969,9 +32043,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1914 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
+    // Pos:1918 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1141, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1144, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31986,9 +32060,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1915 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
+    // Pos:1919 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, 
+        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1145, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32004,9 +32078,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1916 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
+    // Pos:1920 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1142, 
+        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1145, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32021,9 +32095,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1917 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
+    // Pos:1921 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1143, 
+        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32039,9 +32113,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1918 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
+    // Pos:1922 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1143, 
+        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32056,9 +32130,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1919 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
+    // Pos:1923 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1144, 
+        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1147, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32074,9 +32148,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1920 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
+    // Pos:1924 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1144, 
+        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1147, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32091,9 +32165,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1921 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
+    // Pos:1925 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1145, 
+        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32109,9 +32183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1922 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
+    // Pos:1926 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1145, 
+        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32126,9 +32200,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1923 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
+    // Pos:1927 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1146, 
+        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1149, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32144,9 +32218,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1924 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
+    // Pos:1928 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1146, 
+        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1149, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32161,9 +32235,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1925 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
+    // Pos:1929 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1147, 
+        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1150, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32179,9 +32253,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1926 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1930 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1147, 
+        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1150, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32196,9 +32270,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1927 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
+    // Pos:1931 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1148, 
+        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1151, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32214,9 +32288,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1928 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1932 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1148, 
+        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1151, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32231,9 +32305,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1929 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
+    // Pos:1933 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1149, 
+        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1152, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32249,9 +32323,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1930 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
+    // Pos:1934 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1149, 
+        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1152, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32266,9 +32340,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1931 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
+    // Pos:1935 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1150, 
+        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1153, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32285,9 +32359,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1932 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
+    // Pos:1936 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1150, 
+        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1153, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32303,9 +32377,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1933 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
+    // Pos:1937 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
     {
-        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1151, 
+        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1154, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32320,9 +32394,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1934 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
+    // Pos:1938 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1152, 
+        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1155, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32338,9 +32412,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1935 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1939 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1153, 
+        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1156, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32355,9 +32429,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1936 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
+    // Pos:1940 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1154, 
+        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1157, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32373,9 +32447,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1937 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
+    // Pos:1941 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1155, 
+        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1158, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32391,9 +32465,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1938 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
+    // Pos:1942 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1156, 
+        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1159, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32409,9 +32483,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1939 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
+    // Pos:1943 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1157, 
+        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1160, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32427,9 +32501,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1940 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
+    // Pos:1944 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1157, 
+        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1160, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32444,9 +32518,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1941 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
+    // Pos:1945 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1158, 
+        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1161, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32462,9 +32536,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1942 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
+    // Pos:1946 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1158, 
+        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1161, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32479,9 +32553,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1943 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
+    // Pos:1947 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1159, 
+        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1162, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32497,9 +32571,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1944 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1948 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1160, 
+        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1163, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32515,9 +32589,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1945 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
+    // Pos:1949 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1161, 
+        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1164, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32533,9 +32607,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1946 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
+    // Pos:1950 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1162, 
+        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1165, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32551,9 +32625,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1947 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
+    // Pos:1951 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1163, 
+        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32569,9 +32643,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1948 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
+    // Pos:1952 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
     {
-        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1164, 
+        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32587,9 +32661,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1949 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
+    // Pos:1953 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1165, 
+        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1168, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32605,9 +32679,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1950 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1954 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1166, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32622,9 +32696,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1951 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
+    // Pos:1955 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1166, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32639,9 +32713,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1952 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
+    // Pos:1956 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1166, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32655,9 +32729,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1953 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
+    // Pos:1957 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1167, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1170, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32672,9 +32746,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1954 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
+    // Pos:1958 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1167, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1170, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32689,9 +32763,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1955 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
+    // Pos:1959 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1167, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1170, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32705,9 +32779,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1956 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
+    // Pos:1960 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1168, 
+        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1171, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -32721,9 +32795,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1957 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
+    // Pos:1961 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1169, 
+        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1172, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -32737,9 +32811,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1958 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
+    // Pos:1962 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1170, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32754,9 +32828,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1959 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
+    // Pos:1963 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1170, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32771,9 +32845,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1960 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
+    // Pos:1964 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1170, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32787,9 +32861,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1961 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1965 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1171, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32804,9 +32878,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1962 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
+    // Pos:1966 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1171, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32821,9 +32895,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1963 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
+    // Pos:1967 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1171, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32837,9 +32911,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1964 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:1968 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1172, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1175, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -32855,9 +32929,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1965 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:1969 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1172, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1175, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -32873,9 +32947,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1966 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
+    // Pos:1970 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1173, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1176, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -32891,9 +32965,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1967 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
+    // Pos:1971 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1173, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1176, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -32909,9 +32983,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1968 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
+    // Pos:1972 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1174, 
+        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1177, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32928,9 +33002,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1969 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
+    // Pos:1973 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1175, 
+        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32947,9 +33021,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1970 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
+    // Pos:1974 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1176, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1179, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32965,9 +33039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1971 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
+    // Pos:1975 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1176, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1179, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32982,9 +33056,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1972 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
+    // Pos:1976 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1177, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1180, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33000,9 +33074,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1973 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
+    // Pos:1977 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1177, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1180, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33017,9 +33091,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1974 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
+    // Pos:1978 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1181, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33035,9 +33109,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1975 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
+    // Pos:1979 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1178, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1181, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33052,9 +33126,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1976 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
+    // Pos:1980 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1179, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33070,9 +33144,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1977 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
+    // Pos:1981 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1179, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33087,9 +33161,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1978 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
+    // Pos:1982 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1180, 
+        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1183, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33108,9 +33182,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1979 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
+    // Pos:1983 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1181, 
+        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1184, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33129,9 +33203,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1980 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
+    // Pos:1984 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1182, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1185, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33147,9 +33221,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1981 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
+    // Pos:1985 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1182, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1185, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33164,9 +33238,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1982 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1986 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1183, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1186, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33182,9 +33256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1983 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
+    // Pos:1987 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1183, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1186, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33199,9 +33273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1984 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
+    // Pos:1988 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1184, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1187, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33217,9 +33291,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1985 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
+    // Pos:1989 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1184, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1187, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33234,9 +33308,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1986 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
+    // Pos:1990 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1185, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1188, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33252,9 +33326,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1987 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
+    // Pos:1991 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1185, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1188, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33269,9 +33343,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1988 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
+    // Pos:1992 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1186, 
+        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1189, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33288,9 +33362,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1989 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
+    // Pos:1993 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1187, 
+        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1190, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33307,9 +33381,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1990 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
+    // Pos:1994 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1188, 
+        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1191, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33326,9 +33400,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1991 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
+    // Pos:1995 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1189, 
+        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1192, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33345,9 +33419,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1992 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
+    // Pos:1996 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 
+        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1193, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33364,9 +33438,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1993 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
+    // Pos:1997 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1191, 
+        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1194, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33383,9 +33457,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1994 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
+    // Pos:1998 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1192, 
+        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1195, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33402,9 +33476,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1995 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
+    // Pos:1999 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1193, 
+        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1196, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33421,9 +33495,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1996 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
+    // Pos:2000 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1194, 
+        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1197, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33439,9 +33513,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1997 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
+    // Pos:2001 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1195, 
+        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1198, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33457,9 +33531,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1998 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
+    // Pos:2002 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1196, 
+        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1199, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -33474,9 +33548,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:1999 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
+    // Pos:2003 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1197, 
+        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1200, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33491,9 +33565,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2000 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
+    // Pos:2004 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1198, 
+        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1201, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33508,9 +33582,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2001 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
+    // Pos:2005 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1199, 
+        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1202, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -33525,9 +33599,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2002 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
+    // Pos:2006 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1200, 
+        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1203, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33543,9 +33617,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2003 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
+    // Pos:2007 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1201, 
+        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1204, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33561,9 +33635,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2004 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
+    // Pos:2008 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1202, 
+        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1205, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33579,9 +33653,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2005 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
+    // Pos:2009 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1203, 
+        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1206, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33597,9 +33671,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2006 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
+    // Pos:2010 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1204, 
+        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33615,9 +33689,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2007 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
+    // Pos:2011 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
     {
-        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1205, 
+        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33633,9 +33707,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2008 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
+    // Pos:2012 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1206, 
+        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -33650,9 +33724,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2009 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
+    // Pos:2013 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1207, 
+        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -33667,9 +33741,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2010 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
+    // Pos:2014 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1208, 
+        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33685,9 +33759,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2011 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
+    // Pos:2015 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1208, 
+        ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -33702,9 +33776,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2012 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
+    // Pos:2016 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1209, 
+        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1212, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33720,9 +33794,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2013 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
+    // Pos:2017 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1209, 
+        ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1212, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -33737,9 +33811,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2014 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:2018 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1210, 
+        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1213, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33755,9 +33829,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2015 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
+    // Pos:2019 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1210, 
+        ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1213, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -33772,9 +33846,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2016 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
+    // Pos:2020 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1211, 
+        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1214, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33790,9 +33864,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2017 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
+    // Pos:2021 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1211, 
+        ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1214, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -33807,9 +33881,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2018 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+    // Pos:2022 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1212, 
+        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1215, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33825,9 +33899,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2019 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
+    // Pos:2023 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1213, 
+        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1216, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -33843,9 +33917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2020 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
+    // Pos:2024 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1214, 
+        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1217, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -33861,9 +33935,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2021 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
+    // Pos:2025 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1215, 
+        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33879,9 +33953,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2022 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
+    // Pos:2026 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1215, 
+        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -33896,9 +33970,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2023 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
+    // Pos:2027 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1216, 
+        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1219, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -33914,9 +33988,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2024 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
+    // Pos:2028 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1217, 
+        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33932,9 +34006,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2025 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
+    // Pos:2029 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1218, 
+        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33950,9 +34024,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2026 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
+    // Pos:2030 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1219, 
+        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33968,9 +34042,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2027 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
+    // Pos:2031 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1220, 
+        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33986,9 +34060,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2028 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
+    // Pos:2032 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1221, 
+        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34004,9 +34078,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2029 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
+    // Pos:2033 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1222, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1225, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34023,9 +34097,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2030 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
+    // Pos:2034 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1222, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1225, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34042,9 +34116,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2031 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
+    // Pos:2035 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1223, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1226, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34061,9 +34135,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2032 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
+    // Pos:2036 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1223, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1226, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34080,9 +34154,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2033 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
+    // Pos:2037 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1224, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34098,9 +34172,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2034 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
+    // Pos:2038 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1224, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34116,9 +34190,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2035 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
+    // Pos:2039 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1224, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34133,9 +34207,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2036 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
+    // Pos:2040 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1224, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34150,9 +34224,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2037 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
+    // Pos:2041 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1225, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34168,9 +34242,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2038 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
+    // Pos:2042 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1225, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34186,9 +34260,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2039 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
+    // Pos:2043 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1225, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34203,9 +34277,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2040 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
+    // Pos:2044 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1225, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34220,9 +34294,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2041 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
+    // Pos:2045 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34238,9 +34312,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2042 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
+    // Pos:2046 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34256,9 +34330,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2043 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
+    // Pos:2047 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34274,9 +34348,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2044 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
+    // Pos:2048 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1226, 
+        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -34291,9 +34365,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2045 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
+    // Pos:2049 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34309,9 +34383,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2046 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
+    // Pos:2050 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34327,9 +34401,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2047 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
+    // Pos:2051 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1227, 
+        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -34344,9 +34418,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2048 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
+    // Pos:2052 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34362,9 +34436,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2049 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
+    // Pos:2053 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34380,9 +34454,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2050 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
+    // Pos:2054 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1228, 
+        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -34397,9 +34471,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2051 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
+    // Pos:2055 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1229, 
+        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -34415,9 +34489,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2052 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
+    // Pos:2056 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1230, 
+        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34433,9 +34507,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2053 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
+    // Pos:2057 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1231, 
+        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1234, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34451,9 +34525,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2054 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
+    // Pos:2058 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1232, 
+        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1235, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34469,9 +34543,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2055 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
+    // Pos:2059 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1233, 
+        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34487,9 +34561,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2056 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
+    // Pos:2060 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1234, 
+        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34505,9 +34579,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2057 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
+    // Pos:2061 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1235, 
+        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34523,9 +34597,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2058 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
+    // Pos:2062 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1236, 
+        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -34540,9 +34614,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2059 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
+    // Pos:2063 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1237, 
+        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1240, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34557,9 +34631,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2060 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
+    // Pos:2064 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1238, 
+        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1241, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34574,9 +34648,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2061 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
+    // Pos:2065 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1239, 
+        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1242, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -34591,9 +34665,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2062 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2066 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1240, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34608,9 +34682,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2063 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2067 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1240, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34625,9 +34699,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2064 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2068 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1240, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34642,9 +34716,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2065 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2069 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1240, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34659,9 +34733,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2066 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2070 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1241, 
+        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1244, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34676,9 +34750,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2067 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2071 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1241, 
+        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1244, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34693,9 +34767,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2068 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2072 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1242, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1245, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34710,9 +34784,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2069 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2073 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1242, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1245, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34727,9 +34801,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2070 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2074 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34744,9 +34818,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2071 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2075 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34761,9 +34835,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2072 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2076 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34778,9 +34852,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2073 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2077 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34795,9 +34869,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2074 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2078 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34812,9 +34886,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2075 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2079 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1243, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34829,9 +34903,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2076 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
+    // Pos:2080 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1244, 
+        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34846,9 +34920,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2077 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
+    // Pos:2081 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1244, 
+        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34863,9 +34937,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2078 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
+    // Pos:2082 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1245, 
+        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1248, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34880,9 +34954,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2079 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
+    // Pos:2083 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1245, 
+        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1248, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34897,9 +34971,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2080 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
+    // Pos:2084 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1246, 
+        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1249, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34914,9 +34988,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2081 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
+    // Pos:2085 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1246, 
+        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1249, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34931,9 +35005,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2082 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
+    // Pos:2086 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1247, 
+        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1250, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34948,9 +35022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2083 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
+    // Pos:2087 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1247, 
+        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1250, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34965,9 +35039,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2084 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
+    // Pos:2088 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
     {
-        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1248, 
+        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1251, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34981,9 +35055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2085 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
+    // Pos:2089 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
     {
-        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1249, 
+        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1252, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34997,9 +35071,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2086 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
+    // Pos:2090 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
     {
-        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1250, 
+        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1253, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35013,9 +35087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2087 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
+    // Pos:2091 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
     {
-        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1251, 
+        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1254, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35030,9 +35104,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2088 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
+    // Pos:2092 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
     {
-        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1252, 
+        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1255, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35046,9 +35120,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2089 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
+    // Pos:2093 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
     {
-        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1253, 
+        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1256, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35063,9 +35137,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2090 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
+    // Pos:2094 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
     {
-        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1254, 
+        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1257, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35079,9 +35153,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2091 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
+    // Pos:2095 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
     {
-        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1255, 
+        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1258, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35095,9 +35169,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2092 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
+    // Pos:2096 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
     {
-        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1256, 
+        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1259, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35111,9 +35185,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2093 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
+    // Pos:2097 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
     {
-        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1257, 
+        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1260, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35127,9 +35201,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2094 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
+    // Pos:2098 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
     {
-        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1258, 
+        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1261, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35143,9 +35217,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2095 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
+    // Pos:2099 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
     {
-        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1259, 
+        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1262, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35159,9 +35233,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2096 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
+    // Pos:2100 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
     {
-        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1260, 
+        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1263, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35176,9 +35250,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2097 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
+    // Pos:2101 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
     {
-        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1261, 
+        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1264, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35192,9 +35266,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2098 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
+    // Pos:2102 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
     {
-        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1262, 
+        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1265, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35208,9 +35282,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2099 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
+    // Pos:2103 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
     {
-        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1263, 
+        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35224,9 +35298,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2100 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
+    // Pos:2104 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
     {
-        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1264, 
+        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1267, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35240,9 +35314,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2101 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
+    // Pos:2105 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
     {
-        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1265, 
+        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1268, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35257,9 +35331,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2102 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
+    // Pos:2106 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
     {
-        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1266, 
+        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35273,9 +35347,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2103 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
+    // Pos:2107 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
     {
-        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1267, 
+        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1270, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35290,9 +35364,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2104 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
+    // Pos:2108 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
     {
-        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1268, 
+        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1271, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35307,9 +35381,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2105 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
+    // Pos:2109 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
     {
-        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1269, 
+        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1272, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35323,9 +35397,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2106 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2110 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35341,9 +35415,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2107 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2111 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35359,9 +35433,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2108 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2112 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1270, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35377,9 +35451,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2109 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2113 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1270, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35395,9 +35469,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2110 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2114 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1271, 
+        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1274, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -35413,9 +35487,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2111 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2115 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1271, 
+        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1274, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35431,9 +35505,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2112 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2116 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1272, 
+        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1275, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -35449,9 +35523,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2113 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2117 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1272, 
+        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1275, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35467,9 +35541,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2114 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2118 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35485,9 +35559,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2115 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2119 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35503,9 +35577,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2116 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2120 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1273, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35521,9 +35595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2117 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2121 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1273, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35539,9 +35613,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2118 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
+    // Pos:2122 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1274, 
+        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1277, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35556,9 +35630,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2119 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
+    // Pos:2123 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1275, 
+        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1278, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35573,9 +35647,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2120 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
+    // Pos:2124 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
     {
-        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1276, 
+        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35591,9 +35665,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2121 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
+    // Pos:2125 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1277, 
+        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35609,9 +35683,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2122 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
+    // Pos:2126 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1278, 
+        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1281, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35627,9 +35701,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2123 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
+    // Pos:2127 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1279, 
+        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35645,9 +35719,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2124 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
+    // Pos:2128 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1280, 
+        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35663,9 +35737,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2125 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
+    // Pos:2129 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1281, 
+        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1284, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35681,9 +35755,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2126 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
+    // Pos:2130 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1282, 
+        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1285, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35699,9 +35773,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2127 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
+    // Pos:2131 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1283, 
+        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1286, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35717,9 +35791,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2128 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
+    // Pos:2132 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1284, 
+        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1287, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35735,9 +35809,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2129 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
+    // Pos:2133 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1285, 
+        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1288, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35753,9 +35827,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2130 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
+    // Pos:2134 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1286, 
+        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1289, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35771,9 +35845,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2131 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
+    // Pos:2135 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1287, 
+        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1290, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35789,9 +35863,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2132 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
+    // Pos:2136 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
     {
-        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1288, 
+        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -35807,9 +35881,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2133 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
+    // Pos:2137 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
     {
-        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1289, 
+        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1292, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -35825,9 +35899,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2134 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
+    // Pos:2138 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1290, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35843,9 +35917,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2135 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
+    // Pos:2139 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1290, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35860,9 +35934,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2136 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
+    // Pos:2140 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1291, 
+        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35878,9 +35952,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2137 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
+    // Pos:2141 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1291, 
+        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35895,9 +35969,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2138 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
+    // Pos:2142 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1292, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35912,9 +35986,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2139 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
+    // Pos:2143 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1292, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35929,9 +36003,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2140 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
+    // Pos:2144 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1293, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1296, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35946,9 +36020,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2141 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
+    // Pos:2145 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1293, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1296, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35963,9 +36037,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2142 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
+    // Pos:2146 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1294, 
+        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1297, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35981,9 +36055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2143 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
+    // Pos:2147 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1294, 
+        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1297, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35998,9 +36072,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2144 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
+    // Pos:2148 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1295, 
+        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36016,9 +36090,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2145 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
+    // Pos:2149 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1295, 
+        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36033,9 +36107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2146 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
+    // Pos:2150 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1296, 
+        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36051,9 +36125,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2147 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
+    // Pos:2151 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1297, 
+        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1300, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36069,9 +36143,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2148 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
+    // Pos:2152 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1297, 
+        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1300, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36086,9 +36160,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2149 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
+    // Pos:2153 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1298, 
+        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36104,9 +36178,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2150 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:2154 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1298, 
+        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36121,9 +36195,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2151 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
+    // Pos:2155 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1299, 
+        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1302, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36139,9 +36213,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2152 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
+    // Pos:2156 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1299, 
+        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1302, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36156,9 +36230,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2153 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
+    // Pos:2157 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1300, 
+        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36174,9 +36248,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2154 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
+    // Pos:2158 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, 
+        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36192,9 +36266,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2155 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
+    // Pos:2159 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1301, 
+        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1304, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36209,9 +36283,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2156 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
+    // Pos:2160 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, 
+        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36227,9 +36301,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2157 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
+    // Pos:2161 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1302, 
+        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36244,9 +36318,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2158 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
+    // Pos:2162 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 
+        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1306, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36262,9 +36336,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2159 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
+    // Pos:2163 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1303, 
+        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1306, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36279,9 +36353,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2160 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
+    // Pos:2164 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1304, 
+        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1307, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36297,9 +36371,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2161 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
+    // Pos:2165 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1305, 
+        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1308, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36315,9 +36389,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2162 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
+    // Pos:2166 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1305, 
+        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1308, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36332,9 +36406,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2163 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
+    // Pos:2167 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1306, 
+        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36350,9 +36424,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2164 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
+    // Pos:2168 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1306, 
+        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36367,9 +36441,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2165 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
+    // Pos:2169 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1307, 
+        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36385,9 +36459,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2166 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
+    // Pos:2170 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1307, 
+        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36402,9 +36476,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2167 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
+    // Pos:2171 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1308, 
+        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1311, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36420,9 +36494,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2168 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
+    // Pos:2172 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1309, 
+        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36438,9 +36512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2169 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
+    // Pos:2173 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1309, 
+        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36455,9 +36529,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2170 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
+    // Pos:2174 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1310, 
+        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36471,9 +36545,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2171 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
+    // Pos:2175 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1311, 
+        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1314, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36487,9 +36561,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2172 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
+    // Pos:2176 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
     {
-        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1312, 
+        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36504,9 +36578,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2173 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
+    // Pos:2177 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
     {
-        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1313, 
+        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36521,9 +36595,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2174 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
+    // Pos:2178 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1314, 
+        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1317, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36537,9 +36611,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2175 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
+    // Pos:2179 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1315, 
+        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1318, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36553,9 +36627,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2176 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
+    // Pos:2180 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1316, 
+        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1319, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36569,9 +36643,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2177 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
+    // Pos:2181 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1317, 
+        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1320, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36585,9 +36659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2178 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
+    // Pos:2182 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
     {
-        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1318, 
+        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1321, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36601,9 +36675,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2179 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
+    // Pos:2183 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1319, 
+        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1322, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36617,9 +36691,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2180 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
+    // Pos:2184 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
     {
-        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, 
+        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36634,9 +36708,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2181 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
+    // Pos:2185 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
     {
-        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, 
+        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36651,9 +36725,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2182 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
+    // Pos:2186 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
     {
-        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1322, 
+        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36668,9 +36742,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2183 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
+    // Pos:2187 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
     {
-        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 
+        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36685,9 +36759,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2184 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
+    // Pos:2188 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
     {
-        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 
+        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36702,9 +36776,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2185 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
+    // Pos:2189 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
     {
-        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 
+        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36719,9 +36793,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2186 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
+    // Pos:2190 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
     {
-        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1326, 
+        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36736,9 +36810,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2187 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
+    // Pos:2191 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
     {
-        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1327, 
+        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36753,9 +36827,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2188 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
+    // Pos:2192 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
     {
-        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1328, 
+        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1331, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36770,9 +36844,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2189 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
+    // Pos:2193 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 
+        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36787,9 +36861,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2190 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
+    // Pos:2194 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1329, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36803,9 +36877,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2191 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
+    // Pos:2195 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1329, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36819,9 +36893,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2192 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
+    // Pos:2196 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1330, 
+        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36836,9 +36910,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2193 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
+    // Pos:2197 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1330, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36852,9 +36926,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2194 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
+    // Pos:2198 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1330, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36868,9 +36942,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2195 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
+    // Pos:2199 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1331, 
+        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36885,9 +36959,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2196 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
+    // Pos:2200 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1331, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36901,9 +36975,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2197 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
+    // Pos:2201 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1331, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36917,9 +36991,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2198 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
+    // Pos:2202 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, 
+        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36934,9 +37008,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2199 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
+    // Pos:2203 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1332, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36950,9 +37024,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2200 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
+    // Pos:2204 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1332, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36966,9 +37040,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2201 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
+    // Pos:2205 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1333, 
+        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36983,9 +37057,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2202 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
+    // Pos:2206 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1333, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36999,9 +37073,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2203 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
+    // Pos:2207 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1333, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37015,9 +37089,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2204 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
+    // Pos:2208 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1334, 
+        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37032,9 +37106,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2205 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
+    // Pos:2209 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1334, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37048,9 +37122,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2206 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
+    // Pos:2210 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1334, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37064,9 +37138,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2207 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
+    // Pos:2211 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1335, 
+        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37081,9 +37155,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2208 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
+    // Pos:2212 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1336, 
+        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37098,9 +37172,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2209 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
+    // Pos:2213 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1337, 
+        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37115,9 +37189,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2210 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
+    // Pos:2214 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1338, 
+        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37132,9 +37206,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2211 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
+    // Pos:2215 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1339, 
+        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37149,9 +37223,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2212 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
+    // Pos:2216 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
     {
-        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1340, 
+        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37166,9 +37240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2213 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
+    // Pos:2217 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1341, 
+        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37182,9 +37256,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2214 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
+    // Pos:2218 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
     {
-        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1342, 
+        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37199,9 +37273,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2215 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
+    // Pos:2219 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1343, 
+        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37216,9 +37290,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2216 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
+    // Pos:2220 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1343, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37232,9 +37306,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2217 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
+    // Pos:2221 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1343, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37248,9 +37322,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2218 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
+    // Pos:2222 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1344, 
+        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37265,9 +37339,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2219 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
+    // Pos:2223 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1344, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37281,9 +37355,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2220 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
+    // Pos:2224 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1344, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37297,9 +37371,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2221 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
+    // Pos:2225 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1345, 
+        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37314,9 +37388,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2222 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
+    // Pos:2226 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1345, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37330,9 +37404,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2223 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
+    // Pos:2227 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1345, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37346,9 +37420,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2224 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
+    // Pos:2228 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1346, 
+        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37363,9 +37437,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2225 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
+    // Pos:2229 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1346, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37379,9 +37453,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2226 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
+    // Pos:2230 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1346, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37395,9 +37469,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2227 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
+    // Pos:2231 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1347, 
+        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37412,9 +37486,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2228 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
+    // Pos:2232 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1347, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37428,9 +37502,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2229 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
+    // Pos:2233 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1347, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37444,9 +37518,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2230 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
+    // Pos:2234 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1348, 
+        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37461,9 +37535,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2231 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
+    // Pos:2235 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1348, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37477,9 +37551,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2232 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
+    // Pos:2236 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1348, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37493,9 +37567,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2233 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
+    // Pos:2237 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 
+        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37511,9 +37585,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2234 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
+    // Pos:2238 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1349, 
+        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37528,9 +37602,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2235 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
+    // Pos:2239 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1350, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37546,9 +37620,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2236 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
+    // Pos:2240 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1350, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37563,9 +37637,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2237 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
+    // Pos:2241 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1351, 
+        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37581,9 +37655,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2238 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
+    // Pos:2242 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1351, 
+        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37598,9 +37672,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2239 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
+    // Pos:2243 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1352, 
+        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37616,9 +37690,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2240 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
+    // Pos:2244 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1352, 
+        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37633,9 +37707,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2241 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
+    // Pos:2245 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1353, 
+        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37651,9 +37725,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2242 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
+    // Pos:2246 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1353, 
+        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37668,9 +37742,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2243 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
+    // Pos:2247 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1354, 
+        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1357, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37686,9 +37760,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2244 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
+    // Pos:2248 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1355, 
+        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37704,9 +37778,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2245 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
+    // Pos:2249 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1355, 
+        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37721,9 +37795,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2246 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
+    // Pos:2250 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
     {
-        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1356, 
+        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1359, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -37739,9 +37813,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2247 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
+    // Pos:2251 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37757,9 +37831,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2248 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
+    // Pos:2252 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1357, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37774,9 +37848,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2249 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
+    // Pos:2253 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1358, 
+        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -37791,9 +37865,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2250 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
+    // Pos:2254 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1359, 
+        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -37808,9 +37882,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2251 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
+    // Pos:2255 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1360, 
+        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -37825,9 +37899,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2252 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
+    // Pos:2256 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1361, 
+        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -37842,9 +37916,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2253 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
+    // Pos:2257 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
     {
-        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1362, 
+        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37859,9 +37933,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2254 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
+    // Pos:2258 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1363, 
+        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37877,9 +37951,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2255 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
+    // Pos:2259 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1364, 
+        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37895,9 +37969,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2256 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
+    // Pos:2260 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1365, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37913,9 +37987,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2257 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
+    // Pos:2261 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1365, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37931,9 +38005,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2258 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
+    // Pos:2262 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
+        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1369, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37949,9 +38023,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2259 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
+    // Pos:2263 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 
+        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37967,9 +38041,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2260 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2264 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 
+        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37985,9 +38059,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2261 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2265 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1369, 
+        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38003,9 +38077,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2262 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
+    // Pos:2266 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1370, 
+        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38021,9 +38095,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2263 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
+    // Pos:2267 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1371, 
+        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38039,9 +38113,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2264 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2268 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1372, 
+        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1375, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38057,9 +38131,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2265 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2269 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1373, 
+        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1376, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38075,9 +38149,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2266 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
+    // Pos:2270 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1374, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38092,9 +38166,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2267 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
+    // Pos:2271 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1374, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38109,9 +38183,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2268 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
+    // Pos:2272 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1374, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38126,9 +38200,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2269 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
+    // Pos:2273 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1375, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38143,9 +38217,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2270 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
+    // Pos:2274 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1375, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38160,9 +38234,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2271 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
+    // Pos:2275 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1375, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38177,9 +38251,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2272 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
+    // Pos:2276 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1376, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38194,9 +38268,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2273 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
+    // Pos:2277 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1376, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38211,9 +38285,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2274 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
+    // Pos:2278 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1376, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38228,9 +38302,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2275 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
+    // Pos:2279 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1377, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38245,9 +38319,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2276 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
+    // Pos:2280 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1377, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38262,9 +38336,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2277 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
+    // Pos:2281 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1377, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38279,9 +38353,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2278 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2282 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1378, 
+        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38296,9 +38370,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2279 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2283 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1378, 
+        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38313,9 +38387,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2280 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2284 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1379, 
+        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38330,9 +38404,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2281 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2285 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1380, 
+        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38347,9 +38421,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2282 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2286 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1381, 
+        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1384, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38364,9 +38438,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2283 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2287 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1382, 
+        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38381,9 +38455,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2284 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
+    // Pos:2288 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1383, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1386, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38398,9 +38472,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2285 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
+    // Pos:2289 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1383, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1386, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38415,9 +38489,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2286 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
+    // Pos:2290 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1384, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38432,9 +38506,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2287 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
+    // Pos:2291 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1384, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38449,9 +38523,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2288 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
+    // Pos:2292 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1385, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1388, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38466,9 +38540,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2289 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
+    // Pos:2293 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1385, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1388, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38483,9 +38557,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2290 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
+    // Pos:2294 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1386, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1389, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38500,9 +38574,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2291 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
+    // Pos:2295 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1386, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1389, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38517,9 +38591,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2292 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
+    // Pos:2296 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1387, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38534,9 +38608,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2293 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
+    // Pos:2297 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1387, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38551,9 +38625,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2294 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
+    // Pos:2298 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1387, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38568,9 +38642,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2295 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
+    // Pos:2299 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1387, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38585,9 +38659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2296 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
+    // Pos:2300 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
     {
-        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1388, 
+        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1391, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38602,9 +38676,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2297 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
+    // Pos:2301 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1389, 
+        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1392, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38621,9 +38695,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2298 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
+    // Pos:2302 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1390, 
+        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1393, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38640,9 +38714,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2299 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
+    // Pos:2303 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1391, 
+        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1394, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38658,9 +38732,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2300 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
+    // Pos:2304 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1392, 
+        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1395, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38676,9 +38750,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2301 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
+    // Pos:2305 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1393, 
+        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1396, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38694,9 +38768,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2302 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
+    // Pos:2306 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1394, 
+        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1397, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38713,9 +38787,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2303 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
+    // Pos:2307 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1395, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1398, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38730,9 +38804,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2304 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
+    // Pos:2308 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1395, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1398, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38747,9 +38821,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2305 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+    // Pos:2309 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
     {
-        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1396, 
+        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1399, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38764,9 +38838,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2306 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
+    // Pos:2310 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1397, 
+        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1400, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38783,9 +38857,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2307 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
+    // Pos:2311 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1398, 
+        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1401, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38802,9 +38876,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2308 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
+    // Pos:2312 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1399, 
+        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38820,9 +38894,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2309 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
+    // Pos:2313 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1400, 
+        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1403, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38838,9 +38912,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2310 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
+    // Pos:2314 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1401, 
+        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1404, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38856,9 +38930,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2311 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
+    // Pos:2315 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1402, 
+        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1405, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38875,9 +38949,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2312 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
+    // Pos:2316 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 
+        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38893,9 +38967,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2313 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
+    // Pos:2317 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1403, 
+        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38910,9 +38984,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2314 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
+    // Pos:2318 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
     {
-        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1404, 
+        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -38928,9 +39002,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2315 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
+    // Pos:2319 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1405, 
+        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1408, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38946,9 +39020,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2316 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2320 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1405, 
+        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1408, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38963,9 +39037,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2317 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2321 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38981,9 +39055,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2318 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2322 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1406, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38998,9 +39072,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2319 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2323 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1407, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39016,9 +39090,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2320 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2324 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1407, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39033,9 +39107,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2321 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
+    // Pos:2325 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
     {
-        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1408, 
+        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1411, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39050,9 +39124,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2322 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
+    // Pos:2326 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
     {
-        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1409, 
+        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1412, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39067,9 +39141,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2323 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
+    // Pos:2327 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
     {
-        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1410, 
+        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39084,9 +39158,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2324 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
+    // Pos:2328 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1411, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39102,9 +39176,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2325 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
+    // Pos:2329 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1411, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39120,9 +39194,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2326 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
+    // Pos:2330 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1411, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39137,9 +39211,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2327 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
+    // Pos:2331 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1411, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39154,9 +39228,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2328 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
+    // Pos:2332 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1415, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39171,9 +39245,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2329 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
+    // Pos:2333 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1412, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1415, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39188,9 +39262,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2330 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
+    // Pos:2334 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39206,9 +39280,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2331 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
+    // Pos:2335 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39224,9 +39298,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2332 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
+    // Pos:2336 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1413, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39241,9 +39315,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2333 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
+    // Pos:2337 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1413, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39258,9 +39332,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2334 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
+    // Pos:2338 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
+        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1417, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39276,9 +39350,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2335 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
+    // Pos:2339 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1414, 
+        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1417, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39293,9 +39367,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2336 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
+    // Pos:2340 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1418, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39311,9 +39385,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2337 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
+    // Pos:2341 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1415, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1418, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39328,9 +39402,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2338 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
+    // Pos:2342 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
     {
-        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1416, 
+        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39346,9 +39420,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2339 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
+    // Pos:2343 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1417, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39364,9 +39438,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2340 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
+    // Pos:2344 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1417, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39382,9 +39456,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2341 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
+    // Pos:2345 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1417, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39399,9 +39473,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2342 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
+    // Pos:2346 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1417, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39416,9 +39490,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2343 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
+    // Pos:2347 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1418, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39434,9 +39508,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2344 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
+    // Pos:2348 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1418, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39452,9 +39526,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2345 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
+    // Pos:2349 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1418, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39469,9 +39543,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2346 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
+    // Pos:2350 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1418, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39486,9 +39560,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2347 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
+    // Pos:2351 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1419, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39504,9 +39578,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2348 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
+    // Pos:2352 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1419, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39522,9 +39596,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2349 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
+    // Pos:2353 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, 
+        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1423, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39540,9 +39614,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2350 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
+    // Pos:2354 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1420, 
+        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1423, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39557,9 +39631,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2351 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
+    // Pos:2355 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1421, 
+        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1424, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39575,9 +39649,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2352 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
+    // Pos:2356 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
     {
-        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1422, 
+        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39593,9 +39667,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2353 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
+    // Pos:2357 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1423, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39611,9 +39685,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2354 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
+    // Pos:2358 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1423, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39629,9 +39703,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2355 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
+    // Pos:2359 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1423, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39646,9 +39720,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2356 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
+    // Pos:2360 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1423, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39663,9 +39737,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2357 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
+    // Pos:2361 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1424, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39681,9 +39755,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2358 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
+    // Pos:2362 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1424, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39699,9 +39773,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2359 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
+    // Pos:2363 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1424, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39716,9 +39790,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2360 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
+    // Pos:2364 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1424, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39733,9 +39807,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2361 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
+    // Pos:2365 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39750,9 +39824,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2362 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
+    // Pos:2366 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1425, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39767,9 +39841,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2363 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
+    // Pos:2367 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39785,9 +39859,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2364 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
+    // Pos:2368 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39803,9 +39877,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2365 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
+    // Pos:2369 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1426, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39820,9 +39894,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2366 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
+    // Pos:2370 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1426, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39837,9 +39911,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2367 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
+    // Pos:2371 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1427, 
+        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39855,9 +39929,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2368 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
+    // Pos:2372 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1427, 
+        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39872,9 +39946,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2369 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
+    // Pos:2373 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1428, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39890,9 +39964,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2370 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
+    // Pos:2374 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1428, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39907,9 +39981,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2371 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
+    // Pos:2375 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
     {
-        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1429, 
+        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39925,9 +39999,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2372 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
+    // Pos:2376 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39943,9 +40017,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2373 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
+    // Pos:2377 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39961,9 +40035,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2374 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
+    // Pos:2378 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1430, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39978,9 +40052,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2375 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
+    // Pos:2379 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1430, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39995,9 +40069,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2376 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
+    // Pos:2380 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 
+        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40013,9 +40087,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2377 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
+    // Pos:2381 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1431, 
+        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40030,9 +40104,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2378 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
+    // Pos:2382 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1432, 
+        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1435, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40048,9 +40122,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2379 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
+    // Pos:2383 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1432, 
+        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1435, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40065,9 +40139,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2380 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
+    // Pos:2384 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1433, 
+        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40083,9 +40157,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2381 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
+    // Pos:2385 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1433, 
+        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1436, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40100,9 +40174,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2382 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
+    // Pos:2386 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
+        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40118,9 +40192,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2383 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
+    // Pos:2387 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1434, 
+        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1437, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40135,9 +40209,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2384 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
+    // Pos:2388 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, 
+        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40153,9 +40227,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2385 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
+    // Pos:2389 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1435, 
+        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1438, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40170,9 +40244,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2386 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
+    // Pos:2390 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1436, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40188,9 +40262,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2387 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
+    // Pos:2391 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1436, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1439, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40205,9 +40279,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2388 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
+    // Pos:2392 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1440, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40223,9 +40297,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2389 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
+    // Pos:2393 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1437, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1440, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40240,9 +40314,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2390 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
+    // Pos:2394 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
+        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1441, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40258,9 +40332,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2391 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
+    // Pos:2395 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1438, 
+        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1441, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40275,9 +40349,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2392 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
+    // Pos:2396 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1439, 
+        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1442, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40294,9 +40368,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2393 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
+    // Pos:2397 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1440, 
+        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1443, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40313,9 +40387,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2394 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
+    // Pos:2398 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
     {
-        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1441, 
+        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1444, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40330,9 +40404,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2395 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2399 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1442, 
+        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1445, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40348,9 +40422,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2396 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2400 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1443, 
+        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1446, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40366,9 +40440,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2397 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2401 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1444, 
+        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1447, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40384,9 +40458,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2398 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2402 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1445, 
+        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1448, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40402,9 +40476,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2399 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2403 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1446, 
+        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1449, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40420,9 +40494,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2400 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2404 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1447, 
+        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1450, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40438,9 +40512,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2401 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2405 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1448, 
+        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1451, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40456,9 +40530,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2402 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2406 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1449, 
+        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1452, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40474,9 +40548,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2403 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
+    // Pos:2407 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1450, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1453, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40492,9 +40566,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2404 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
+    // Pos:2408 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1450, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1453, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40509,9 +40583,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2405 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
+    // Pos:2409 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1451, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1454, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40527,9 +40601,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2406 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
+    // Pos:2410 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1451, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1454, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40544,9 +40618,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2407 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
+    // Pos:2411 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1452, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1455, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40562,9 +40636,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2408 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
+    // Pos:2412 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1452, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1455, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40579,9 +40653,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2409 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
+    // Pos:2413 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1453, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1456, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40597,9 +40671,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2410 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
+    // Pos:2414 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1453, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1456, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40614,9 +40688,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2411 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
+    // Pos:2415 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1454, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1457, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40632,9 +40706,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2412 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
+    // Pos:2416 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1454, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1457, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40649,9 +40723,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2413 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
+    // Pos:2417 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1455, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1458, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40667,9 +40741,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2414 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
+    // Pos:2418 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1455, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1458, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40684,9 +40758,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2415 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
+    // Pos:2419 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1456, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1459, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40702,9 +40776,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2416 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
+    // Pos:2420 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1456, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1459, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40719,9 +40793,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2417 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
+    // Pos:2421 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1457, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1460, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40737,9 +40811,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2418 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
+    // Pos:2422 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1457, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1460, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40754,9 +40828,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2419 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
+    // Pos:2423 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
     {
-        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1458, 
+        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1461, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40771,9 +40845,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2420 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
+    // Pos:2424 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1459, 
+        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1462, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40789,9 +40863,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2421 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
+    // Pos:2425 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1460, 
+        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1463, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40807,9 +40881,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2422 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
+    // Pos:2426 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1461, 
+        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1464, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40826,9 +40900,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2423 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
+    // Pos:2427 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1462, 
+        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1465, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40845,9 +40919,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2424 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
+    // Pos:2428 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1463, 
+        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1466, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40864,9 +40938,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2425 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
+    // Pos:2429 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1464, 
+        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1467, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40883,9 +40957,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2426 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
+    // Pos:2430 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1465, 
+        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1468, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40900,9 +40974,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2427 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
+    // Pos:2431 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1466, 
+        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1469, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40917,9 +40991,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2428 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
+    // Pos:2432 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1467, 
+        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40935,9 +41009,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2429 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
+    // Pos:2433 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1468, 
+        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1471, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40953,9 +41027,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2430 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
+    // Pos:2434 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1469, 
+        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1472, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40970,9 +41044,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2431 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
+    // Pos:2435 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1470, 
+        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1473, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40987,9 +41061,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2432 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
+    // Pos:2436 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1471, 
+        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41005,9 +41079,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2433 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
+    // Pos:2437 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1472, 
+        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1475, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41023,9 +41097,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2434 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
+    // Pos:2438 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
     {
-        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1473, 
+        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1476, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41039,9 +41113,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2435 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
+    // Pos:2439 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
     {
-        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1474, 
+        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1477, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41056,9 +41130,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2436 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
+    // Pos:2440 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1475, 
+        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1478, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -41074,9 +41148,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2437 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
+    // Pos:2441 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1476, 
+        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -41092,9 +41166,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2438 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
+    // Pos:2442 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1477, 
+        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1480, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -41111,9 +41185,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2439 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
+    // Pos:2443 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1478, 
+        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1481, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -41130,9 +41204,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2440 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
+    // Pos:2444 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1479, 
+        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1482, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41148,9 +41222,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2441 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
+    // Pos:2445 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1480, 
+        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41166,9 +41240,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2442 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
+    // Pos:2446 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1481, 
+        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1484, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41185,9 +41259,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2443 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
+    // Pos:2447 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1482, 
+        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1485, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41204,9 +41278,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2444 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
+    // Pos:2448 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1483, 
+        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1486, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41221,9 +41295,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2445 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
+    // Pos:2449 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1484, 
+        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1487, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41238,9 +41312,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2446 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
+    // Pos:2450 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1485, 
+        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1488, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41256,9 +41330,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2447 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
+    // Pos:2451 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1486, 
+        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1489, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41274,9 +41348,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2448 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
+    // Pos:2452 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1487, 
+        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1490, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41291,9 +41365,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2449 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
+    // Pos:2453 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1488, 
+        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1491, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41308,9 +41382,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2450 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
+    // Pos:2454 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1489, 
+        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1492, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41326,9 +41400,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2451 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
+    // Pos:2455 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1490, 
+        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1493, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41344,9 +41418,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2452 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
+    // Pos:2456 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1491, 
+        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1494, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41361,9 +41435,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2453 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
+    // Pos:2457 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1492, 
+        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1495, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41378,9 +41452,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2454 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
+    // Pos:2458 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1493, 
+        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1496, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41396,9 +41470,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2455 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
+    // Pos:2459 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1494, 
+        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1497, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41414,9 +41488,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2456 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
+    // Pos:2460 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
     {
-        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1495, 
+        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1498, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41430,9 +41504,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2457 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
+    // Pos:2461 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
     {
-        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1496, 
+        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1499, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41447,9 +41521,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2458 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
+    // Pos:2462 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 
+        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41465,9 +41539,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2459 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
+    // Pos:2463 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1498, 
+        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41483,9 +41557,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2460 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
+    // Pos:2464 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 
+        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41501,9 +41575,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2461 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
+    // Pos:2465 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
+        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41519,9 +41593,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2462 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2466 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1501, 
+        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1504, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41536,9 +41610,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2463 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2467 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1502, 
+        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1505, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41553,9 +41627,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2464 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
+    // Pos:2468 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1503, 
+        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1506, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41569,9 +41643,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2465 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
+    // Pos:2469 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1504, 
+        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1507, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41585,9 +41659,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2466 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
+    // Pos:2470 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1505, 
+        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1508, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41601,9 +41675,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2467 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
+    // Pos:2471 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1506, 
+        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1509, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41617,9 +41691,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2468 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
+    // Pos:2472 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1507, 
+        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1510, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41633,9 +41707,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2469 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
+    // Pos:2473 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1508, 
+        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1511, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41649,9 +41723,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2470 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
+    // Pos:2474 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1509, 
+        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1512, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41665,9 +41739,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2471 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
+    // Pos:2475 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1510, 
+        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1513, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41681,9 +41755,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2472 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2476 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1511, 
+        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41698,9 +41772,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2473 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2477 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1512, 
+        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41715,9 +41789,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2474 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+    // Pos:2478 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1513, 
+        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41734,9 +41808,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2475 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
+    // Pos:2479 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1514, 
+        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41753,9 +41827,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2476 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
+    // Pos:2480 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1515, 
+        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1518, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41772,9 +41846,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2477 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
+    // Pos:2481 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 
+        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1519, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41791,9 +41865,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2478 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
+    // Pos:2482 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1517, 
+        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1520, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41810,9 +41884,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2479 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2483 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1517, 
+        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1520, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41828,9 +41902,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2480 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
+    // Pos:2484 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1518, 
+        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41847,9 +41921,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2481 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2485 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1518, 
+        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41865,9 +41939,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2482 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+    // Pos:2486 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1519, 
+        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41882,9 +41956,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2483 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
+    // Pos:2487 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1519, 
+        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41898,9 +41972,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2484 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
+    // Pos:2488 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1520, 
+        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41915,9 +41989,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2485 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
+    // Pos:2489 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1520, 
+        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41931,9 +42005,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2486 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
+    // Pos:2490 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1521, 
+        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41949,9 +42023,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2487 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2491 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1521, 
+        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41966,9 +42040,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2488 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
+    // Pos:2492 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1522, 
+        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41984,9 +42058,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2489 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2493 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1522, 
+        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42001,9 +42075,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2490 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
+    // Pos:2494 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
     {
-        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1523, 
+        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -42017,9 +42091,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2491 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
+    // Pos:2495 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1524, 
+        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42035,9 +42109,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2492 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2496 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1524, 
+        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42052,9 +42126,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2493 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
+    // Pos:2497 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1525, 
+        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1528, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42070,9 +42144,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2494 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2498 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1525, 
+        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1528, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42087,9 +42161,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2495 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
+    // Pos:2499 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1526, 
+        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1529, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42105,9 +42179,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2496 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2500 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1526, 
+        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1529, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42122,9 +42196,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2497 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
+    // Pos:2501 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1527, 
+        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1530, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42140,9 +42214,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2498 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2502 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1527, 
+        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1530, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42157,9 +42231,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2499 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
+    // Pos:2503 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
     {
-        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1528, 
+        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1531, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42174,9 +42248,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2500 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
+    // Pos:2504 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
     {
-        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1529, 
+        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1532, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42191,9 +42265,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2501 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
+    // Pos:2505 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1530, 
+        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1533, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42208,9 +42282,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2502 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
+    // Pos:2506 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1530, 
+        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1533, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42225,9 +42299,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2503 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
+    // Pos:2507 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1531, 
+        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1534, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42242,9 +42316,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2504 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
+    // Pos:2508 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1531, 
+        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1534, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42259,9 +42333,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2505 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2509 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1532, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1535, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42277,9 +42351,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2506 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2510 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1532, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1535, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42294,9 +42368,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2507 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2511 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1533, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1536, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42312,9 +42386,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2508 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2512 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1533, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1536, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42329,9 +42403,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2509 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2513 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1534, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1537, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42347,9 +42421,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2510 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2514 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1534, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1537, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42364,9 +42438,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2511 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2515 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1535, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1538, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42382,9 +42456,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2512 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2516 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1535, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1538, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42399,9 +42473,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2513 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
+    // Pos:2517 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1536, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1539, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -42417,9 +42491,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2514 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2518 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1536, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1539, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42434,9 +42508,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2515 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
+    // Pos:2519 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1537, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1540, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -42452,9 +42526,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2516 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2520 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1537, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1540, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42469,9 +42543,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2517 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
+    // Pos:2521 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
     {
-        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1538, 
+        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1541, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -42484,9 +42558,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2518 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
+    // Pos:2522 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
     {
-        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1539, 
+        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1542, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -42499,9 +42573,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2519 Instruction:"WAIT" Encoding:"0x9B"/""
+    // Pos:2523 Instruction:"WAIT" Encoding:"0x9B"/""
     {
-        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1540, 
+        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1543, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, 
@@ -42514,9 +42588,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2520 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
+    // Pos:2524 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
     {
-        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1541, 
+        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1544, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -42529,9 +42603,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2521 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
+    // Pos:2525 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
     {
-        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1542, 
+        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1545, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, 
@@ -42544,9 +42618,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2522 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
+    // Pos:2526 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
     {
-        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1543, 
+        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1546, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -42560,9 +42634,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2523 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
+    // Pos:2527 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
     {
-        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1544, 
+        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1547, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -42576,9 +42650,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2524 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
+    // Pos:2528 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
     {
-        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1545, 
+        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1548, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, 
@@ -42594,9 +42668,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2525 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
+    // Pos:2529 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1546, 
+        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1549, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -42612,9 +42686,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2526 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
+    // Pos:2530 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
     {
-        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1547, 
+        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42627,9 +42701,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2527 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2531 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1548, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42643,9 +42717,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2528 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2532 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1549, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1552, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42659,9 +42733,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2529 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2533 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1550, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42675,9 +42749,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2530 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2534 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1551, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42691,9 +42765,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2531 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
+    // Pos:2535 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
     {
-        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1552, 
+        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1555, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -42707,9 +42781,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2532 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
+    // Pos:2536 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1553, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1556, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42724,9 +42798,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2533 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
+    // Pos:2537 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1553, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1556, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42741,9 +42815,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2534 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
+    // Pos:2538 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
     {
-        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1554, 
+        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -42758,9 +42832,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2535 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
+    // Pos:2539 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42774,9 +42848,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2536 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
+    // Pos:2540 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42790,9 +42864,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2537 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
+    // Pos:2541 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42806,9 +42880,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2538 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
+    // Pos:2542 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42822,9 +42896,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2539 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
+    // Pos:2543 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42838,9 +42912,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2540 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
+    // Pos:2544 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42854,9 +42928,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2541 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
+    // Pos:2545 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42870,9 +42944,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2542 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
+    // Pos:2546 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42886,9 +42960,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2543 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
+    // Pos:2547 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42902,9 +42976,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2544 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
+    // Pos:2548 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42918,9 +42992,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2545 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
+    // Pos:2549 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
     {
-        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1556, 
+        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1559, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42933,9 +43007,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2546 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
+    // Pos:2550 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
     {
-        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1557, 
+        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1560, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42948,9 +43022,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2547 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
+    // Pos:2551 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
     {
-        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1558, 
+        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1561, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42963,9 +43037,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2548 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
+    // Pos:2552 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
     {
-        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1559, 
+        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1562, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42978,9 +43052,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2549 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
+    // Pos:2553 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
     {
-        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1560, 
+        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1563, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42993,9 +43067,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2550 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
+    // Pos:2554 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
     {
-        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1561, 
+        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -43008,9 +43082,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2551 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
+    // Pos:2555 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
     {
-        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1562, 
+        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43026,9 +43100,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2552 Instruction:"XLATB" Encoding:"0xD7"/""
+    // Pos:2556 Instruction:"XLATB" Encoding:"0xD7"/""
     {
-        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1563, 
+        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -43042,9 +43116,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2553 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
+    // Pos:2557 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43059,9 +43133,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2554 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
+    // Pos:2558 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43076,9 +43150,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2555 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
+    // Pos:2559 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43093,9 +43167,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2556 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
+    // Pos:2560 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43110,9 +43184,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2557 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
+    // Pos:2561 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -43127,9 +43201,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2558 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
+    // Pos:2562 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -43144,9 +43218,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2559 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
+    // Pos:2563 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43161,9 +43235,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2560 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
+    // Pos:2564 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43178,9 +43252,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2561 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
+    // Pos:2565 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -43195,9 +43269,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2562 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
+    // Pos:2566 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1564, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1567, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43212,9 +43286,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2563 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
+    // Pos:2567 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1565, 
+        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1568, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -43228,9 +43302,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2564 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
+    // Pos:2568 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1566, 
+        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -43244,9 +43318,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2565 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
+    // Pos:2569 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
     {
-        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1567, 
+        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1570, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -43259,9 +43333,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2566 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2570 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1568, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1571, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43278,9 +43352,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2567 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2571 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1569, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43297,9 +43371,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2568 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2572 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1570, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43316,9 +43390,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2569 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2573 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1571, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43335,9 +43409,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2570 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2574 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1572, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43354,9 +43428,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2571 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2575 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1573, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43373,9 +43447,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2572 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2576 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1574, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1577, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -43392,9 +43466,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2573 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2577 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1575, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1578, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -43411,9 +43485,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2574 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2578 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1576, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43430,9 +43504,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2575 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2579 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1577, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1580, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43449,9 +43523,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2576 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2580 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1578, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1581, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43468,9 +43542,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2577 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2581 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1579, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1582, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43487,9 +43561,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2578 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
+    // Pos:2582 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
     {
-        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1580, 
+        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1583, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43505,9 +43579,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2579 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
+    // Pos:2583 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
     {
-        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1581, 
+        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1584, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43520,9 +43594,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2580 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
+    // Pos:2584 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
     {
-        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1582, 
+        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1585, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43535,9 +43609,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2581 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
+    // Pos:2585 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1583, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1586, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43550,9 +43624,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2582 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/""
+    // Pos:2586 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1583, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1586, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43565,9 +43639,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2583 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
+    // Pos:2587 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1584, 
+        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1587, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -43580,9 +43654,9 @@ const ND_INSTRUCTION gInstructions[2585] =
         },
     }, 
 
-    // Pos:2584 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
+    // Pos:2588 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
     {
-        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1585, 
+        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1588, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
index f3c8fb1..b0084fe 100644
--- a/bddisasm/include/mnemonics.h
+++ b/bddisasm/include/mnemonics.h
@@ -1,7 +1,7 @@
 #ifndef MNEMONICS_H
 #define MNEMONICS_H
 
-const char *gMnemonics[1586] = 
+const char *gMnemonics[1589] = 
 {
     "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", 
     "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL", 
@@ -29,139 +29,139 @@ const char *gMnemonics[1586] =
     "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", 
     "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", 
     "ENCODEKEY256", "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", 
-    "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", 
-    "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", 
-    "FCMOVNE", "FCMOVNU", "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", 
-    "FCOMPP", "FCOS", "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", 
-    "FEMMS", "FFREE", "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", 
-    "FIDIVR", "FILD", "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", 
-    "FISUB", "FISUBR", "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", 
-    "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", 
-    "FNCLEX", "FNDISI", "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", 
-    "FNSTSW", "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", 
-    "FRSTOR", "FSCALE", "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", 
-    "FSTP", "FSTPNCE", "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", 
-    "FTST", "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", 
-    "FXCH", "FXRSTOR", "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", 
-    "FYL2X", "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", 
-    "GF2P8MULB", "HADDPD", "HADDPS", "HLT", "HRESET", "HSUBPD", "HSUBPS", 
-    "IDIV", "IMUL", "IN", "INC", "INCSSPD", "INCSSPQ", "INSB", "INSD", 
-    "INSERTPS", "INSERTQ", "INSW", "INT", "INT1", "INT3", "INTO", 
-    "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB", "INVPCID", 
-    "INVVPID", "IRETD", "IRETQ", "IRETW", "JBE", "JC", "JCXZ", "JECXZ", 
-    "JL", "JLE", "JMP", "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", 
-    "JNO", "JNP", "JNS", "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", 
-    "KADDB", "KADDD", "KADDQ", "KADDW", "KANDB", "KANDD", "KANDNB", 
-    "KANDND", "KANDNQ", "KANDNW", "KANDQ", "KANDW", "KMERGE2L1H", 
-    "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", "KMOVW", "KNOTB", "KNOTD", 
-    "KNOTQ", "KNOTW", "KORB", "KORD", "KORQ", "KORTESTB", "KORTESTD", 
-    "KORTESTQ", "KORTESTW", "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", 
-    "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", 
-    "KTESTD", "KTESTQ", "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", 
-    "KXNORB", "KXNORD", "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", 
-    "KXORW", "LAHF", "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", 
-    "LEA", "LEAVE", "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", 
-    "LLDT", "LLWPCB", "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", 
-    "LODSW", "LOOP", "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", 
-    "LWPVAL", "LZCNT", "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", 
-    "MAXSD", "MAXSS", "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", 
-    "MINSS", "MONITOR", "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", 
-    "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", 
-    "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", 
-    "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", 
-    "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", 
-    "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", 
-    "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", 
-    "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", "MULSS", 
-    "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD", 
-    "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW", 
-    "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD", 
-    "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", "PALIGNR", 
-    "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", "PBLENDVB", 
-    "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", 
-    "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", 
-    "PCMPISTRI", "PCMPISTRM", "PCONFIG", "PDEP", "PEXT", "PEXTRB", 
-    "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", "PFACC", "PFADD", 
-    "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", "PFMUL", "PFNACC", 
-    "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", "PFRCPV", "PFRSQIT1", 
-    "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", "PHADDD", "PHADDSW", 
-    "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", "PHSUBW", "PI2FD", 
-    "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", "PMADDUBSW", 
-    "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", "PMAXUD", 
-    "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", "PMINUW", 
-    "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD", 
-    "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD", 
-    "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW", 
-    "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", "POPCNT", 
-    "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", "PREFETCHM", 
-    "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", 
-    "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", 
-    "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", 
-    "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", 
-    "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", 
-    "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", 
-    "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", 
-    "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", "PUSHFD", 
-    "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", 
-    "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", "RDPMC", 
-    "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", 
-    "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", 
-    "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", 
-    "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", 
-    "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", 
-    "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", 
-    "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", 
-    "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", 
-    "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", 
-    "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", 
-    "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", 
-    "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT", 
-    "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", 
-    "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", 
-    "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", 
-    "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", 
-    "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS", 
-    "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TESTUI", 
-    "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", 
-    "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", 
-    "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", 
-    "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", 
-    "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPS", "VADDSD", "VADDSS", 
-    "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", 
-    "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", 
-    "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", 
-    "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", 
-    "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", 
-    "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", 
-    "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", 
-    "VBROADCASTSS", "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", 
-    "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", 
-    "VCVTNE2PS2BF16", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", 
-    "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", 
-    "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", 
-    "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", 
-    "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", 
-    "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", 
-    "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", 
-    "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", 
-    "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", "VDBPSADBW", "VDIVPD", 
-    "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", 
-    "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", 
-    "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", 
-    "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", 
-    "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", "VFIXUPIMMPD", 
-    "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", "VFMADD132PS", 
-    "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS", "VFMADD213SD", 
-    "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD", "VFMADD231SS", 
-    "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", 
-    "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS", "VFMADDSUB231PD", 
-    "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", 
-    "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PS", 
-    "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS", "VFMSUB231SD", 
-    "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS", "VFMSUBADD213PD", 
-    "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS", "VFMSUBADDPD", 
-    "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", "VFMSUBSS", 
-    "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS", 
+    "ERETS", "ERETU", "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD", 
+    "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE", 
+    "FCMOVNB", "FCMOVNBE", "FCMOVNE", "FCMOVNU", "FCMOVU", "FCOM", 
+    "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", "FCOS", "FDECSTP", "FDIV", 
+    "FDIVP", "FDIVR", "FDIVRP", "FEMMS", "FFREE", "FFREEP", "FIADD", 
+    "FICOM", "FICOMP", "FIDIV", "FIDIVR", "FILD", "FIMUL", "FINCSTP", 
+    "FIST", "FISTP", "FISTTP", "FISUB", "FISUBR", "FLD", "FLD1", 
+    "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", 
+    "FLDZ", "FMUL", "FMULP", "FNCLEX", "FNDISI", "FNINIT", "FNOP", 
+    "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", "FPATAN", "FPREM", "FPREM1", 
+    "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", "FSCALE", "FSIN", "FSINCOS", 
+    "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE", "FSTSG", "FSUB", 
+    "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM", "FUCOMI", "FUCOMIP", 
+    "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR", "FXRSTOR64", 
+    "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", "FYL2XP1", "GETSEC", 
+    "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", "HADDPS", 
+    "HLT", "HRESET", "HSUBPD", "HSUBPS", "IDIV", "IMUL", "IN", "INC", 
+    "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ", 
+    "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG", 
+    "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ", 
+    "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", 
+    "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", 
+    "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", 
+    "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", 
+    "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", 
+    "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", 
+    "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", 
+    "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", 
+    "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", "KTESTW", 
+    "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", 
+    "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", 
+    "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", 
+    "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LKGS", "LLDT", "LLWPCB", 
+    "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", 
+    "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", 
+    "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", 
+    "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", 
+    "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", 
+    "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", 
+    "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", 
+    "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", 
+    "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", 
+    "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", 
+    "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", "MUL", 
+    "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX", 
+    "NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", 
+    "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", 
+    "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", 
+    "PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", 
+    "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", 
+    "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", 
+    "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCONFIG", 
+    "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", 
+    "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", 
+    "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", 
+    "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", 
+    "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", 
+    "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", 
+    "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", 
+    "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", 
+    "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", 
+    "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", 
+    "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", 
+    "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", 
+    "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", 
+    "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", 
+    "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", 
+    "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", 
+    "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", 
+    "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", 
+    "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", 
+    "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", 
+    "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", 
+    "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", 
+    "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", 
+    "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", 
+    "RDTSC", "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", 
+    "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", 
+    "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", 
+    "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", 
+    "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", 
+    "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", 
+    "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", 
+    "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", 
+    "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", 
+    "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", 
+    "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", 
+    "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", 
+    "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", 
+    "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", 
+    "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", 
+    "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", 
+    "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", 
+    "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", 
+    "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", 
+    "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", 
+    "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", 
+    "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPS", 
+    "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", 
+    "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", 
+    "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD", 
+    "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS", 
+    "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8", 
+    "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2", 
+    "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4", 
+    "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPS", "VCMPSD", 
+    "VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", 
+    "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16", 
+    "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", 
+    "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", 
+    "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", 
+    "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", 
+    "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", 
+    "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", 
+    "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", 
+    "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", 
+    "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", 
+    "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", 
+    "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
+    "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", 
+    "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", 
+    "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", 
+    "VFMADD132PS", "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS", 
+    "VFMADD213SD", "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD", 
+    "VFMADD231SS", "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", 
+    "VFMADDSUB132PD", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS", 
+    "VFMADDSUB231PD", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", 
+    "VFMSUB132PD", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD", 
+    "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS", 
+    "VFMSUB231SD", "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS", 
+    "VFMSUBADD213PD", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS", 
+    "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", 
+    "VFMSUBSS", "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS", 
     "VFNMADD213PD", "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SS", 
     "VFNMADD231PD", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SS", 
     "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD", 
diff --git a/bddisasm/include/nd_crt.h b/bddisasm/include/nd_crt.h
index 745555d..da38ef8 100644
--- a/bddisasm/include/nd_crt.h
+++ b/bddisasm/include/nd_crt.h
@@ -64,8 +64,11 @@ extern void __cdecl __va_start(__out va_list *, ...);       // is this exported
 
 #endif // _MSC_VER
 
-#ifndef KERNEL_MODE
-// Declared here only. Expecting it to be defined in the integrator.
+// By default, an integrator is expected to provide nd_vsnprintf_s and nd_strcat_s.
+// bddisasm needs both for NdToText, while bdshemu needs nd_vsnprintf_s for emulation tracing.
+// If BDDISASM_NO_FORMAT is defined at compile time these requirements are removed. Instruction formatting will no
+// longer be available in bddisasm and emulation tracing will no longer be available in bdshemu.
+#ifndef BDDISASM_NO_FORMAT
 extern int nd_vsnprintf_s(
     char *buffer,
     size_t sizeOfBuffer,
@@ -73,12 +76,6 @@ extern int nd_vsnprintf_s(
     const char *format,
     va_list argptr
     );
-#endif // KERNEL_MODE
-
-// Declared here only. Expecting it to be defined in the integrator.
-extern void *nd_memset(void *s, int c, size_t n);
-
-#define nd_memzero(Dest, Size)         nd_memset((Dest), 0, (Size))
 
 char *
 nd_strcat_s(
@@ -86,5 +83,11 @@ nd_strcat_s(
     size_t dst_size,
     const char *src
     );
+#endif // !BDDISASM_NO_FORMAT
+
+// Declared here only. Expecting it to be defined in the integrator.
+extern void *nd_memset(void *s, int c, size_t n);
+
+#define nd_memzero(Dest, Size)         nd_memset((Dest), 0, (Size))
 
 #endif // ND_CRT_H
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
index ad7a2f3..927eeb0 100644
--- a/bddisasm/include/table_evex.h
+++ b/bddisasm/include/table_evex.h
@@ -4,7 +4,7 @@
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1352]
+    (const void *)&gInstructions[1356]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = 
@@ -39,13 +39,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1575]
+    (const void *)&gInstructions[1579]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1577]
+    (const void *)&gInstructions[1581]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = 
@@ -71,7 +71,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1353]
+    (const void *)&gInstructions[1357]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = 
@@ -95,13 +95,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1579]
+    (const void *)&gInstructions[1583]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1581]
+    (const void *)&gInstructions[1585]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = 
@@ -127,7 +127,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1354]
+    (const void *)&gInstructions[1358]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = 
@@ -162,13 +162,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1583]
+    (const void *)&gInstructions[1587]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1585]
+    (const void *)&gInstructions[1589]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = 
@@ -194,7 +194,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1355]
+    (const void *)&gInstructions[1359]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = 
@@ -218,13 +218,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1587]
+    (const void *)&gInstructions[1591]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1589]
+    (const void *)&gInstructions[1593]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1366]
+    (const void *)&gInstructions[1370]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = 
@@ -267,7 +267,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1368]
+    (const void *)&gInstructions[1372]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = 
@@ -284,7 +284,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1370]
+    (const void *)&gInstructions[1374]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = 
@@ -301,7 +301,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1372]
+    (const void *)&gInstructions[1376]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = 
@@ -318,13 +318,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1386]
+    (const void *)&gInstructions[1390]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1387]
+    (const void *)&gInstructions[1391]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = 
@@ -350,13 +350,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1393]
+    (const void *)&gInstructions[1397]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1404]
+    (const void *)&gInstructions[1408]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = 
@@ -382,13 +382,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1394]
+    (const void *)&gInstructions[1398]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1396]
+    (const void *)&gInstructions[1400]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = 
@@ -423,13 +423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1395]
+    (const void *)&gInstructions[1399]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1397]
+    (const void *)&gInstructions[1401]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = 
@@ -475,13 +475,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1399]
+    (const void *)&gInstructions[1403]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1958]
+    (const void *)&gInstructions[1962]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = 
@@ -507,13 +507,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1400]
+    (const void *)&gInstructions[1404]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1402]
+    (const void *)&gInstructions[1406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = 
@@ -548,13 +548,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1401]
+    (const void *)&gInstructions[1405]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1403]
+    (const void *)&gInstructions[1407]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = 
@@ -600,7 +600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1406]
+    (const void *)&gInstructions[1410]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = 
@@ -626,13 +626,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1420]
+    (const void *)&gInstructions[1424]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1421]
+    (const void *)&gInstructions[1425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = 
@@ -658,7 +658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1427]
+    (const void *)&gInstructions[1431]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = 
@@ -673,7 +673,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1428]
+    (const void *)&gInstructions[1432]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = 
@@ -688,7 +688,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2310]
+    (const void *)&gInstructions[2314]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = 
@@ -714,7 +714,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1437]
+    (const void *)&gInstructions[1441]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = 
@@ -729,7 +729,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2208]
+    (const void *)&gInstructions[2212]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = 
@@ -755,7 +755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1500]
+    (const void *)&gInstructions[1504]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = 
@@ -770,7 +770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1898]
+    (const void *)&gInstructions[1902]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = 
@@ -805,7 +805,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2014]
+    (const void *)&gInstructions[2018]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = 
@@ -831,13 +831,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1505]
+    (const void *)&gInstructions[1509]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1506]
+    (const void *)&gInstructions[1510]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = 
@@ -874,13 +874,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1507]
+    (const void *)&gInstructions[1511]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1508]
+    (const void *)&gInstructions[1512]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = 
@@ -906,13 +906,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1527]
+    (const void *)&gInstructions[1531]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1529]
+    (const void *)&gInstructions[1533]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = 
@@ -938,13 +938,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1531]
+    (const void *)&gInstructions[1535]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1533]
+    (const void *)&gInstructions[1537]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = 
@@ -970,13 +970,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1535]
+    (const void *)&gInstructions[1539]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1537]
+    (const void *)&gInstructions[1541]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = 
@@ -1002,13 +1002,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1539]
+    (const void *)&gInstructions[1543]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1541]
+    (const void *)&gInstructions[1545]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = 
@@ -1034,13 +1034,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1543]
+    (const void *)&gInstructions[1547]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1545]
+    (const void *)&gInstructions[1549]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = 
@@ -1066,13 +1066,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1547]
+    (const void *)&gInstructions[1551]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1549]
+    (const void *)&gInstructions[1553]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = 
@@ -1098,13 +1098,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1559]
+    (const void *)&gInstructions[1563]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1561]
+    (const void *)&gInstructions[1565]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = 
@@ -1130,13 +1130,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1563]
+    (const void *)&gInstructions[1567]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1565]
+    (const void *)&gInstructions[1569]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = 
@@ -1162,13 +1162,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1567]
+    (const void *)&gInstructions[1571]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1569]
+    (const void *)&gInstructions[1573]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = 
@@ -1194,13 +1194,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1591]
+    (const void *)&gInstructions[1595]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1593]
+    (const void *)&gInstructions[1597]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = 
@@ -1226,13 +1226,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1595]
+    (const void *)&gInstructions[1599]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1597]
+    (const void *)&gInstructions[1601]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = 
@@ -1258,13 +1258,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1599]
+    (const void *)&gInstructions[1603]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1601]
+    (const void *)&gInstructions[1605]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = 
@@ -1290,13 +1290,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1603]
+    (const void *)&gInstructions[1607]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1605]
+    (const void *)&gInstructions[1609]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = 
@@ -1322,13 +1322,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1607]
+    (const void *)&gInstructions[1611]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1609]
+    (const void *)&gInstructions[1613]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = 
@@ -1354,13 +1354,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1623]
+    (const void *)&gInstructions[1627]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1625]
+    (const void *)&gInstructions[1629]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = 
@@ -1386,13 +1386,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1627]
+    (const void *)&gInstructions[1631]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1629]
+    (const void *)&gInstructions[1633]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = 
@@ -1418,13 +1418,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1631]
+    (const void *)&gInstructions[1635]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1633]
+    (const void *)&gInstructions[1637]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = 
@@ -1450,13 +1450,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1635]
+    (const void *)&gInstructions[1639]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1637]
+    (const void *)&gInstructions[1641]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = 
@@ -1482,13 +1482,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1639]
+    (const void *)&gInstructions[1643]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1641]
+    (const void *)&gInstructions[1645]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = 
@@ -1514,13 +1514,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1643]
+    (const void *)&gInstructions[1647]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1645]
+    (const void *)&gInstructions[1649]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = 
@@ -1546,13 +1546,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1655]
+    (const void *)&gInstructions[1659]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1657]
+    (const void *)&gInstructions[1661]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = 
@@ -1578,13 +1578,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1659]
+    (const void *)&gInstructions[1663]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1661]
+    (const void *)&gInstructions[1665]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = 
@@ -1610,13 +1610,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1663]
+    (const void *)&gInstructions[1667]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1665]
+    (const void *)&gInstructions[1669]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = 
@@ -1642,13 +1642,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1667]
+    (const void *)&gInstructions[1671]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1669]
+    (const void *)&gInstructions[1673]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = 
@@ -1674,13 +1674,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1671]
+    (const void *)&gInstructions[1675]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1673]
+    (const void *)&gInstructions[1677]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = 
@@ -1706,13 +1706,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1675]
+    (const void *)&gInstructions[1679]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1677]
+    (const void *)&gInstructions[1681]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = 
@@ -1738,13 +1738,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1695]
+    (const void *)&gInstructions[1699]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1697]
+    (const void *)&gInstructions[1701]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = 
@@ -1779,13 +1779,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1699]
+    (const void *)&gInstructions[1703]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1700]
+    (const void *)&gInstructions[1704]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = 
@@ -1811,13 +1811,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1703]
+    (const void *)&gInstructions[1707]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1704]
+    (const void *)&gInstructions[1708]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = 
@@ -1843,13 +1843,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2464]
+    (const void *)&gInstructions[2468]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2465]
+    (const void *)&gInstructions[2469]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = 
@@ -1875,13 +1875,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2468]
+    (const void *)&gInstructions[2472]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2469]
+    (const void *)&gInstructions[2473]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = 
@@ -1942,13 +1942,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1701]
+    (const void *)&gInstructions[1705]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1702]
+    (const void *)&gInstructions[1706]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = 
@@ -1974,13 +1974,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1705]
+    (const void *)&gInstructions[1709]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1706]
+    (const void *)&gInstructions[1710]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = 
@@ -2006,13 +2006,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2466]
+    (const void *)&gInstructions[2470]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2467]
+    (const void *)&gInstructions[2471]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = 
@@ -2038,13 +2038,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2470]
+    (const void *)&gInstructions[2474]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2471]
+    (const void *)&gInstructions[2475]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = 
@@ -2105,13 +2105,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1707]
+    (const void *)&gInstructions[1711]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1709]
+    (const void *)&gInstructions[1713]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = 
@@ -2146,13 +2146,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1711]
+    (const void *)&gInstructions[1715]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1712]
+    (const void *)&gInstructions[1716]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = 
@@ -2178,13 +2178,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1713]
+    (const void *)&gInstructions[1717]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1714]
+    (const void *)&gInstructions[1718]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = 
@@ -2210,7 +2210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1723]
+    (const void *)&gInstructions[1727]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = 
@@ -2236,7 +2236,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1832]
+    (const void *)&gInstructions[1836]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = 
@@ -2260,7 +2260,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1956]
+    (const void *)&gInstructions[1960]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = 
@@ -2295,13 +2295,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1896]
+    (const void *)&gInstructions[1900]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1897]
+    (const void *)&gInstructions[1901]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = 
@@ -2327,7 +2327,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1899]
+    (const void *)&gInstructions[1903]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = 
@@ -2362,7 +2362,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2016]
+    (const void *)&gInstructions[2020]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = 
@@ -2388,7 +2388,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1900]
+    (const void *)&gInstructions[1904]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = 
@@ -2405,7 +2405,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1902]
+    (const void *)&gInstructions[1906]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = 
@@ -2431,7 +2431,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1904]
+    (const void *)&gInstructions[1908]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = 
@@ -2457,7 +2457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1905]
+    (const void *)&gInstructions[1909]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = 
@@ -2474,7 +2474,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1911]
+    (const void *)&gInstructions[1915]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = 
@@ -2500,13 +2500,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1944]
+    (const void *)&gInstructions[1948]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1947]
+    (const void *)&gInstructions[1951]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = 
@@ -2532,13 +2532,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1945]
+    (const void *)&gInstructions[1949]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1946]
+    (const void *)&gInstructions[1950]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = 
@@ -2564,7 +2564,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1950]
+    (const void *)&gInstructions[1954]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = 
@@ -2590,7 +2590,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1951]
+    (const void *)&gInstructions[1955]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = 
@@ -2625,7 +2625,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1953]
+    (const void *)&gInstructions[1957]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = 
@@ -2651,13 +2651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1954]
+    (const void *)&gInstructions[1958]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1959]
+    (const void *)&gInstructions[1963]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_w = 
@@ -2692,7 +2692,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1957]
+    (const void *)&gInstructions[1961]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = 
@@ -2716,7 +2716,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2168]
+    (const void *)&gInstructions[2172]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = 
@@ -2733,7 +2733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1961]
+    (const void *)&gInstructions[1965]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = 
@@ -2759,7 +2759,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1962]
+    (const void *)&gInstructions[1966]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = 
@@ -2794,7 +2794,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1974]
+    (const void *)&gInstructions[1978]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = 
@@ -2809,13 +2809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2170]
+    (const void *)&gInstructions[2174]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2213]
+    (const void *)&gInstructions[2217]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = 
@@ -2850,7 +2850,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1984]
+    (const void *)&gInstructions[1988]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = 
@@ -2876,13 +2876,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1998]
+    (const void *)&gInstructions[2002]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2001]
+    (const void *)&gInstructions[2005]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = 
@@ -2908,13 +2908,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1999]
+    (const void *)&gInstructions[2003]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2000]
+    (const void *)&gInstructions[2004]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = 
@@ -2940,13 +2940,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2008]
+    (const void *)&gInstructions[2012]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2009]
+    (const void *)&gInstructions[2013]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = 
@@ -2972,7 +2972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2010]
+    (const void *)&gInstructions[2014]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = 
@@ -2998,7 +2998,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2012]
+    (const void *)&gInstructions[2016]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = 
@@ -3024,13 +3024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2020]
+    (const void *)&gInstructions[2024]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2057]
+    (const void *)&gInstructions[2061]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = 
@@ -3056,13 +3056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2021]
+    (const void *)&gInstructions[2025]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2048]
+    (const void *)&gInstructions[2052]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = 
@@ -3088,13 +3088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2023]
+    (const void *)&gInstructions[2027]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2028]
+    (const void *)&gInstructions[2032]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = 
@@ -3120,13 +3120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2024]
+    (const void *)&gInstructions[2028]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2027]
+    (const void *)&gInstructions[2031]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = 
@@ -3152,13 +3152,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2025]
+    (const void *)&gInstructions[2029]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2026]
+    (const void *)&gInstructions[2030]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = 
@@ -3184,7 +3184,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2033]
+    (const void *)&gInstructions[2037]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = 
@@ -3210,7 +3210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2037]
+    (const void *)&gInstructions[2041]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = 
@@ -3236,13 +3236,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2041]
+    (const void *)&gInstructions[2045]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2045]
+    (const void *)&gInstructions[2049]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = 
@@ -3257,13 +3257,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2042]
+    (const void *)&gInstructions[2046]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2046]
+    (const void *)&gInstructions[2050]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = 
@@ -3300,13 +3300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2051]
+    (const void *)&gInstructions[2055]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2056]
+    (const void *)&gInstructions[2060]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = 
@@ -3332,13 +3332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2052]
+    (const void *)&gInstructions[2056]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2055]
+    (const void *)&gInstructions[2059]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = 
@@ -3364,13 +3364,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2053]
+    (const void *)&gInstructions[2057]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2054]
+    (const void *)&gInstructions[2058]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = 
@@ -3396,13 +3396,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2058]
+    (const void *)&gInstructions[2062]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2061]
+    (const void *)&gInstructions[2065]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = 
@@ -3428,13 +3428,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2059]
+    (const void *)&gInstructions[2063]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2060]
+    (const void *)&gInstructions[2064]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = 
@@ -3460,13 +3460,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2076]
+    (const void *)&gInstructions[2080]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2078]
+    (const void *)&gInstructions[2082]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = 
@@ -3501,13 +3501,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2080]
+    (const void *)&gInstructions[2084]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2082]
+    (const void *)&gInstructions[2086]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = 
@@ -3542,13 +3542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2118]
+    (const void *)&gInstructions[2122]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2119]
+    (const void *)&gInstructions[2123]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = 
@@ -3574,7 +3574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2132]
+    (const void *)&gInstructions[2136]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = 
@@ -3600,7 +3600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2133]
+    (const void *)&gInstructions[2137]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = 
@@ -3626,7 +3626,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2134]
+    (const void *)&gInstructions[2138]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = 
@@ -3643,7 +3643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2142]
+    (const void *)&gInstructions[2146]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = 
@@ -3660,13 +3660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2144]
+    (const void *)&gInstructions[2148]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2146]
+    (const void *)&gInstructions[2150]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = 
@@ -3692,13 +3692,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2151]
+    (const void *)&gInstructions[2155]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2153]
+    (const void *)&gInstructions[2157]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = 
@@ -3724,7 +3724,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2154]
+    (const void *)&gInstructions[2158]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = 
@@ -3741,19 +3741,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2156]
+    (const void *)&gInstructions[2160]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2175]
+    (const void *)&gInstructions[2179]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2176]
+    (const void *)&gInstructions[2180]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = 
@@ -3788,13 +3788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2158]
+    (const void *)&gInstructions[2162]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2160]
+    (const void *)&gInstructions[2164]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = 
@@ -3809,13 +3809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2171]
+    (const void *)&gInstructions[2175]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2179]
+    (const void *)&gInstructions[2183]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = 
@@ -3850,13 +3850,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2165]
+    (const void *)&gInstructions[2169]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2167]
+    (const void *)&gInstructions[2171]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = 
@@ -3882,7 +3882,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2172]
+    (const void *)&gInstructions[2176]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = 
@@ -3897,7 +3897,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2215]
+    (const void *)&gInstructions[2219]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = 
@@ -3914,7 +3914,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2173]
+    (const void *)&gInstructions[2177]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = 
@@ -3929,7 +3929,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2227]
+    (const void *)&gInstructions[2231]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = 
@@ -3946,13 +3946,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2174]
+    (const void *)&gInstructions[2178]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2177]
+    (const void *)&gInstructions[2181]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = 
@@ -3976,7 +3976,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2233]
+    (const void *)&gInstructions[2237]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = 
@@ -4002,7 +4002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2180]
+    (const void *)&gInstructions[2184]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = 
@@ -4017,7 +4017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2218]
+    (const void *)&gInstructions[2222]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = 
@@ -4034,7 +4034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2181]
+    (const void *)&gInstructions[2185]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = 
@@ -4049,7 +4049,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2224]
+    (const void *)&gInstructions[2228]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = 
@@ -4075,7 +4075,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2182]
+    (const void *)&gInstructions[2186]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = 
@@ -4090,7 +4090,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2230]
+    (const void *)&gInstructions[2234]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = 
@@ -4107,7 +4107,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2183]
+    (const void *)&gInstructions[2187]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = 
@@ -4122,7 +4122,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2189]
+    (const void *)&gInstructions[2193]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = 
@@ -4139,7 +4139,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2184]
+    (const void *)&gInstructions[2188]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = 
@@ -4154,7 +4154,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2201]
+    (const void *)&gInstructions[2205]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = 
@@ -4171,7 +4171,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2185]
+    (const void *)&gInstructions[2189]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = 
@@ -4186,7 +4186,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2192]
+    (const void *)&gInstructions[2196]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = 
@@ -4203,7 +4203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2186]
+    (const void *)&gInstructions[2190]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = 
@@ -4218,7 +4218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2198]
+    (const void *)&gInstructions[2202]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = 
@@ -4244,7 +4244,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2187]
+    (const void *)&gInstructions[2191]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = 
@@ -4259,7 +4259,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2204]
+    (const void *)&gInstructions[2208]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = 
@@ -4276,7 +4276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2188]
+    (const void *)&gInstructions[2192]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = 
@@ -4291,7 +4291,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2195]
+    (const void *)&gInstructions[2199]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = 
@@ -4308,7 +4308,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2207]
+    (const void *)&gInstructions[2211]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = 
@@ -4323,7 +4323,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2352]
+    (const void *)&gInstructions[2356]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = 
@@ -4349,7 +4349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2209]
+    (const void *)&gInstructions[2213]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = 
@@ -4364,7 +4364,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2338]
+    (const void *)&gInstructions[2342]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = 
@@ -4390,7 +4390,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2210]
+    (const void *)&gInstructions[2214]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = 
@@ -4405,13 +4405,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2260]
+    (const void *)&gInstructions[2264]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2261]
+    (const void *)&gInstructions[2265]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = 
@@ -4437,7 +4437,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2211]
+    (const void *)&gInstructions[2215]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = 
@@ -4452,13 +4452,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2264]
+    (const void *)&gInstructions[2268]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2265]
+    (const void *)&gInstructions[2269]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = 
@@ -4484,7 +4484,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2212]
+    (const void *)&gInstructions[2216]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = 
@@ -4499,7 +4499,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2371]
+    (const void *)&gInstructions[2375]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = 
@@ -4525,7 +4525,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2214]
+    (const void *)&gInstructions[2218]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = 
@@ -4540,7 +4540,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2221]
+    (const void *)&gInstructions[2225]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = 
@@ -4557,7 +4557,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2235]
+    (const void *)&gInstructions[2239]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = 
@@ -4574,13 +4574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2241]
+    (const void *)&gInstructions[2245]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2243]
+    (const void *)&gInstructions[2247]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = 
@@ -4606,7 +4606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2246]
+    (const void *)&gInstructions[2250]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = 
@@ -4632,13 +4632,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2249]
+    (const void *)&gInstructions[2253]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2252]
+    (const void *)&gInstructions[2256]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = 
@@ -4664,13 +4664,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2250]
+    (const void *)&gInstructions[2254]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2251]
+    (const void *)&gInstructions[2255]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = 
@@ -4696,13 +4696,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2280]
+    (const void *)&gInstructions[2284]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2281]
+    (const void *)&gInstructions[2285]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = 
@@ -4737,13 +4737,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2282]
+    (const void *)&gInstructions[2286]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2283]
+    (const void *)&gInstructions[2287]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = 
@@ -4778,13 +4778,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2299]
+    (const void *)&gInstructions[2303]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2300]
+    (const void *)&gInstructions[2304]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = 
@@ -4810,7 +4810,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2301]
+    (const void *)&gInstructions[2305]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = 
@@ -4836,13 +4836,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2308]
+    (const void *)&gInstructions[2312]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2309]
+    (const void *)&gInstructions[2313]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = 
@@ -4868,7 +4868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2312]
+    (const void *)&gInstructions[2316]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = 
@@ -4885,7 +4885,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2314]
+    (const void *)&gInstructions[2318]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = 
@@ -4911,13 +4911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2334]
+    (const void *)&gInstructions[2338]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2336]
+    (const void *)&gInstructions[2340]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = 
@@ -4943,13 +4943,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2349]
+    (const void *)&gInstructions[2353]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2351]
+    (const void *)&gInstructions[2355]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = 
@@ -4975,13 +4975,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2367]
+    (const void *)&gInstructions[2371]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2369]
+    (const void *)&gInstructions[2373]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = 
@@ -5007,13 +5007,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2395]
+    (const void *)&gInstructions[2399]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2398]
+    (const void *)&gInstructions[2402]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = 
@@ -5028,13 +5028,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2399]
+    (const void *)&gInstructions[2403]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2402]
+    (const void *)&gInstructions[2406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = 
@@ -5060,13 +5060,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2396]
+    (const void *)&gInstructions[2400]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2397]
+    (const void *)&gInstructions[2401]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = 
@@ -5081,13 +5081,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2400]
+    (const void *)&gInstructions[2404]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2401]
+    (const void *)&gInstructions[2405]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = 
@@ -5113,13 +5113,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2426]
+    (const void *)&gInstructions[2430]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2427]
+    (const void *)&gInstructions[2431]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = 
@@ -5145,13 +5145,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2428]
+    (const void *)&gInstructions[2432]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2429]
+    (const void *)&gInstructions[2433]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = 
@@ -5177,13 +5177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2430]
+    (const void *)&gInstructions[2434]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2431]
+    (const void *)&gInstructions[2435]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = 
@@ -5220,13 +5220,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2432]
+    (const void *)&gInstructions[2436]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2433]
+    (const void *)&gInstructions[2437]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = 
@@ -5252,13 +5252,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2448]
+    (const void *)&gInstructions[2452]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2449]
+    (const void *)&gInstructions[2453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = 
@@ -5284,13 +5284,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2450]
+    (const void *)&gInstructions[2454]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2451]
+    (const void *)&gInstructions[2455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = 
@@ -5316,13 +5316,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2452]
+    (const void *)&gInstructions[2456]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2453]
+    (const void *)&gInstructions[2457]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = 
@@ -5359,13 +5359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2454]
+    (const void *)&gInstructions[2458]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2455]
+    (const void *)&gInstructions[2459]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = 
@@ -5391,13 +5391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2458]
+    (const void *)&gInstructions[2462]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2459]
+    (const void *)&gInstructions[2463]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = 
@@ -5423,13 +5423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2460]
+    (const void *)&gInstructions[2464]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2461]
+    (const void *)&gInstructions[2465]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = 
@@ -5455,13 +5455,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2462]
+    (const void *)&gInstructions[2466]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2463]
+    (const void *)&gInstructions[2467]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = 
@@ -5496,13 +5496,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2472]
+    (const void *)&gInstructions[2476]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2473]
+    (const void *)&gInstructions[2477]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = 
@@ -5800,7 +5800,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1356]
+    (const void *)&gInstructions[1360]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = 
@@ -5815,7 +5815,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1358]
+    (const void *)&gInstructions[1362]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = 
@@ -5830,7 +5830,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1360]
+    (const void *)&gInstructions[1364]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = 
@@ -5845,7 +5845,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1362]
+    (const void *)&gInstructions[1366]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = 
@@ -5871,7 +5871,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1378]
+    (const void *)&gInstructions[1382]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = 
@@ -5886,7 +5886,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1380]
+    (const void *)&gInstructions[1384]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = 
@@ -5912,7 +5912,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1382]
+    (const void *)&gInstructions[1386]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = 
@@ -5927,7 +5927,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1384]
+    (const void *)&gInstructions[1388]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = 
@@ -5953,7 +5953,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1408]
+    (const void *)&gInstructions[1412]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = 
@@ -5968,7 +5968,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1410]
+    (const void *)&gInstructions[1414]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = 
@@ -5983,7 +5983,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1412]
+    (const void *)&gInstructions[1416]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = 
@@ -5998,7 +5998,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1414]
+    (const void *)&gInstructions[1418]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = 
@@ -6024,7 +6024,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1416]
+    (const void *)&gInstructions[1420]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = 
@@ -6039,7 +6039,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1418]
+    (const void *)&gInstructions[1422]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = 
@@ -6065,13 +6065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1422]
+    (const void *)&gInstructions[1426]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1451]
+    (const void *)&gInstructions[1455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = 
@@ -6086,7 +6086,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1429]
+    (const void *)&gInstructions[1433]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = 
@@ -6101,7 +6101,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1468]
+    (const void *)&gInstructions[1472]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = 
@@ -6127,13 +6127,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1425]
+    (const void *)&gInstructions[1429]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1452]
+    (const void *)&gInstructions[1456]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = 
@@ -6148,7 +6148,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1440]
+    (const void *)&gInstructions[1444]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = 
@@ -6163,7 +6163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1473]
+    (const void *)&gInstructions[1477]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = 
@@ -6189,7 +6189,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1431]
+    (const void *)&gInstructions[1435]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = 
@@ -6204,7 +6204,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1442]
+    (const void *)&gInstructions[1446]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = 
@@ -6219,7 +6219,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1455]
+    (const void *)&gInstructions[1459]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = 
@@ -6234,7 +6234,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1463]
+    (const void *)&gInstructions[1467]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = 
@@ -6260,13 +6260,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1434]
+    (const void *)&gInstructions[1438]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1448]
+    (const void *)&gInstructions[1452]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = 
@@ -6281,13 +6281,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1488]
+    (const void *)&gInstructions[1492]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1489]
+    (const void *)&gInstructions[1493]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = 
@@ -6302,7 +6302,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1490]
+    (const void *)&gInstructions[1494]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = 
@@ -6319,13 +6319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1435]
+    (const void *)&gInstructions[1439]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1449]
+    (const void *)&gInstructions[1453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = 
@@ -6340,13 +6340,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1436]
+    (const void *)&gInstructions[1440]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1450]
+    (const void *)&gInstructions[1454]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = 
@@ -6361,13 +6361,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1457]
+    (const void *)&gInstructions[1461]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1467]
+    (const void *)&gInstructions[1471]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = 
@@ -6384,13 +6384,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1453]
+    (const void *)&gInstructions[1457]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1465]
+    (const void *)&gInstructions[1469]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = 
@@ -6407,13 +6407,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1458]
+    (const void *)&gInstructions[1462]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1459]
+    (const void *)&gInstructions[1463]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = 
@@ -6428,7 +6428,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1461]
+    (const void *)&gInstructions[1465]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = 
@@ -6445,13 +6445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1470]
+    (const void *)&gInstructions[1474]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1475]
+    (const void *)&gInstructions[1479]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = 
@@ -6466,13 +6466,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1484]
+    (const void *)&gInstructions[1488]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1486]
+    (const void *)&gInstructions[1490]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = 
@@ -6487,13 +6487,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1485]
+    (const void *)&gInstructions[1489]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1487]
+    (const void *)&gInstructions[1491]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = 
@@ -6519,13 +6519,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1471]
+    (const void *)&gInstructions[1475]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1476]
+    (const void *)&gInstructions[1480]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = 
@@ -6540,13 +6540,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1472]
+    (const void *)&gInstructions[1476]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1477]
+    (const void *)&gInstructions[1481]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = 
@@ -6561,13 +6561,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1480]
+    (const void *)&gInstructions[1484]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1483]
+    (const void *)&gInstructions[1487]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = 
@@ -6584,13 +6584,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1478]
+    (const void *)&gInstructions[1482]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1481]
+    (const void *)&gInstructions[1485]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = 
@@ -6607,7 +6607,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1492]
+    (const void *)&gInstructions[1496]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = 
@@ -6622,7 +6622,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1494]
+    (const void *)&gInstructions[1498]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = 
@@ -6637,7 +6637,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1496]
+    (const void *)&gInstructions[1500]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = 
@@ -6652,7 +6652,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1498]
+    (const void *)&gInstructions[1502]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = 
@@ -6678,7 +6678,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1750]
+    (const void *)&gInstructions[1754]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = 
@@ -6693,7 +6693,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1752]
+    (const void *)&gInstructions[1756]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = 
@@ -6708,7 +6708,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1754]
+    (const void *)&gInstructions[1758]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = 
@@ -6723,7 +6723,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1756]
+    (const void *)&gInstructions[1760]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = 
@@ -6749,7 +6749,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1763]
+    (const void *)&gInstructions[1767]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = 
@@ -6764,7 +6764,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1765]
+    (const void *)&gInstructions[1769]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = 
@@ -6779,7 +6779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1767]
+    (const void *)&gInstructions[1771]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = 
@@ -6794,7 +6794,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1769]
+    (const void *)&gInstructions[1773]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = 
@@ -6820,7 +6820,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1775]
+    (const void *)&gInstructions[1779]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = 
@@ -6835,7 +6835,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1779]
+    (const void *)&gInstructions[1783]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = 
@@ -6861,7 +6861,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1776]
+    (const void *)&gInstructions[1780]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = 
@@ -6876,7 +6876,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1780]
+    (const void *)&gInstructions[1784]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = 
@@ -6902,13 +6902,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1783]
+    (const void *)&gInstructions[1787]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1838]
+    (const void *)&gInstructions[1842]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_w = 
@@ -6945,13 +6945,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1784]
+    (const void *)&gInstructions[1788]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1839]
+    (const void *)&gInstructions[1843]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_w = 
@@ -6977,7 +6977,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1840]
+    (const void *)&gInstructions[1844]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = 
@@ -7014,7 +7014,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1787]
+    (const void *)&gInstructions[1791]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = 
@@ -7029,7 +7029,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1788]
+    (const void *)&gInstructions[1792]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = 
@@ -7044,7 +7044,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1789]
+    (const void *)&gInstructions[1793]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = 
@@ -7070,7 +7070,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1808]
+    (const void *)&gInstructions[1812]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = 
@@ -7096,7 +7096,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1824]
+    (const void *)&gInstructions[1828]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = 
@@ -7131,7 +7131,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1820]
+    (const void *)&gInstructions[1824]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = 
@@ -7166,7 +7166,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1856]
+    (const void *)&gInstructions[1860]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = 
@@ -7192,13 +7192,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1794]
+    (const void *)&gInstructions[1798]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1796]
+    (const void *)&gInstructions[1800]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = 
@@ -7213,13 +7213,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1800]
+    (const void *)&gInstructions[1804]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1806]
+    (const void *)&gInstructions[1810]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = 
@@ -7234,13 +7234,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1802]
+    (const void *)&gInstructions[1806]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1804]
+    (const void *)&gInstructions[1808]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = 
@@ -7266,13 +7266,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1795]
+    (const void *)&gInstructions[1799]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1797]
+    (const void *)&gInstructions[1801]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = 
@@ -7287,13 +7287,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1801]
+    (const void *)&gInstructions[1805]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1807]
+    (const void *)&gInstructions[1811]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = 
@@ -7308,13 +7308,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1803]
+    (const void *)&gInstructions[1807]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1805]
+    (const void *)&gInstructions[1809]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = 
@@ -7340,7 +7340,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1810]
+    (const void *)&gInstructions[1814]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = 
@@ -7375,7 +7375,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1814]
+    (const void *)&gInstructions[1818]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = 
@@ -7401,7 +7401,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1818]
+    (const void *)&gInstructions[1822]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = 
@@ -7436,7 +7436,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1854]
+    (const void *)&gInstructions[1858]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = 
@@ -7462,7 +7462,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1811]
+    (const void *)&gInstructions[1815]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = 
@@ -7497,7 +7497,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1815]
+    (const void *)&gInstructions[1819]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = 
@@ -7543,7 +7543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1821]
+    (const void *)&gInstructions[1825]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = 
@@ -7578,7 +7578,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1825]
+    (const void *)&gInstructions[1829]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = 
@@ -7624,7 +7624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1830]
+    (const void *)&gInstructions[1834]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = 
@@ -7659,7 +7659,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1834]
+    (const void *)&gInstructions[1838]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = 
@@ -7683,7 +7683,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1836]
+    (const void *)&gInstructions[1840]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = 
@@ -7718,7 +7718,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1841]
+    (const void *)&gInstructions[1845]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = 
@@ -7755,7 +7755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1846]
+    (const void *)&gInstructions[1850]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = 
@@ -7770,7 +7770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1847]
+    (const void *)&gInstructions[1851]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = 
@@ -7794,7 +7794,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1858]
+    (const void *)&gInstructions[1862]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = 
@@ -7809,7 +7809,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1859]
+    (const void *)&gInstructions[1863]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = 
@@ -7833,7 +7833,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1866]
+    (const void *)&gInstructions[1870]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = 
@@ -7848,7 +7848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1870]
+    (const void *)&gInstructions[1874]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = 
@@ -7874,7 +7874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1848]
+    (const void *)&gInstructions[1852]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = 
@@ -7889,7 +7889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1849]
+    (const void *)&gInstructions[1853]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = 
@@ -7913,7 +7913,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1860]
+    (const void *)&gInstructions[1864]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = 
@@ -7928,7 +7928,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1861]
+    (const void *)&gInstructions[1865]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = 
@@ -7952,7 +7952,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1867]
+    (const void *)&gInstructions[1871]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = 
@@ -7967,7 +7967,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1871]
+    (const void *)&gInstructions[1875]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = 
@@ -7993,7 +7993,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1881]
+    (const void *)&gInstructions[1885]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = 
@@ -8008,7 +8008,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1883]
+    (const void *)&gInstructions[1887]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = 
@@ -8023,7 +8023,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1885]
+    (const void *)&gInstructions[1889]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = 
@@ -8038,7 +8038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1887]
+    (const void *)&gInstructions[1891]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = 
@@ -8064,7 +8064,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1892]
+    (const void *)&gInstructions[1896]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = 
@@ -8079,7 +8079,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1894]
+    (const void *)&gInstructions[1898]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = 
@@ -8105,7 +8105,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1907]
+    (const void *)&gInstructions[1911]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = 
@@ -8131,7 +8131,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1909]
+    (const void *)&gInstructions[1913]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = 
@@ -8148,7 +8148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1913]
+    (const void *)&gInstructions[1917]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = 
@@ -8165,7 +8165,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1915]
+    (const void *)&gInstructions[1919]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = 
@@ -8182,7 +8182,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1917]
+    (const void *)&gInstructions[1921]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = 
@@ -8208,7 +8208,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1919]
+    (const void *)&gInstructions[1923]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = 
@@ -8234,7 +8234,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1921]
+    (const void *)&gInstructions[1925]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = 
@@ -8251,7 +8251,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1923]
+    (const void *)&gInstructions[1927]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = 
@@ -8268,7 +8268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1925]
+    (const void *)&gInstructions[1929]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = 
@@ -8285,7 +8285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1927]
+    (const void *)&gInstructions[1931]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = 
@@ -8302,7 +8302,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1929]
+    (const void *)&gInstructions[1933]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = 
@@ -8319,13 +8319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1934]
+    (const void *)&gInstructions[1938]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1938]
+    (const void *)&gInstructions[1942]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = 
@@ -8351,13 +8351,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1936]
+    (const void *)&gInstructions[1940]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1937]
+    (const void *)&gInstructions[1941]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = 
@@ -8383,7 +8383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1939]
+    (const void *)&gInstructions[1943]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = 
@@ -8400,7 +8400,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1941]
+    (const void *)&gInstructions[1945]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = 
@@ -8417,7 +8417,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1970]
+    (const void *)&gInstructions[1974]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = 
@@ -8434,7 +8434,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1972]
+    (const void *)&gInstructions[1976]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = 
@@ -8451,7 +8451,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1976]
+    (const void *)&gInstructions[1980]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = 
@@ -8468,7 +8468,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1980]
+    (const void *)&gInstructions[1984]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = 
@@ -8485,7 +8485,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1982]
+    (const void *)&gInstructions[1986]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = 
@@ -8511,7 +8511,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1986]
+    (const void *)&gInstructions[1990]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = 
@@ -8528,7 +8528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2070]
+    (const void *)&gInstructions[2074]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = 
@@ -8565,7 +8565,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2114]
+    (const void *)&gInstructions[2118]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = 
@@ -8582,7 +8582,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2115]
+    (const void *)&gInstructions[2119]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = 
@@ -8619,7 +8619,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2136]
+    (const void *)&gInstructions[2140]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = 
@@ -8636,7 +8636,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2147]
+    (const void *)&gInstructions[2151]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = 
@@ -8653,7 +8653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2149]
+    (const void *)&gInstructions[2153]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = 
@@ -8670,7 +8670,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2161]
+    (const void *)&gInstructions[2165]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = 
@@ -8687,7 +8687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2163]
+    (const void *)&gInstructions[2167]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = 
@@ -8704,7 +8704,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2237]
+    (const void *)&gInstructions[2241]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = 
@@ -8721,7 +8721,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2239]
+    (const void *)&gInstructions[2243]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = 
@@ -8738,7 +8738,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2244]
+    (const void *)&gInstructions[2248]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = 
@@ -8755,7 +8755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2247]
+    (const void *)&gInstructions[2251]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = 
@@ -8781,13 +8781,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2254]
+    (const void *)&gInstructions[2258]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2255]
+    (const void *)&gInstructions[2259]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = 
@@ -8813,13 +8813,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2258]
+    (const void *)&gInstructions[2262]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2259]
+    (const void *)&gInstructions[2263]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = 
@@ -8834,13 +8834,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2262]
+    (const void *)&gInstructions[2266]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2263]
+    (const void *)&gInstructions[2267]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = 
@@ -8855,7 +8855,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2324]
+    (const void *)&gInstructions[2328]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = 
@@ -8870,13 +8870,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2343]
+    (const void *)&gInstructions[2347]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2347]
+    (const void *)&gInstructions[2351]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = 
@@ -8891,7 +8891,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2357]
+    (const void *)&gInstructions[2361]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = 
@@ -8932,7 +8932,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2278]
+    (const void *)&gInstructions[2282]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = 
@@ -8949,7 +8949,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2315]
+    (const void *)&gInstructions[2319]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = 
@@ -8964,13 +8964,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2317]
+    (const void *)&gInstructions[2321]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2319]
+    (const void *)&gInstructions[2323]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = 
@@ -8987,7 +8987,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2325]
+    (const void *)&gInstructions[2329]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = 
@@ -9013,13 +9013,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2328]
+    (const void *)&gInstructions[2332]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2330]
+    (const void *)&gInstructions[2334]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = 
@@ -9034,13 +9034,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2361]
+    (const void *)&gInstructions[2365]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2363]
+    (const void *)&gInstructions[2367]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = 
@@ -9081,7 +9081,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2331]
+    (const void *)&gInstructions[2335]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = 
@@ -9107,19 +9107,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2339]
+    (const void *)&gInstructions[2343]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2353]
+    (const void *)&gInstructions[2357]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2372]
+    (const void *)&gInstructions[2376]
 };
 
 const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = 
@@ -9151,7 +9151,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2340]
+    (const void *)&gInstructions[2344]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = 
@@ -9168,13 +9168,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2344]
+    (const void *)&gInstructions[2348]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2348]
+    (const void *)&gInstructions[2352]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = 
@@ -9200,7 +9200,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2354]
+    (const void *)&gInstructions[2358]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = 
@@ -9217,7 +9217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2358]
+    (const void *)&gInstructions[2362]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = 
@@ -9243,7 +9243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2364]
+    (const void *)&gInstructions[2368]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = 
@@ -9269,7 +9269,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2373]
+    (const void *)&gInstructions[2377]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = 
@@ -9286,7 +9286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2376]
+    (const void *)&gInstructions[2380]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = 
@@ -9303,7 +9303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2378]
+    (const void *)&gInstructions[2382]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = 
@@ -9329,7 +9329,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2380]
+    (const void *)&gInstructions[2384]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = 
@@ -9355,7 +9355,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2382]
+    (const void *)&gInstructions[2386]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = 
@@ -9372,7 +9372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2384]
+    (const void *)&gInstructions[2388]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = 
@@ -9389,7 +9389,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2386]
+    (const void *)&gInstructions[2390]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = 
@@ -9406,7 +9406,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2388]
+    (const void *)&gInstructions[2392]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = 
@@ -9423,7 +9423,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2390]
+    (const void *)&gInstructions[2394]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = 
@@ -9440,7 +9440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2403]
+    (const void *)&gInstructions[2407]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = 
@@ -9457,7 +9457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2405]
+    (const void *)&gInstructions[2409]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = 
@@ -9483,7 +9483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2407]
+    (const void *)&gInstructions[2411]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = 
@@ -9509,7 +9509,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2409]
+    (const void *)&gInstructions[2413]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = 
@@ -9526,7 +9526,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2411]
+    (const void *)&gInstructions[2415]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = 
@@ -9543,7 +9543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2413]
+    (const void *)&gInstructions[2417]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = 
@@ -9569,7 +9569,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2415]
+    (const void *)&gInstructions[2419]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = 
@@ -9595,7 +9595,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2417]
+    (const void *)&gInstructions[2421]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = 
@@ -9612,13 +9612,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2420]
+    (const void *)&gInstructions[2424]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2421]
+    (const void *)&gInstructions[2425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = 
@@ -9644,7 +9644,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2478]
+    (const void *)&gInstructions[2482]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = 
@@ -9659,7 +9659,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2480]
+    (const void *)&gInstructions[2484]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = 
@@ -9685,7 +9685,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2482]
+    (const void *)&gInstructions[2486]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = 
@@ -9700,7 +9700,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2484]
+    (const void *)&gInstructions[2488]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = 
@@ -9715,7 +9715,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2486]
+    (const void *)&gInstructions[2490]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = 
@@ -9730,7 +9730,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2488]
+    (const void *)&gInstructions[2492]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = 
@@ -9756,7 +9756,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2491]
+    (const void *)&gInstructions[2495]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = 
@@ -9771,7 +9771,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2493]
+    (const void *)&gInstructions[2497]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = 
@@ -9786,7 +9786,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2495]
+    (const void *)&gInstructions[2499]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = 
@@ -9801,7 +9801,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2497]
+    (const void *)&gInstructions[2501]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = 
@@ -9827,7 +9827,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2501]
+    (const void *)&gInstructions[2505]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = 
@@ -9842,7 +9842,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2503]
+    (const void *)&gInstructions[2507]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = 
@@ -9868,7 +9868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2505]
+    (const void *)&gInstructions[2509]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = 
@@ -9883,7 +9883,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2507]
+    (const void *)&gInstructions[2511]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = 
@@ -9909,7 +9909,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2509]
+    (const void *)&gInstructions[2513]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = 
@@ -9924,7 +9924,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2511]
+    (const void *)&gInstructions[2515]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = 
@@ -9950,7 +9950,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2513]
+    (const void *)&gInstructions[2517]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = 
@@ -9965,7 +9965,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2515]
+    (const void *)&gInstructions[2519]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = 
@@ -10254,13 +10254,13 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1376]
+    (const void *)&gInstructions[1380]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1377]
+    (const void *)&gInstructions[1381]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = 
@@ -10286,7 +10286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1445]
+    (const void *)&gInstructions[1449]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = 
@@ -10312,7 +10312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1491]
+    (const void *)&gInstructions[1495]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = 
@@ -10338,13 +10338,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1510]
+    (const void *)&gInstructions[1514]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1512]
+    (const void *)&gInstructions[1516]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = 
@@ -10370,13 +10370,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1511]
+    (const void *)&gInstructions[1515]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1513]
+    (const void *)&gInstructions[1517]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = 
@@ -10413,13 +10413,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1515]
+    (const void *)&gInstructions[1519]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1517]
+    (const void *)&gInstructions[1521]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = 
@@ -10445,13 +10445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1516]
+    (const void *)&gInstructions[1520]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1518]
+    (const void *)&gInstructions[1522]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = 
@@ -10488,7 +10488,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1519]
+    (const void *)&gInstructions[1523]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = 
@@ -10505,7 +10505,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1520]
+    (const void *)&gInstructions[1524]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = 
@@ -10542,13 +10542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1523]
+    (const void *)&gInstructions[1527]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1524]
+    (const void *)&gInstructions[1528]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = 
@@ -10574,13 +10574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1525]
+    (const void *)&gInstructions[1529]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1526]
+    (const void *)&gInstructions[1530]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = 
@@ -10606,13 +10606,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1687]
+    (const void *)&gInstructions[1691]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1688]
+    (const void *)&gInstructions[1692]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = 
@@ -10638,13 +10638,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1689]
+    (const void *)&gInstructions[1693]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1690]
+    (const void *)&gInstructions[1694]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = 
@@ -10670,13 +10670,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1715]
+    (const void *)&gInstructions[1719]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1716]
+    (const void *)&gInstructions[1720]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = 
@@ -10702,13 +10702,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1717]
+    (const void *)&gInstructions[1721]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1718]
+    (const void *)&gInstructions[1722]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = 
@@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1719]
+    (const void *)&gInstructions[1723]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = 
@@ -10760,7 +10760,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1721]
+    (const void *)&gInstructions[1725]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = 
@@ -10786,13 +10786,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1730]
+    (const void *)&gInstructions[1734]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1732]
+    (const void *)&gInstructions[1736]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = 
@@ -10818,13 +10818,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1731]
+    (const void *)&gInstructions[1735]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1733]
+    (const void *)&gInstructions[1737]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = 
@@ -10861,13 +10861,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1735]
+    (const void *)&gInstructions[1739]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1737]
+    (const void *)&gInstructions[1741]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = 
@@ -10893,13 +10893,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1736]
+    (const void *)&gInstructions[1740]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1738]
+    (const void *)&gInstructions[1742]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = 
@@ -10936,7 +10936,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1739]
+    (const void *)&gInstructions[1743]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = 
@@ -10953,7 +10953,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1740]
+    (const void *)&gInstructions[1744]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = 
@@ -10990,7 +10990,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1931]
+    (const void *)&gInstructions[1935]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = 
@@ -11007,7 +11007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1964]
+    (const void *)&gInstructions[1968]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = 
@@ -11024,13 +11024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1968]
+    (const void *)&gInstructions[1972]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1995]
+    (const void *)&gInstructions[1999]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = 
@@ -11056,13 +11056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1969]
+    (const void *)&gInstructions[1973]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1990]
+    (const void *)&gInstructions[1994]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = 
@@ -11088,13 +11088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1991]
+    (const void *)&gInstructions[1995]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1994]
+    (const void *)&gInstructions[1998]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = 
@@ -11120,13 +11120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1992]
+    (const void *)&gInstructions[1996]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1993]
+    (const void *)&gInstructions[1997]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = 
@@ -11152,7 +11152,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2034]
+    (const void *)&gInstructions[2038]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = 
@@ -11178,7 +11178,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2038]
+    (const void *)&gInstructions[2042]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = 
@@ -11204,7 +11204,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2043]
+    (const void *)&gInstructions[2047]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = 
@@ -11230,7 +11230,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2049]
+    (const void *)&gInstructions[2053]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = 
@@ -11256,7 +11256,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2062]
+    (const void *)&gInstructions[2066]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = 
@@ -11273,7 +11273,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2063]
+    (const void *)&gInstructions[2067]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = 
@@ -11310,13 +11310,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2066]
+    (const void *)&gInstructions[2070]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2068]
+    (const void *)&gInstructions[2072]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_w = 
@@ -11353,7 +11353,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2071]
+    (const void *)&gInstructions[2075]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = 
@@ -11370,7 +11370,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2072]
+    (const void *)&gInstructions[2076]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = 
@@ -11407,7 +11407,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2106]
+    (const void *)&gInstructions[2110]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = 
@@ -11424,7 +11424,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2107]
+    (const void *)&gInstructions[2111]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = 
@@ -11461,13 +11461,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2110]
+    (const void *)&gInstructions[2114]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2112]
+    (const void *)&gInstructions[2116]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_w = 
@@ -11504,13 +11504,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2297]
+    (const void *)&gInstructions[2301]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2298]
+    (const void *)&gInstructions[2302]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = 
@@ -11536,7 +11536,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2302]
+    (const void *)&gInstructions[2306]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = 
@@ -11562,13 +11562,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2306]
+    (const void *)&gInstructions[2310]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2307]
+    (const void *)&gInstructions[2311]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = 
@@ -11594,7 +11594,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2311]
+    (const void *)&gInstructions[2315]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = 
@@ -11620,13 +11620,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2392]
+    (const void *)&gInstructions[2396]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2393]
+    (const void *)&gInstructions[2397]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = 
@@ -11652,13 +11652,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2422]
+    (const void *)&gInstructions[2426]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2423]
+    (const void *)&gInstructions[2427]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = 
@@ -11684,13 +11684,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2424]
+    (const void *)&gInstructions[2428]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2425]
+    (const void *)&gInstructions[2429]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = 
@@ -11716,13 +11716,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2436]
+    (const void *)&gInstructions[2440]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2437]
+    (const void *)&gInstructions[2441]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = 
@@ -11748,13 +11748,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2438]
+    (const void *)&gInstructions[2442]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2439]
+    (const void *)&gInstructions[2443]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = 
@@ -11780,7 +11780,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2440]
+    (const void *)&gInstructions[2444]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = 
@@ -11806,7 +11806,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2441]
+    (const void *)&gInstructions[2445]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = 
@@ -11832,7 +11832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2442]
+    (const void *)&gInstructions[2446]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = 
@@ -11858,7 +11858,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2443]
+    (const void *)&gInstructions[2447]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = 
@@ -11884,13 +11884,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2474]
+    (const void *)&gInstructions[2478]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2475]
+    (const void *)&gInstructions[2479]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = 
@@ -11916,13 +11916,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2476]
+    (const void *)&gInstructions[2480]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2477]
+    (const void *)&gInstructions[2481]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = 
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
index 3fec085..a86cb29 100644
--- a/bddisasm/include/table_root.h
+++ b/bddisasm/include/table_root.h
@@ -88,25 +88,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[796]
+    (const void *)&gInstructions[800]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1199]
+    (const void *)&gInstructions[1203]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1299]
+    (const void *)&gInstructions[1303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2559]
+    (const void *)&gInstructions[2563]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = 
@@ -151,25 +151,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[797]
+    (const void *)&gInstructions[801]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1200]
+    (const void *)&gInstructions[1204]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1300]
+    (const void *)&gInstructions[1304]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2560]
+    (const void *)&gInstructions[2564]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = 
@@ -214,25 +214,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[798]
+    (const void *)&gInstructions[802]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1201]
+    (const void *)&gInstructions[1205]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1301]
+    (const void *)&gInstructions[1305]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2561]
+    (const void *)&gInstructions[2565]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = 
@@ -277,25 +277,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[799]
+    (const void *)&gInstructions[803]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1202]
+    (const void *)&gInstructions[1206]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1302]
+    (const void *)&gInstructions[1306]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2562]
+    (const void *)&gInstructions[2566]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = 
@@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2527]
+    (const void *)&gInstructions[2531]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2528]
+    (const void *)&gInstructions[2532]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = 
@@ -664,7 +664,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[580]
+    (const void *)&gInstructions[584]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix = 
@@ -764,13 +764,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[654]
+    (const void *)&gInstructions[658]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[655]
+    (const void *)&gInstructions[659]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = 
@@ -853,13 +853,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[656]
+    (const void *)&gInstructions[660]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[657]
+    (const void *)&gInstructions[661]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = 
@@ -983,7 +983,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[663]
+    (const void *)&gInstructions[667]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = 
@@ -1009,7 +1009,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[397]
+    (const void *)&gInstructions[399]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = 
@@ -1026,7 +1026,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[442]
+    (const void *)&gInstructions[444]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = 
@@ -1052,7 +1052,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[446]
+    (const void *)&gInstructions[448]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = 
@@ -1078,7 +1078,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[447]
+    (const void *)&gInstructions[449]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = 
@@ -1104,7 +1104,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[664]
+    (const void *)&gInstructions[668]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = 
@@ -1130,7 +1130,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[682]
+    (const void *)&gInstructions[686]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = 
@@ -1156,13 +1156,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[812]
+    (const void *)&gInstructions[816]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[813]
+    (const void *)&gInstructions[817]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = 
@@ -1179,13 +1179,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[814]
+    (const void *)&gInstructions[818]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[815]
+    (const void *)&gInstructions[819]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = 
@@ -1202,13 +1202,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[816]
+    (const void *)&gInstructions[820]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[817]
+    (const void *)&gInstructions[821]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = 
@@ -1225,7 +1225,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[822]
+    (const void *)&gInstructions[826]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = 
@@ -1242,7 +1242,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[853]
+    (const void *)&gInstructions[857]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = 
@@ -1259,7 +1259,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[860]
+    (const void *)&gInstructions[864]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = 
@@ -1276,7 +1276,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[869]
+    (const void *)&gInstructions[873]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = 
@@ -1293,13 +1293,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[906]
+    (const void *)&gInstructions[910]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[907]
+    (const void *)&gInstructions[911]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = 
@@ -1316,13 +1316,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[908]
+    (const void *)&gInstructions[912]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[909]
+    (const void *)&gInstructions[913]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = 
@@ -1339,13 +1339,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[910]
+    (const void *)&gInstructions[914]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[911]
+    (const void *)&gInstructions[915]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = 
@@ -1362,7 +1362,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[912]
+    (const void *)&gInstructions[916]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = 
@@ -1379,13 +1379,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[913]
+    (const void *)&gInstructions[917]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[914]
+    (const void *)&gInstructions[918]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = 
@@ -1402,13 +1402,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[915]
+    (const void *)&gInstructions[919]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[916]
+    (const void *)&gInstructions[920]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = 
@@ -1425,13 +1425,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[917]
+    (const void *)&gInstructions[921]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[918]
+    (const void *)&gInstructions[922]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = 
@@ -1448,13 +1448,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[929]
+    (const void *)&gInstructions[933]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[930]
+    (const void *)&gInstructions[934]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = 
@@ -1471,7 +1471,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[933]
+    (const void *)&gInstructions[937]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = 
@@ -1488,7 +1488,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[934]
+    (const void *)&gInstructions[938]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = 
@@ -1505,7 +1505,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[939]
+    (const void *)&gInstructions[943]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = 
@@ -1522,7 +1522,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[940]
+    (const void *)&gInstructions[944]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = 
@@ -1539,7 +1539,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[941]
+    (const void *)&gInstructions[945]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = 
@@ -1556,7 +1556,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[942]
+    (const void *)&gInstructions[946]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = 
@@ -1573,7 +1573,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[947]
+    (const void *)&gInstructions[951]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = 
@@ -1590,7 +1590,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[948]
+    (const void *)&gInstructions[952]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = 
@@ -1607,7 +1607,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[951]
+    (const void *)&gInstructions[955]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = 
@@ -1624,7 +1624,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[952]
+    (const void *)&gInstructions[956]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = 
@@ -1641,7 +1641,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[953]
+    (const void *)&gInstructions[957]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = 
@@ -1658,7 +1658,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[954]
+    (const void *)&gInstructions[958]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = 
@@ -1675,7 +1675,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[955]
+    (const void *)&gInstructions[959]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = 
@@ -1692,7 +1692,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[956]
+    (const void *)&gInstructions[960]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = 
@@ -1709,7 +1709,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[957]
+    (const void *)&gInstructions[961]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = 
@@ -1726,7 +1726,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[958]
+    (const void *)&gInstructions[962]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = 
@@ -1743,7 +1743,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[959]
+    (const void *)&gInstructions[963]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = 
@@ -1760,7 +1760,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[960]
+    (const void *)&gInstructions[964]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = 
@@ -1777,7 +1777,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[961]
+    (const void *)&gInstructions[965]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = 
@@ -1794,7 +1794,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[962]
+    (const void *)&gInstructions[966]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = 
@@ -1811,7 +1811,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[963]
+    (const void *)&gInstructions[967]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = 
@@ -1828,13 +1828,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[964]
+    (const void *)&gInstructions[968]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[965]
+    (const void *)&gInstructions[969]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = 
@@ -1851,7 +1851,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[971]
+    (const void *)&gInstructions[975]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = 
@@ -1868,13 +1868,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1012]
+    (const void *)&gInstructions[1016]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1013]
+    (const void *)&gInstructions[1017]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = 
@@ -1891,13 +1891,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1018]
+    (const void *)&gInstructions[1022]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1019]
+    (const void *)&gInstructions[1023]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = 
@@ -1914,13 +1914,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1020]
+    (const void *)&gInstructions[1024]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1021]
+    (const void *)&gInstructions[1025]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = 
@@ -1937,13 +1937,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1022]
+    (const void *)&gInstructions[1026]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1023]
+    (const void *)&gInstructions[1027]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = 
@@ -1960,7 +1960,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1076]
+    (const void *)&gInstructions[1080]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = 
@@ -1977,7 +1977,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1235]
+    (const void *)&gInstructions[1239]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = 
@@ -1994,7 +1994,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1236]
+    (const void *)&gInstructions[1240]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = 
@@ -2011,7 +2011,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1237]
+    (const void *)&gInstructions[1241]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = 
@@ -2028,7 +2028,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1239]
+    (const void *)&gInstructions[1243]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = 
@@ -2045,7 +2045,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1240]
+    (const void *)&gInstructions[1244]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = 
@@ -2062,7 +2062,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1241]
+    (const void *)&gInstructions[1245]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = 
@@ -2079,13 +2079,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2529]
+    (const void *)&gInstructions[2533]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2530]
+    (const void *)&gInstructions[2534]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = 
@@ -2530,7 +2530,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[239]
+    (const void *)&gInstructions[241]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = 
@@ -2547,7 +2547,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[395]
+    (const void *)&gInstructions[397]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = 
@@ -2564,7 +2564,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[396]
+    (const void *)&gInstructions[398]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = 
@@ -2581,7 +2581,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[401]
+    (const void *)&gInstructions[403]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_f0_reg_00_00_mprefix = 
@@ -2637,7 +2637,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_f0_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[431]
+    (const void *)&gInstructions[433]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = 
@@ -2654,7 +2654,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[432]
+    (const void *)&gInstructions[434]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = 
@@ -2680,7 +2680,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[721]
+    (const void *)&gInstructions[725]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = 
@@ -2697,13 +2697,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[841]
+    (const void *)&gInstructions[845]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[842]
+    (const void *)&gInstructions[846]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = 
@@ -2720,7 +2720,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[854]
+    (const void *)&gInstructions[858]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = 
@@ -2737,7 +2737,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[855]
+    (const void *)&gInstructions[859]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = 
@@ -2754,7 +2754,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[863]
+    (const void *)&gInstructions[867]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = 
@@ -2771,7 +2771,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[864]
+    (const void *)&gInstructions[868]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = 
@@ -2788,7 +2788,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[872]
+    (const void *)&gInstructions[876]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = 
@@ -2805,7 +2805,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[873]
+    (const void *)&gInstructions[877]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = 
@@ -2822,7 +2822,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[877]
+    (const void *)&gInstructions[881]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = 
@@ -2839,7 +2839,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[878]
+    (const void *)&gInstructions[882]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = 
@@ -2865,13 +2865,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[879]
+    (const void *)&gInstructions[883]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[880]
+    (const void *)&gInstructions[884]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary = 
@@ -2901,7 +2901,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[883]
+    (const void *)&gInstructions[887]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = 
@@ -2918,7 +2918,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[884]
+    (const void *)&gInstructions[888]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = 
@@ -2944,7 +2944,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[921]
+    (const void *)&gInstructions[925]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = 
@@ -2961,7 +2961,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[922]
+    (const void *)&gInstructions[926]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = 
@@ -2987,13 +2987,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[923]
+    (const void *)&gInstructions[927]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[924]
+    (const void *)&gInstructions[928]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = 
@@ -3023,7 +3023,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1166]
+    (const void *)&gInstructions[1170]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = 
@@ -3040,7 +3040,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1167]
+    (const void *)&gInstructions[1171]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = 
@@ -3057,7 +3057,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1168]
+    (const void *)&gInstructions[1172]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = 
@@ -3074,7 +3074,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1169]
+    (const void *)&gInstructions[1173]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = 
@@ -3091,7 +3091,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1238]
+    (const void *)&gInstructions[1242]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = 
@@ -3476,7 +3476,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[756]
+    (const void *)&gInstructions[760]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_reg_mprefix = 
@@ -3502,7 +3502,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_mpx_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[750]
+    (const void *)&gInstructions[754]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = 
@@ -3566,13 +3566,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[757]
+    (const void *)&gInstructions[761]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[758]
+    (const void *)&gInstructions[762]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_reg_mprefix = 
@@ -3598,7 +3598,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_mpx_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[751]
+    (const void *)&gInstructions[755]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = 
@@ -3621,7 +3621,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1338]
+    (const void *)&gInstructions[1342]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = 
@@ -3646,7 +3646,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[598]
+    (const void *)&gInstructions[602]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = 
@@ -3779,14 +3779,26 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_NP_leaf =
     (const void *)&gInstructions[114]
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F2_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[239]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[240]
+};
+
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_02_NP_leaf,
         /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F3_leaf,
+        /* 03 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F2_leaf,
     }
 };
 
@@ -3799,7 +3811,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1211]
+    (const void *)&gInstructions[1215]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = 
@@ -3816,7 +3828,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[611]
+    (const void *)&gInstructions[615]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = 
@@ -3833,7 +3845,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[729]
+    (const void *)&gInstructions[733]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = 
@@ -3850,7 +3862,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1212]
+    (const void *)&gInstructions[1216]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = 
@@ -3867,7 +3879,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1213]
+    (const void *)&gInstructions[1217]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = 
@@ -3884,7 +3896,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1275]
+    (const void *)&gInstructions[1279]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = 
@@ -3901,7 +3913,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1316]
+    (const void *)&gInstructions[1320]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = 
@@ -3939,43 +3951,43 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[444]
+    (const void *)&gInstructions[446]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1263]
+    (const void *)&gInstructions[1267]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1278]
+    (const void *)&gInstructions[1282]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1761]
+    (const void *)&gInstructions[1765]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1762]
+    (const void *)&gInstructions[1766]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1773]
+    (const void *)&gInstructions[1777]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1774]
+    (const void *)&gInstructions[1778]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = 
@@ -3992,19 +4004,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1772]
+    (const void *)&gInstructions[1776]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1879]
+    (const void *)&gInstructions[1883]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1880]
+    (const void *)&gInstructions[1884]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = 
@@ -4031,7 +4043,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1135]
+    (const void *)&gInstructions[1139]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = 
@@ -4048,7 +4060,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1192]
+    (const void *)&gInstructions[1196]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = 
@@ -4065,19 +4077,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1215]
+    (const void *)&gInstructions[1219]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1231]
+    (const void *)&gInstructions[1235]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2583]
+    (const void *)&gInstructions[2587]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = 
@@ -4094,13 +4106,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1292]
+    (const void *)&gInstructions[1296]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2525]
+    (const void *)&gInstructions[2529]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = 
@@ -4117,7 +4129,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1330]
+    (const void *)&gInstructions[1334]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = 
@@ -4134,7 +4146,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1345]
+    (const void *)&gInstructions[1349]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = 
@@ -4151,7 +4163,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2565]
+    (const void *)&gInstructions[2569]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = 
@@ -4189,19 +4201,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[445]
+    (const void *)&gInstructions[447]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1151]
+    (const void *)&gInstructions[1155]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1152]
+    (const void *)&gInstructions[1156]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = 
@@ -4218,13 +4230,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[605]
+    (const void *)&gInstructions[609]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[612]
+    (const void *)&gInstructions[616]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = 
@@ -4241,7 +4253,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[730]
+    (const void *)&gInstructions[734]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = 
@@ -4258,19 +4270,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1037]
+    (const void *)&gInstructions[1041]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1114]
+    (const void *)&gInstructions[1118]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1336]
+    (const void *)&gInstructions[1340]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = 
@@ -4287,19 +4299,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1137]
+    (const void *)&gInstructions[1141]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1146]
+    (const void *)&gInstructions[1150]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1310]
+    (const void *)&gInstructions[1314]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = 
@@ -4337,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1760]
+    (const void *)&gInstructions[1764]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = 
@@ -4354,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2550]
+    (const void *)&gInstructions[2554]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = 
@@ -4371,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2551]
+    (const void *)&gInstructions[2555]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = 
@@ -4388,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2578]
+    (const void *)&gInstructions[2582]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = 
@@ -4405,7 +4417,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2584]
+    (const void *)&gInstructions[2588]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = 
@@ -4454,7 +4466,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[874]
+    (const void *)&gInstructions[878]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = 
@@ -4471,25 +4483,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1758]
+    (const void *)&gInstructions[1762]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1771]
+    (const void *)&gInstructions[1775]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1878]
+    (const void *)&gInstructions[1882]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1890]
+    (const void *)&gInstructions[1894]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = 
@@ -4510,13 +4522,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[579]
+    (const void *)&gInstructions[583]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1269]
+    (const void *)&gInstructions[1273]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = 
@@ -4537,31 +4549,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[443]
+    (const void *)&gInstructions[445]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[574]
+    (const void *)&gInstructions[576]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[576]
+    (const void *)&gInstructions[578]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[579]
+    (const void *)&gInstructions[583]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1175]
+    (const void *)&gInstructions[1179]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = 
@@ -4578,19 +4590,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1234]
+    (const void *)&gInstructions[1238]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1262]
+    (const void *)&gInstructions[1266]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1268]
+    (const void *)&gInstructions[1272]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = 
@@ -4626,19 +4638,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_NP_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[759]
+    (const void *)&gInstructions[763]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[760]
+    (const void *)&gInstructions[764]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[761]
+    (const void *)&gInstructions[765]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = 
@@ -4655,43 +4667,43 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[763]
+    (const void *)&gInstructions[767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[764]
+    (const void *)&gInstructions[768]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[765]
+    (const void *)&gInstructions[769]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[766]
+    (const void *)&gInstructions[770]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[767]
+    (const void *)&gInstructions[771]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[768]
+    (const void *)&gInstructions[772]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[769]
+    (const void *)&gInstructions[773]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = 
@@ -4712,49 +4724,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[762]
+    (const void *)&gInstructions[766]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[763]
+    (const void *)&gInstructions[767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[764]
+    (const void *)&gInstructions[768]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[765]
+    (const void *)&gInstructions[769]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[766]
+    (const void *)&gInstructions[770]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[767]
+    (const void *)&gInstructions[771]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[768]
+    (const void *)&gInstructions[772]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[769]
+    (const void *)&gInstructions[773]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_reg_modrmreg = 
@@ -4784,7 +4796,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_cldm_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[752]
+    (const void *)&gInstructions[756]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = 
@@ -4836,13 +4848,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2574]
+    (const void *)&gInstructions[2578]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2575]
+    (const void *)&gInstructions[2579]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = 
@@ -4872,13 +4884,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[387]
+    (const void *)&gInstructions[389]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[388]
+    (const void *)&gInstructions[390]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = 
@@ -4908,13 +4920,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[389]
+    (const void *)&gInstructions[391]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[390]
+    (const void *)&gInstructions[392]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = 
@@ -4944,7 +4956,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[566]
+    (const void *)&gInstructions[568]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = 
@@ -4961,19 +4973,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1077]
+    (const void *)&gInstructions[1081]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2570]
+    (const void *)&gInstructions[2574]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2571]
+    (const void *)&gInstructions[2575]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = 
@@ -5003,7 +5015,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1280]
+    (const void *)&gInstructions[1284]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = 
@@ -5020,13 +5032,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2566]
+    (const void *)&gInstructions[2570]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2567]
+    (const void *)&gInstructions[2571]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = 
@@ -5071,13 +5083,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[425]
+    (const void *)&gInstructions[427]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[426]
+    (const void *)&gInstructions[428]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = 
@@ -5096,7 +5108,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[572]
+    (const void *)&gInstructions[574]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = 
@@ -5113,25 +5125,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[606]
+    (const void *)&gInstructions[610]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1337]
+    (const void *)&gInstructions[1341]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1346]
+    (const void *)&gInstructions[1350]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1347]
+    (const void *)&gInstructions[1351]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = 
@@ -5148,7 +5160,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1077]
+    (const void *)&gInstructions[1081]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = 
@@ -5165,7 +5177,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1131]
+    (const void *)&gInstructions[1135]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = 
@@ -5195,7 +5207,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1132]
+    (const void *)&gInstructions[1136]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = 
@@ -5225,7 +5237,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1233]
+    (const void *)&gInstructions[1237]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = 
@@ -5242,7 +5254,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2522]
+    (const void *)&gInstructions[2526]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = 
@@ -5272,7 +5284,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2523]
+    (const void *)&gInstructions[2527]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = 
@@ -5500,19 +5512,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1759]
+    (const void *)&gInstructions[1763]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1875]
+    (const void *)&gInstructions[1879]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1891]
+    (const void *)&gInstructions[1895]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = 
@@ -5529,7 +5541,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1876]
+    (const void *)&gInstructions[1880]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = 
@@ -5546,13 +5558,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2568]
+    (const void *)&gInstructions[2572]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2569]
+    (const void *)&gInstructions[2573]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = 
@@ -5582,13 +5594,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2572]
+    (const void *)&gInstructions[2576]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2573]
+    (const void *)&gInstructions[2577]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = 
@@ -5618,13 +5630,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2576]
+    (const void *)&gInstructions[2580]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2577]
+    (const void *)&gInstructions[2581]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = 
@@ -5669,19 +5681,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1134]
+    (const void *)&gInstructions[1138]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1140]
+    (const void *)&gInstructions[1144]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1141]
+    (const void *)&gInstructions[1145]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = 
@@ -5698,19 +5710,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1138]
+    (const void *)&gInstructions[1142]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1139]
+    (const void *)&gInstructions[1143]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1214]
+    (const void *)&gInstructions[1218]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = 
@@ -6054,7 +6066,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[782]
+    (const void *)&gInstructions[786]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = 
@@ -6079,7 +6091,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[781]
+    (const void *)&gInstructions[785]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = 
@@ -6098,37 +6110,37 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[779]
+    (const void *)&gInstructions[783]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[780]
+    (const void *)&gInstructions[784]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[783]
+    (const void *)&gInstructions[787]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[784]
+    (const void *)&gInstructions[788]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[785]
+    (const void *)&gInstructions[789]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[786]
+    (const void *)&gInstructions[790]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = 
@@ -6149,25 +6161,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[771]
+    (const void *)&gInstructions[775]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[772]
+    (const void *)&gInstructions[776]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[773]
+    (const void *)&gInstructions[777]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1144]
+    (const void *)&gInstructions[1148]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = 
@@ -6186,7 +6198,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1143]
+    (const void *)&gInstructions[1147]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = 
@@ -6205,31 +6217,31 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[774]
+    (const void *)&gInstructions[778]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[775]
+    (const void *)&gInstructions[779]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[776]
+    (const void *)&gInstructions[780]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[777]
+    (const void *)&gInstructions[781]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[778]
+    (const void *)&gInstructions[782]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = 
@@ -6250,7 +6262,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[770]
+    (const void *)&gInstructions[774]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = 
@@ -6265,7 +6277,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[754]
+    (const void *)&gInstructions[758]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = 
@@ -6282,7 +6294,7 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[240]
+    (const void *)&gInstructions[242]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = 
@@ -6303,13 +6315,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[433]
+    (const void *)&gInstructions[435]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1877]
+    (const void *)&gInstructions[1881]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = 
@@ -6326,7 +6338,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1307]
+    (const void *)&gInstructions[1311]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = 
@@ -6354,19 +6366,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[241]
+    (const void *)&gInstructions[243]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[434]
+    (const void *)&gInstructions[436]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1889]
+    (const void *)&gInstructions[1893]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = 
@@ -6383,7 +6395,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1889]
+    (const void *)&gInstructions[1893]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = 
@@ -6409,7 +6421,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1170]
+    (const void *)&gInstructions[1174]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = 
@@ -6437,13 +6449,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[284]
+    (const void *)&gInstructions[286]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[394]
+    (const void *)&gInstructions[396]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = 
@@ -6460,7 +6472,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2526]
+    (const void *)&gInstructions[2530]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = 
@@ -6479,13 +6491,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[398]
+    (const void *)&gInstructions[400]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[399]
+    (const void *)&gInstructions[401]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = 
@@ -6502,7 +6514,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1309]
+    (const void *)&gInstructions[1313]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = 
@@ -6530,13 +6542,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[402]
+    (const void *)&gInstructions[404]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[403]
+    (const void *)&gInstructions[405]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = 
@@ -6553,7 +6565,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1176]
+    (const void *)&gInstructions[1180]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = 
@@ -6581,79 +6593,96 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[406]
+    (const void *)&gInstructions[408]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[441]
+    (const void *)&gInstructions[443]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[451]
+    (const void *)&gInstructions[453]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[453]
+    (const void *)&gInstructions[455]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[457]
+    (const void *)&gInstructions[459]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[459]
+    (const void *)&gInstructions[461]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[464]
+    (const void *)&gInstructions[466]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_F2_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[579]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_00_mem_06_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_00_mem_06_NP_leaf,
+        /* 01 */ NULL,
+        /* 02 */ NULL,
+        /* 03 */ (const void *)&gRootTable_root_0f_00_mem_06_F2_leaf,
+    }
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[577]
+    (const void *)&gInstructions[581]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[595]
+    (const void *)&gInstructions[599]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1264]
+    (const void *)&gInstructions[1268]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1289]
+    (const void *)&gInstructions[1293]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1503]
+    (const void *)&gInstructions[1507]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1504]
+    (const void *)&gInstructions[1508]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = 
@@ -6666,51 +6695,68 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
         /* 03 */ (const void *)&gRootTable_root_0f_00_mem_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_0f_00_mem_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_0f_00_mem_05_leaf,
-        /* 06 */ (const void *)&gRootTable_root_0f_00_mem_06_leaf,
+        /* 06 */ (const void *)&gRootTable_root_0f_00_mem_06_mprefix,
         /* 07 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[464]
+    (const void *)&gInstructions[466]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_F2_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[580]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_00_reg_06_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_00_reg_06_NP_leaf,
+        /* 01 */ NULL,
+        /* 02 */ NULL,
+        /* 03 */ (const void *)&gRootTable_root_0f_00_reg_06_F2_leaf,
+    }
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[577]
+    (const void *)&gInstructions[581]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[595]
+    (const void *)&gInstructions[599]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1265]
+    (const void *)&gInstructions[1269]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1290]
+    (const void *)&gInstructions[1294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1503]
+    (const void *)&gInstructions[1507]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1504]
+    (const void *)&gInstructions[1508]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = 
@@ -6723,7 +6769,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg =
         /* 03 */ (const void *)&gRootTable_root_0f_00_reg_03_leaf,
         /* 04 */ (const void *)&gRootTable_root_0f_00_reg_04_leaf,
         /* 05 */ (const void *)&gRootTable_root_0f_00_reg_05_leaf,
-        /* 06 */ (const void *)&gRootTable_root_0f_00_reg_06_leaf,
+        /* 06 */ (const void *)&gRootTable_root_0f_00_reg_06_mprefix,
         /* 07 */ NULL,
     }
 };
@@ -6740,13 +6786,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[465]
+    (const void *)&gInstructions[467]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[992]
+    (const void *)&gInstructions[996]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = 
@@ -6765,85 +6811,85 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[468]
+    (const void *)&gInstructions[470]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[470]
+    (const void *)&gInstructions[472]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[472]
+    (const void *)&gInstructions[474]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[474]
+    (const void *)&gInstructions[476]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[476]
+    (const void *)&gInstructions[478]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[478]
+    (const void *)&gInstructions[480]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[480]
+    (const void *)&gInstructions[482]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[482]
+    (const void *)&gInstructions[484]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[484]
+    (const void *)&gInstructions[486]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[486]
+    (const void *)&gInstructions[488]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[489]
+    (const void *)&gInstructions[491]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[491]
+    (const void *)&gInstructions[493]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[563]
+    (const void *)&gInstructions[565]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[564]
+    (const void *)&gInstructions[566]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = 
@@ -6858,7 +6904,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[565]
+    (const void *)&gInstructions[567]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = 
@@ -6884,7 +6930,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[573]
+    (const void *)&gInstructions[575]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = 
@@ -6899,7 +6945,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[575]
+    (const void *)&gInstructions[577]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = 
@@ -6914,13 +6960,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[592]
+    (const void *)&gInstructions[596]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[593]
+    (const void *)&gInstructions[597]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = 
@@ -6935,7 +6981,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[594]
+    (const void *)&gInstructions[598]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = 
@@ -6950,13 +6996,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[599]
+    (const void *)&gInstructions[603]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[600]
+    (const void *)&gInstructions[604]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = 
@@ -6982,25 +7028,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[601]
+    (const void *)&gInstructions[605]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[602]
+    (const void *)&gInstructions[606]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[603]
+    (const void *)&gInstructions[607]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[604]
+    (const void *)&gInstructions[608]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = 
@@ -7017,25 +7063,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[607]
+    (const void *)&gInstructions[611]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[608]
+    (const void *)&gInstructions[612]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[609]
+    (const void *)&gInstructions[613]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[610]
+    (const void *)&gInstructions[614]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = 
@@ -7052,7 +7098,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[613]
+    (const void *)&gInstructions[617]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = 
@@ -7084,7 +7130,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2579]
+    (const void *)&gInstructions[2583]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = 
@@ -7116,7 +7162,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2580]
+    (const void *)&gInstructions[2584]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = 
@@ -7172,49 +7218,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[614]
+    (const void *)&gInstructions[618]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[615]
+    (const void *)&gInstructions[619]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[616]
+    (const void *)&gInstructions[620]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[617]
+    (const void *)&gInstructions[621]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[618]
+    (const void *)&gInstructions[622]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[619]
+    (const void *)&gInstructions[623]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[650]
+    (const void *)&gInstructions[654]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[652]
+    (const void *)&gInstructions[656]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = 
@@ -7231,13 +7277,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[651]
+    (const void *)&gInstructions[655]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[653]
+    (const void *)&gInstructions[657]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = 
@@ -7254,13 +7300,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[658]
+    (const void *)&gInstructions[662]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[689]
+    (const void *)&gInstructions[693]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = 
@@ -7279,13 +7325,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[659]
+    (const void *)&gInstructions[663]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[690]
+    (const void *)&gInstructions[694]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = 
@@ -7315,13 +7361,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[660]
+    (const void *)&gInstructions[664]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[692]
+    (const void *)&gInstructions[696]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = 
@@ -7340,13 +7386,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[661]
+    (const void *)&gInstructions[665]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[693]
+    (const void *)&gInstructions[697]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = 
@@ -7365,7 +7411,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[694]
+    (const void *)&gInstructions[698]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = 
@@ -7382,7 +7428,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1267]
+    (const void *)&gInstructions[1271]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = 
@@ -7401,25 +7447,25 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[662]
+    (const void *)&gInstructions[666]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[670]
+    (const void *)&gInstructions[674]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[676]
+    (const void *)&gInstructions[680]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[705]
+    (const void *)&gInstructions[709]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = 
@@ -7436,19 +7482,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[662]
+    (const void *)&gInstructions[666]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[670]
+    (const void *)&gInstructions[674]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[705]
+    (const void *)&gInstructions[709]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = 
@@ -7474,19 +7520,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[665]
+    (const void *)&gInstructions[669]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[696]
+    (const void *)&gInstructions[700]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[697]
+    (const void *)&gInstructions[701]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = 
@@ -7503,7 +7549,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[696]
+    (const void *)&gInstructions[700]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = 
@@ -7529,19 +7575,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[666]
+    (const void *)&gInstructions[670]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[668]
+    (const void *)&gInstructions[672]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[691]
+    (const void *)&gInstructions[695]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = 
@@ -7558,19 +7604,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[667]
+    (const void *)&gInstructions[671]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[669]
+    (const void *)&gInstructions[673]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[695]
+    (const void *)&gInstructions[699]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = 
@@ -7587,19 +7633,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[671]
+    (const void *)&gInstructions[675]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[673]
+    (const void *)&gInstructions[677]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[704]
+    (const void *)&gInstructions[708]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = 
@@ -7616,13 +7662,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[675]
+    (const void *)&gInstructions[679]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[704]
+    (const void *)&gInstructions[708]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = 
@@ -7648,13 +7694,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[672]
+    (const void *)&gInstructions[676]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[674]
+    (const void *)&gInstructions[678]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = 
@@ -7680,13 +7726,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[677]
+    (const void *)&gInstructions[681]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[678]
+    (const void *)&gInstructions[682]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = 
@@ -7712,13 +7758,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[679]
+    (const void *)&gInstructions[683]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[680]
+    (const void *)&gInstructions[684]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = 
@@ -7744,13 +7790,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[681]
+    (const void *)&gInstructions[685]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[686]
+    (const void *)&gInstructions[690]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = 
@@ -7776,7 +7822,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[683]
+    (const void *)&gInstructions[687]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = 
@@ -7802,25 +7848,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[684]
+    (const void *)&gInstructions[688]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[685]
+    (const void *)&gInstructions[689]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[687]
+    (const void *)&gInstructions[691]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[688]
+    (const void *)&gInstructions[692]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = 
@@ -7846,25 +7892,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[700]
+    (const void *)&gInstructions[704]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[708]
+    (const void *)&gInstructions[712]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[715]
+    (const void *)&gInstructions[719]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[717]
+    (const void *)&gInstructions[721]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = 
@@ -7881,25 +7927,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[701]
+    (const void *)&gInstructions[705]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[709]
+    (const void *)&gInstructions[713]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[716]
+    (const void *)&gInstructions[720]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[718]
+    (const void *)&gInstructions[722]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = 
@@ -7916,49 +7962,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[712]
+    (const void *)&gInstructions[716]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[713]
+    (const void *)&gInstructions[717]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[719]
+    (const void *)&gInstructions[723]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[720]
+    (const void *)&gInstructions[724]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[724]
+    (const void *)&gInstructions[728]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[725]
+    (const void *)&gInstructions[729]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[726]
+    (const void *)&gInstructions[730]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[727]
+    (const void *)&gInstructions[731]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = 
@@ -7975,49 +8021,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[733]
+    (const void *)&gInstructions[737]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[734]
+    (const void *)&gInstructions[738]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[735]
+    (const void *)&gInstructions[739]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[736]
+    (const void *)&gInstructions[740]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[737]
+    (const void *)&gInstructions[741]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[738]
+    (const void *)&gInstructions[742]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[739]
+    (const void *)&gInstructions[743]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[740]
+    (const void *)&gInstructions[744]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = 
@@ -8038,49 +8084,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[998]
+    (const void *)&gInstructions[1002]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[999]
+    (const void *)&gInstructions[1003]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1000]
+    (const void *)&gInstructions[1004]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1001]
+    (const void *)&gInstructions[1005]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1002]
+    (const void *)&gInstructions[1006]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1003]
+    (const void *)&gInstructions[1007]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1008]
+    (const void *)&gInstructions[1012]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1009]
+    (const void *)&gInstructions[1013]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = 
@@ -8110,49 +8156,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[741]
+    (const void *)&gInstructions[745]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[742]
+    (const void *)&gInstructions[746]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[743]
+    (const void *)&gInstructions[747]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[744]
+    (const void *)&gInstructions[748]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[745]
+    (const void *)&gInstructions[749]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[746]
+    (const void *)&gInstructions[750]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[747]
+    (const void *)&gInstructions[751]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[748]
+    (const void *)&gInstructions[752]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = 
@@ -8173,49 +8219,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[745]
+    (const void *)&gInstructions[749]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[746]
+    (const void *)&gInstructions[750]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[747]
+    (const void *)&gInstructions[751]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[748]
+    (const void *)&gInstructions[752]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1004]
+    (const void *)&gInstructions[1008]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1005]
+    (const void *)&gInstructions[1009]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1006]
+    (const void *)&gInstructions[1010]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1007]
+    (const void *)&gInstructions[1011]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = 
@@ -8245,31 +8291,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[749]
+    (const void *)&gInstructions[753]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[753]
+    (const void *)&gInstructions[757]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[755]
+    (const void *)&gInstructions[759]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[800]
+    (const void *)&gInstructions[804]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[801]
+    (const void *)&gInstructions[805]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = 
@@ -8286,13 +8332,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[818]
+    (const void *)&gInstructions[822]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[819]
+    (const void *)&gInstructions[823]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = 
@@ -8309,13 +8355,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[820]
+    (const void *)&gInstructions[824]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[821]
+    (const void *)&gInstructions[825]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = 
@@ -8332,13 +8378,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[823]
+    (const void *)&gInstructions[827]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[824]
+    (const void *)&gInstructions[828]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = 
@@ -8355,13 +8401,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[825]
+    (const void *)&gInstructions[829]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[826]
+    (const void *)&gInstructions[830]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = 
@@ -8378,13 +8424,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[827]
+    (const void *)&gInstructions[831]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[828]
+    (const void *)&gInstructions[832]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = 
@@ -8401,13 +8447,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[829]
+    (const void *)&gInstructions[833]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[830]
+    (const void *)&gInstructions[834]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = 
@@ -8424,13 +8470,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[831]
+    (const void *)&gInstructions[835]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[832]
+    (const void *)&gInstructions[836]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = 
@@ -8447,13 +8493,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[833]
+    (const void *)&gInstructions[837]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[834]
+    (const void *)&gInstructions[838]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = 
@@ -8470,13 +8516,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[835]
+    (const void *)&gInstructions[839]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[836]
+    (const void *)&gInstructions[840]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = 
@@ -8493,13 +8539,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[837]
+    (const void *)&gInstructions[841]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[838]
+    (const void *)&gInstructions[842]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = 
@@ -8516,13 +8562,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[839]
+    (const void *)&gInstructions[843]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[840]
+    (const void *)&gInstructions[844]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = 
@@ -8539,13 +8585,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[843]
+    (const void *)&gInstructions[847]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[844]
+    (const void *)&gInstructions[848]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = 
@@ -8562,13 +8608,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[845]
+    (const void *)&gInstructions[849]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[846]
+    (const void *)&gInstructions[850]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = 
@@ -8585,13 +8631,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[848]
+    (const void *)&gInstructions[852]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[849]
+    (const void *)&gInstructions[853]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = 
@@ -8608,157 +8654,157 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[850]
+    (const void *)&gInstructions[854]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[885]
+    (const void *)&gInstructions[889]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[886]
+    (const void *)&gInstructions[890]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[887]
+    (const void *)&gInstructions[891]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[888]
+    (const void *)&gInstructions[892]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[889]
+    (const void *)&gInstructions[893]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[890]
+    (const void *)&gInstructions[894]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[891]
+    (const void *)&gInstructions[895]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[892]
+    (const void *)&gInstructions[896]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[893]
+    (const void *)&gInstructions[897]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[894]
+    (const void *)&gInstructions[898]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[895]
+    (const void *)&gInstructions[899]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[896]
+    (const void *)&gInstructions[900]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[897]
+    (const void *)&gInstructions[901]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[898]
+    (const void *)&gInstructions[902]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[899]
+    (const void *)&gInstructions[903]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[900]
+    (const void *)&gInstructions[904]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[901]
+    (const void *)&gInstructions[905]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[902]
+    (const void *)&gInstructions[906]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[903]
+    (const void *)&gInstructions[907]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[904]
+    (const void *)&gInstructions[908]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[905]
+    (const void *)&gInstructions[909]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[919]
+    (const void *)&gInstructions[923]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[920]
+    (const void *)&gInstructions[924]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[966]
+    (const void *)&gInstructions[970]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1075]
+    (const void *)&gInstructions[1079]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = 
@@ -9027,13 +9073,13 @@ const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[851]
+    (const void *)&gInstructions[855]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[852]
+    (const void *)&gInstructions[856]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = 
@@ -9050,13 +9096,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[856]
+    (const void *)&gInstructions[860]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[857]
+    (const void *)&gInstructions[861]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = 
@@ -9073,13 +9119,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[858]
+    (const void *)&gInstructions[862]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[859]
+    (const void *)&gInstructions[863]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = 
@@ -9096,13 +9142,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[861]
+    (const void *)&gInstructions[865]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[862]
+    (const void *)&gInstructions[866]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = 
@@ -9119,13 +9165,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[865]
+    (const void *)&gInstructions[869]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[866]
+    (const void *)&gInstructions[870]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = 
@@ -9142,13 +9188,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[867]
+    (const void *)&gInstructions[871]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[868]
+    (const void *)&gInstructions[872]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = 
@@ -9165,13 +9211,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[870]
+    (const void *)&gInstructions[874]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[871]
+    (const void *)&gInstructions[875]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = 
@@ -9188,13 +9234,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[881]
+    (const void *)&gInstructions[885]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[882]
+    (const void *)&gInstructions[886]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = 
@@ -9220,13 +9266,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[925]
+    (const void *)&gInstructions[929]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[927]
+    (const void *)&gInstructions[931]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = 
@@ -9243,13 +9289,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[926]
+    (const void *)&gInstructions[930]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[928]
+    (const void *)&gInstructions[932]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = 
@@ -9275,13 +9321,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[931]
+    (const void *)&gInstructions[935]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[932]
+    (const void *)&gInstructions[936]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = 
@@ -9298,13 +9344,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[935]
+    (const void *)&gInstructions[939]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[936]
+    (const void *)&gInstructions[940]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = 
@@ -9321,13 +9367,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[937]
+    (const void *)&gInstructions[941]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[938]
+    (const void *)&gInstructions[942]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = 
@@ -9344,13 +9390,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[943]
+    (const void *)&gInstructions[947]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[944]
+    (const void *)&gInstructions[948]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = 
@@ -9367,13 +9413,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[945]
+    (const void *)&gInstructions[949]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[946]
+    (const void *)&gInstructions[950]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = 
@@ -9390,13 +9436,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[949]
+    (const void *)&gInstructions[953]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[950]
+    (const void *)&gInstructions[954]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = 
@@ -9422,13 +9468,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[967]
+    (const void *)&gInstructions[971]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[968]
+    (const void *)&gInstructions[972]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = 
@@ -9445,13 +9491,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[969]
+    (const void *)&gInstructions[973]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[970]
+    (const void *)&gInstructions[974]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = 
@@ -9468,13 +9514,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[972]
+    (const void *)&gInstructions[976]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[973]
+    (const void *)&gInstructions[977]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = 
@@ -9491,13 +9537,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[974]
+    (const void *)&gInstructions[978]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[975]
+    (const void *)&gInstructions[979]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = 
@@ -9514,25 +9560,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[976]
+    (const void *)&gInstructions[980]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[977]
+    (const void *)&gInstructions[981]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[996]
+    (const void *)&gInstructions[1000]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[997]
+    (const void *)&gInstructions[1001]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = 
@@ -9549,13 +9595,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1010]
+    (const void *)&gInstructions[1014]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1011]
+    (const void *)&gInstructions[1015]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = 
@@ -9572,25 +9618,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1014]
+    (const void *)&gInstructions[1018]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1015]
+    (const void *)&gInstructions[1019]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1016]
+    (const void *)&gInstructions[1020]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1017]
+    (const void *)&gInstructions[1021]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = 
@@ -9607,13 +9653,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1024]
+    (const void *)&gInstructions[1028]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1025]
+    (const void *)&gInstructions[1029]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = 
@@ -9630,13 +9676,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1038]
+    (const void *)&gInstructions[1042]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1039]
+    (const void *)&gInstructions[1043]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = 
@@ -9653,13 +9699,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1046]
+    (const void *)&gInstructions[1050]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1047]
+    (const void *)&gInstructions[1051]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = 
@@ -9700,13 +9746,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1026]
+    (const void *)&gInstructions[1030]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1027]
+    (const void *)&gInstructions[1031]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = 
@@ -9723,7 +9769,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1028]
+    (const void *)&gInstructions[1032]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = 
@@ -9740,13 +9786,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1029]
+    (const void *)&gInstructions[1033]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1030]
+    (const void *)&gInstructions[1034]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = 
@@ -9763,7 +9809,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1050]
+    (const void *)&gInstructions[1054]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = 
@@ -9780,13 +9826,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1051]
+    (const void *)&gInstructions[1055]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1052]
+    (const void *)&gInstructions[1056]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = 
@@ -9827,13 +9873,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1031]
+    (const void *)&gInstructions[1035]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1032]
+    (const void *)&gInstructions[1036]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = 
@@ -9850,13 +9896,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1033]
+    (const void *)&gInstructions[1037]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1034]
+    (const void *)&gInstructions[1038]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = 
@@ -9873,13 +9919,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1042]
+    (const void *)&gInstructions[1046]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1043]
+    (const void *)&gInstructions[1047]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = 
@@ -9896,13 +9942,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1055]
+    (const void *)&gInstructions[1059]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1056]
+    (const void *)&gInstructions[1060]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = 
@@ -9943,13 +9989,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1035]
+    (const void *)&gInstructions[1039]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1036]
+    (const void *)&gInstructions[1040]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = 
@@ -9966,13 +10012,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1040]
+    (const void *)&gInstructions[1044]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1041]
+    (const void *)&gInstructions[1045]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = 
@@ -9989,13 +10035,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1044]
+    (const void *)&gInstructions[1048]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1045]
+    (const void *)&gInstructions[1049]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = 
@@ -10012,13 +10058,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1048]
+    (const void *)&gInstructions[1052]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1049]
+    (const void *)&gInstructions[1053]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = 
@@ -10035,13 +10081,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1053]
+    (const void *)&gInstructions[1057]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1054]
+    (const void *)&gInstructions[1058]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = 
@@ -10058,13 +10104,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1057]
+    (const void *)&gInstructions[1061]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1058]
+    (const void *)&gInstructions[1062]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = 
@@ -10081,13 +10127,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1059]
+    (const void *)&gInstructions[1063]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1060]
+    (const void *)&gInstructions[1064]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = 
@@ -10104,13 +10150,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1061]
+    (const void *)&gInstructions[1065]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1062]
+    (const void *)&gInstructions[1066]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = 
@@ -10127,13 +10173,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1063]
+    (const void *)&gInstructions[1067]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1064]
+    (const void *)&gInstructions[1068]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = 
@@ -10150,13 +10196,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1065]
+    (const void *)&gInstructions[1069]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1066]
+    (const void *)&gInstructions[1070]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = 
@@ -10173,13 +10219,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1067]
+    (const void *)&gInstructions[1071]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1068]
+    (const void *)&gInstructions[1072]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = 
@@ -10196,13 +10242,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1069]
+    (const void *)&gInstructions[1073]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1070]
+    (const void *)&gInstructions[1074]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = 
@@ -10219,13 +10265,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1071]
+    (const void *)&gInstructions[1075]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1072]
+    (const void *)&gInstructions[1076]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = 
@@ -10242,13 +10288,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1073]
+    (const void *)&gInstructions[1077]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1074]
+    (const void *)&gInstructions[1078]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = 
@@ -10265,13 +10311,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1078]
+    (const void *)&gInstructions[1082]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1079]
+    (const void *)&gInstructions[1083]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = 
@@ -10288,13 +10334,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1080]
+    (const void *)&gInstructions[1084]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1081]
+    (const void *)&gInstructions[1085]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = 
@@ -10311,7 +10357,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1082]
+    (const void *)&gInstructions[1086]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = 
@@ -10328,13 +10374,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1083]
+    (const void *)&gInstructions[1087]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1084]
+    (const void *)&gInstructions[1088]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = 
@@ -10351,13 +10397,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1085]
+    (const void *)&gInstructions[1089]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1086]
+    (const void *)&gInstructions[1090]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = 
@@ -10374,13 +10420,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1087]
+    (const void *)&gInstructions[1091]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1088]
+    (const void *)&gInstructions[1092]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = 
@@ -10397,7 +10443,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1089]
+    (const void *)&gInstructions[1093]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = 
@@ -10414,13 +10460,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1090]
+    (const void *)&gInstructions[1094]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1091]
+    (const void *)&gInstructions[1095]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = 
@@ -10437,25 +10483,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1092]
+    (const void *)&gInstructions[1096]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1093]
+    (const void *)&gInstructions[1097]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1115]
+    (const void *)&gInstructions[1119]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1116]
+    (const void *)&gInstructions[1120]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = 
@@ -10472,13 +10518,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1123]
+    (const void *)&gInstructions[1127]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1124]
+    (const void *)&gInstructions[1128]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = 
@@ -10495,19 +10541,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1133]
+    (const void *)&gInstructions[1137]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1136]
+    (const void *)&gInstructions[1140]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1142]
+    (const void *)&gInstructions[1146]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = 
@@ -10526,13 +10572,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1145]
+    (const void *)&gInstructions[1149]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1171]
+    (const void *)&gInstructions[1175]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = 
@@ -10560,19 +10606,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1172]
+    (const void *)&gInstructions[1176]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1173]
+    (const void *)&gInstructions[1177]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1174]
+    (const void *)&gInstructions[1178]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = 
@@ -10589,133 +10635,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1216]
+    (const void *)&gInstructions[1220]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1217]
+    (const void *)&gInstructions[1221]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1218]
+    (const void *)&gInstructions[1222]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1219]
+    (const void *)&gInstructions[1223]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1220]
+    (const void *)&gInstructions[1224]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1221]
+    (const void *)&gInstructions[1225]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1222]
+    (const void *)&gInstructions[1226]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1223]
+    (const void *)&gInstructions[1227]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1224]
+    (const void *)&gInstructions[1228]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1225]
+    (const void *)&gInstructions[1229]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1226]
+    (const void *)&gInstructions[1230]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1227]
+    (const void *)&gInstructions[1231]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1228]
+    (const void *)&gInstructions[1232]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1229]
+    (const void *)&gInstructions[1233]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1230]
+    (const void *)&gInstructions[1234]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1232]
+    (const void *)&gInstructions[1236]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1248]
+    (const void *)&gInstructions[1252]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1249]
+    (const void *)&gInstructions[1253]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1257]
+    (const void *)&gInstructions[1261]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1258]
+    (const void *)&gInstructions[1262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1260]
+    (const void *)&gInstructions[1264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1261]
+    (const void *)&gInstructions[1265]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = 
@@ -10732,25 +10778,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1271]
+    (const void *)&gInstructions[1275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1272]
+    (const void *)&gInstructions[1276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1273]
+    (const void *)&gInstructions[1277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1274]
+    (const void *)&gInstructions[1278]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = 
@@ -10767,25 +10813,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1303]
+    (const void *)&gInstructions[1307]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1304]
+    (const void *)&gInstructions[1308]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1305]
+    (const void *)&gInstructions[1309]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1306]
+    (const void *)&gInstructions[1310]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = 
@@ -10802,7 +10848,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1308]
+    (const void *)&gInstructions[1312]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = 
@@ -10830,37 +10876,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1311]
+    (const void *)&gInstructions[1315]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1312]
+    (const void *)&gInstructions[1316]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1313]
+    (const void *)&gInstructions[1317]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1314]
+    (const void *)&gInstructions[1318]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1340]
+    (const void *)&gInstructions[1344]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1341]
+    (const void *)&gInstructions[1345]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = 
@@ -10877,31 +10923,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1342]
+    (const void *)&gInstructions[1346]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1343]
+    (const void *)&gInstructions[1347]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1344]
+    (const void *)&gInstructions[1348]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1348]
+    (const void *)&gInstructions[1352]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1349]
+    (const void *)&gInstructions[1353]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = 
@@ -10918,13 +10964,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1350]
+    (const void *)&gInstructions[1354]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1351]
+    (const void *)&gInstructions[1355]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = 
@@ -10941,13 +10987,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2520]
+    (const void *)&gInstructions[2524]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2521]
+    (const void *)&gInstructions[2525]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = 
@@ -10966,25 +11012,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2524]
+    (const void *)&gInstructions[2528]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2532]
+    (const void *)&gInstructions[2536]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2533]
+    (const void *)&gInstructions[2537]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2545]
+    (const void *)&gInstructions[2549]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = 
@@ -11016,7 +11062,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2546]
+    (const void *)&gInstructions[2550]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = 
@@ -11048,7 +11094,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2547]
+    (const void *)&gInstructions[2551]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = 
@@ -11080,7 +11126,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2548]
+    (const void *)&gInstructions[2552]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = 
@@ -11112,7 +11158,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2549]
+    (const void *)&gInstructions[2553]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = 
@@ -11144,13 +11190,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2581]
+    (const void *)&gInstructions[2585]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2582]
+    (const void *)&gInstructions[2586]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix = 
@@ -11206,13 +11252,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2563]
+    (const void *)&gInstructions[2567]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2564]
+    (const void *)&gInstructions[2568]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = 
@@ -11570,7 +11616,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[714]
+    (const void *)&gInstructions[718]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = 
@@ -11628,25 +11674,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[424]
+    (const void *)&gInstructions[426]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[463]
+    (const void *)&gInstructions[465]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[467]
+    (const void *)&gInstructions[469]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1108]
+    (const void *)&gInstructions[1112]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = 
@@ -11679,19 +11725,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[424]
+    (const void *)&gInstructions[426]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[463]
+    (const void *)&gInstructions[465]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1108]
+    (const void *)&gInstructions[1112]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = 
@@ -12028,7 +12074,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[423]
+    (const void *)&gInstructions[425]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = 
@@ -12055,43 +12101,43 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[404]
+    (const void *)&gInstructions[406]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[409]
+    (const void *)&gInstructions[411]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[722]
+    (const void *)&gInstructions[726]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[731]
+    (const void *)&gInstructions[735]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[788]
+    (const void *)&gInstructions[792]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1326]
+    (const void *)&gInstructions[1330]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1327]
+    (const void *)&gInstructions[1331]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = 
@@ -12118,43 +12164,43 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[405]
+    (const void *)&gInstructions[407]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[410]
+    (const void *)&gInstructions[412]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[723]
+    (const void *)&gInstructions[727]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[732]
+    (const void *)&gInstructions[736]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[789]
+    (const void *)&gInstructions[793]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1328]
+    (const void *)&gInstructions[1332]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1329]
+    (const void *)&gInstructions[1333]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = 
@@ -12181,49 +12227,49 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[242]
+    (const void *)&gInstructions[244]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[273]
+    (const void *)&gInstructions[275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[302]
+    (const void *)&gInstructions[304]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[344]
+    (const void *)&gInstructions[346]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[346]
+    (const void *)&gInstructions[348]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[347]
+    (const void *)&gInstructions[349]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[391]
+    (const void *)&gInstructions[393]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[392]
+    (const void *)&gInstructions[394]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = 
@@ -12244,25 +12290,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[243]
+    (const void *)&gInstructions[245]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[251]
+    (const void *)&gInstructions[253]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[377]
+    (const void *)&gInstructions[379]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[383]
+    (const void *)&gInstructions[385]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = 
@@ -12283,49 +12329,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[272]
+    (const void *)&gInstructions[274]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[345]
+    (const void *)&gInstructions[347]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[349]
+    (const void *)&gInstructions[351]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[351]
+    (const void *)&gInstructions[353]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[352]
+    (const void *)&gInstructions[354]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[353]
+    (const void *)&gInstructions[355]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[354]
+    (const void *)&gInstructions[356]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[393]
+    (const void *)&gInstructions[395]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = 
@@ -12346,49 +12392,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[316]
+    (const void *)&gInstructions[318]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[319]
+    (const void *)&gInstructions[321]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[322]
+    (const void *)&gInstructions[324]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[323]
+    (const void *)&gInstructions[325]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[324]
+    (const void *)&gInstructions[326]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[325]
+    (const void *)&gInstructions[327]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[326]
+    (const void *)&gInstructions[328]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[327]
+    (const void *)&gInstructions[329]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = 
@@ -12409,7 +12455,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[336]
+    (const void *)&gInstructions[338]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = 
@@ -12430,13 +12476,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[365]
+    (const void *)&gInstructions[367]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[384]
+    (const void *)&gInstructions[386]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = 
@@ -12457,43 +12503,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[315]
+    (const void *)&gInstructions[317]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[320]
+    (const void *)&gInstructions[322]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[321]
+    (const void *)&gInstructions[323]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[340]
+    (const void *)&gInstructions[342]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[341]
+    (const void *)&gInstructions[343]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[355]
+    (const void *)&gInstructions[357]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[359]
+    (const void *)&gInstructions[361]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = 
@@ -12523,49 +12569,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[244]
+    (const void *)&gInstructions[246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[260]
+    (const void *)&gInstructions[262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[266]
+    (const void *)&gInstructions[268]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[274]
+    (const void *)&gInstructions[276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[279]
+    (const void *)&gInstructions[281]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[328]
+    (const void *)&gInstructions[330]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[367]
+    (const void *)&gInstructions[369]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[372]
+    (const void *)&gInstructions[374]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = 
@@ -12586,49 +12632,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[245]
+    (const void *)&gInstructions[247]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[261]
+    (const void *)&gInstructions[263]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[267]
+    (const void *)&gInstructions[269]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[275]
+    (const void *)&gInstructions[277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[280]
+    (const void *)&gInstructions[282]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[329]
+    (const void *)&gInstructions[331]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[368]
+    (const void *)&gInstructions[370]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[373]
+    (const void *)&gInstructions[375]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = 
@@ -12658,49 +12704,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[246]
+    (const void *)&gInstructions[248]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[262]
+    (const void *)&gInstructions[264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[268]
+    (const void *)&gInstructions[270]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[276]
+    (const void *)&gInstructions[278]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[281]
+    (const void *)&gInstructions[283]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[330]
+    (const void *)&gInstructions[332]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[369]
+    (const void *)&gInstructions[371]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[374]
+    (const void *)&gInstructions[376]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = 
@@ -12721,49 +12767,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[247]
+    (const void *)&gInstructions[249]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[263]
+    (const void *)&gInstructions[265]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[269]
+    (const void *)&gInstructions[271]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[277]
+    (const void *)&gInstructions[279]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[282]
+    (const void *)&gInstructions[284]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[331]
+    (const void *)&gInstructions[333]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[370]
+    (const void *)&gInstructions[372]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[375]
+    (const void *)&gInstructions[377]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = 
@@ -12793,19 +12839,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[248]
+    (const void *)&gInstructions[250]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[270]
+    (const void *)&gInstructions[272]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[271]
+    (const void *)&gInstructions[273]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = 
@@ -12826,31 +12872,31 @@ const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[278]
+    (const void *)&gInstructions[280]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[283]
+    (const void *)&gInstructions[285]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[332]
+    (const void *)&gInstructions[334]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[371]
+    (const void *)&gInstructions[373]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[376]
+    (const void *)&gInstructions[378]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = 
@@ -12871,49 +12917,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[288]
+    (const void *)&gInstructions[290]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[290]
+    (const void *)&gInstructions[292]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[292]
+    (const void *)&gInstructions[294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[294]
+    (const void *)&gInstructions[296]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[296]
+    (const void *)&gInstructions[298]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[301]
+    (const void *)&gInstructions[303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[312]
+    (const void *)&gInstructions[314]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[314]
+    (const void *)&gInstructions[316]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = 
@@ -12943,49 +12989,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[249]
+    (const void *)&gInstructions[251]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[250]
+    (const void *)&gInstructions[252]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[298]
+    (const void *)&gInstructions[300]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[299]
+    (const void *)&gInstructions[301]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[304]
+    (const void *)&gInstructions[306]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[306]
+    (const void *)&gInstructions[308]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[307]
+    (const void *)&gInstructions[309]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[310]
+    (const void *)&gInstructions[312]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = 
@@ -13006,31 +13052,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[265]
+    (const void *)&gInstructions[267]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[286]
+    (const void *)&gInstructions[288]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[343]
+    (const void *)&gInstructions[345]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[358]
+    (const void *)&gInstructions[360]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[366]
+    (const void *)&gInstructions[368]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = 
@@ -13051,7 +13097,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[348]
+    (const void *)&gInstructions[350]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = 
@@ -13072,25 +13118,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[363]
+    (const void *)&gInstructions[365]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[364]
+    (const void *)&gInstructions[366]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[380]
+    (const void *)&gInstructions[382]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[386]
+    (const void *)&gInstructions[388]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = 
@@ -13120,31 +13166,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[252]
+    (const void *)&gInstructions[254]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[253]
+    (const void *)&gInstructions[255]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[254]
+    (const void *)&gInstructions[256]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[259]
+    (const void *)&gInstructions[261]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[382]
+    (const void *)&gInstructions[384]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = 
@@ -13180,49 +13226,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[287]
+    (const void *)&gInstructions[289]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[289]
+    (const void *)&gInstructions[291]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[291]
+    (const void *)&gInstructions[293]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[293]
+    (const void *)&gInstructions[295]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[295]
+    (const void *)&gInstructions[297]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[300]
+    (const void *)&gInstructions[302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[311]
+    (const void *)&gInstructions[313]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[313]
+    (const void *)&gInstructions[315]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = 
@@ -13252,61 +13298,61 @@ const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[255]
+    (const void *)&gInstructions[257]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[256]
+    (const void *)&gInstructions[258]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[257]
+    (const void *)&gInstructions[259]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[258]
+    (const void *)&gInstructions[260]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[264]
+    (const void *)&gInstructions[266]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[333]
+    (const void *)&gInstructions[335]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[334]
+    (const void *)&gInstructions[336]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[335]
+    (const void *)&gInstructions[337]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[337]
+    (const void *)&gInstructions[339]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[338]
+    (const void *)&gInstructions[340]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = 
@@ -13327,7 +13373,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[379]
+    (const void *)&gInstructions[381]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = 
@@ -13348,37 +13394,37 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[297]
+    (const void *)&gInstructions[299]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[303]
+    (const void *)&gInstructions[305]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[305]
+    (const void *)&gInstructions[307]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[308]
+    (const void *)&gInstructions[310]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[317]
+    (const void *)&gInstructions[319]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[360]
+    (const void *)&gInstructions[362]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = 
@@ -13408,37 +13454,37 @@ const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[285]
+    (const void *)&gInstructions[287]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[357]
+    (const void *)&gInstructions[359]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[362]
+    (const void *)&gInstructions[364]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[378]
+    (const void *)&gInstructions[380]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[381]
+    (const void *)&gInstructions[383]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[385]
+    (const void *)&gInstructions[387]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = 
@@ -13459,43 +13505,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[309]
+    (const void *)&gInstructions[311]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[318]
+    (const void *)&gInstructions[320]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[339]
+    (const void *)&gInstructions[341]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[342]
+    (const void *)&gInstructions[344]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[350]
+    (const void *)&gInstructions[352]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[356]
+    (const void *)&gInstructions[358]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[361]
+    (const void *)&gInstructions[363]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = 
@@ -13525,103 +13571,103 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[400]
+    (const void *)&gInstructions[402]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[407]
+    (const void *)&gInstructions[409]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[408]
+    (const void *)&gInstructions[410]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[411]
+    (const void *)&gInstructions[413]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[412]
+    (const void *)&gInstructions[414]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[413]
+    (const void *)&gInstructions[415]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[414]
+    (const void *)&gInstructions[416]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[415]
+    (const void *)&gInstructions[417]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[416]
+    (const void *)&gInstructions[418]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[417]
+    (const void *)&gInstructions[419]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[418]
+    (const void *)&gInstructions[420]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[419]
+    (const void *)&gInstructions[421]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[420]
+    (const void *)&gInstructions[422]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[421]
+    (const void *)&gInstructions[423]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[422]
+    (const void *)&gInstructions[424]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[427]
+    (const void *)&gInstructions[429]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[428]
+    (const void *)&gInstructions[430]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = 
@@ -13640,13 +13686,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[429]
+    (const void *)&gInstructions[431]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[430]
+    (const void *)&gInstructions[432]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = 
@@ -13665,13 +13711,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[435]
+    (const void *)&gInstructions[437]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[436]
+    (const void *)&gInstructions[438]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = 
@@ -13703,43 +13749,43 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[437]
+    (const void *)&gInstructions[439]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[438]
+    (const void *)&gInstructions[440]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[439]
+    (const void *)&gInstructions[441]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[440]
+    (const void *)&gInstructions[442]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[448]
+    (const void *)&gInstructions[450]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[449]
+    (const void *)&gInstructions[451]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[450]
+    (const void *)&gInstructions[452]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_cf_dsize = 
@@ -13758,31 +13804,31 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[452]
+    (const void *)&gInstructions[454]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[454]
+    (const void *)&gInstructions[456]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[455]
+    (const void *)&gInstructions[457]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[456]
+    (const void *)&gInstructions[458]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[488]
+    (const void *)&gInstructions[490]
 };
 
 const ND_TABLE_ASIZE gRootTable_root_e3_asize = 
@@ -13799,115 +13845,115 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize =
 const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[458]
+    (const void *)&gInstructions[460]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[460]
+    (const void *)&gInstructions[462]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[461]
+    (const void *)&gInstructions[463]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[462]
+    (const void *)&gInstructions[464]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[466]
+    (const void *)&gInstructions[468]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[469]
+    (const void *)&gInstructions[471]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[471]
+    (const void *)&gInstructions[473]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[473]
+    (const void *)&gInstructions[475]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[475]
+    (const void *)&gInstructions[477]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[477]
+    (const void *)&gInstructions[479]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[479]
+    (const void *)&gInstructions[481]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[481]
+    (const void *)&gInstructions[483]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[483]
+    (const void *)&gInstructions[485]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[485]
+    (const void *)&gInstructions[487]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[487]
+    (const void *)&gInstructions[489]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[490]
+    (const void *)&gInstructions[492]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[492]
+    (const void *)&gInstructions[494]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[562]
+    (const void *)&gInstructions[564]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[567]
+    (const void *)&gInstructions[569]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = 
@@ -13922,7 +13968,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[569]
+    (const void *)&gInstructions[571]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = 
@@ -13937,13 +13983,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[570]
+    (const void *)&gInstructions[572]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[571]
+    (const void *)&gInstructions[573]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = 
@@ -13958,13 +14004,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[581]
+    (const void *)&gInstructions[585]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[582]
+    (const void *)&gInstructions[586]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = 
@@ -13983,13 +14029,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[583]
+    (const void *)&gInstructions[587]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[584]
+    (const void *)&gInstructions[588]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = 
@@ -14008,13 +14054,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[585]
+    (const void *)&gInstructions[589]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[586]
+    (const void *)&gInstructions[590]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = 
@@ -14033,13 +14079,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[587]
+    (const void *)&gInstructions[591]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[588]
+    (const void *)&gInstructions[592]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = 
@@ -14071,55 +14117,55 @@ const ND_TABLE_DSIZE gRootTable_root_ad_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[589]
+    (const void *)&gInstructions[593]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[590]
+    (const void *)&gInstructions[594]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[591]
+    (const void *)&gInstructions[595]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[620]
+    (const void *)&gInstructions[624]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[621]
+    (const void *)&gInstructions[625]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[622]
+    (const void *)&gInstructions[626]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[623]
+    (const void *)&gInstructions[627]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[624]
+    (const void *)&gInstructions[628]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[625]
+    (const void *)&gInstructions[629]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = 
@@ -14134,13 +14180,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[626]
+    (const void *)&gInstructions[630]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[627]
+    (const void *)&gInstructions[631]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = 
@@ -14155,127 +14201,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[628]
+    (const void *)&gInstructions[632]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[629]
+    (const void *)&gInstructions[633]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[630]
+    (const void *)&gInstructions[634]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[631]
+    (const void *)&gInstructions[635]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[632]
+    (const void *)&gInstructions[636]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[633]
+    (const void *)&gInstructions[637]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[634]
+    (const void *)&gInstructions[638]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[635]
+    (const void *)&gInstructions[639]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[636]
+    (const void *)&gInstructions[640]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[637]
+    (const void *)&gInstructions[641]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[638]
+    (const void *)&gInstructions[642]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[639]
+    (const void *)&gInstructions[643]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[640]
+    (const void *)&gInstructions[644]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[641]
+    (const void *)&gInstructions[645]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[642]
+    (const void *)&gInstructions[646]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[643]
+    (const void *)&gInstructions[647]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[644]
+    (const void *)&gInstructions[648]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[645]
+    (const void *)&gInstructions[649]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[646]
+    (const void *)&gInstructions[650]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[647]
+    (const void *)&gInstructions[651]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[648]
+    (const void *)&gInstructions[652]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = 
@@ -14296,13 +14342,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[648]
+    (const void *)&gInstructions[652]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2531]
+    (const void *)&gInstructions[2535]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = 
@@ -14347,7 +14393,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[649]
+    (const void *)&gInstructions[653]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = 
@@ -14368,13 +14414,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[649]
+    (const void *)&gInstructions[653]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2534]
+    (const void *)&gInstructions[2538]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = 
@@ -14419,13 +14465,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[698]
+    (const void *)&gInstructions[702]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[699]
+    (const void *)&gInstructions[703]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = 
@@ -14444,13 +14490,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[702]
+    (const void *)&gInstructions[706]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[703]
+    (const void *)&gInstructions[707]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = 
@@ -14469,13 +14515,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[706]
+    (const void *)&gInstructions[710]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[707]
+    (const void *)&gInstructions[711]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = 
@@ -14494,13 +14540,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[710]
+    (const void *)&gInstructions[714]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[711]
+    (const void *)&gInstructions[715]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = 
@@ -14532,19 +14578,19 @@ const ND_TABLE_DSIZE gRootTable_root_a5_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[787]
+    (const void *)&gInstructions[791]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[847]
+    (const void *)&gInstructions[851]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2537]
+    (const void *)&gInstructions[2541]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = 
@@ -14563,73 +14609,73 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[790]
+    (const void *)&gInstructions[794]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[791]
+    (const void *)&gInstructions[795]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[792]
+    (const void *)&gInstructions[796]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[793]
+    (const void *)&gInstructions[797]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[794]
+    (const void *)&gInstructions[798]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[795]
+    (const void *)&gInstructions[799]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[802]
+    (const void *)&gInstructions[806]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[803]
+    (const void *)&gInstructions[807]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[804]
+    (const void *)&gInstructions[808]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[805]
+    (const void *)&gInstructions[809]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[806]
+    (const void *)&gInstructions[810]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[807]
+    (const void *)&gInstructions[811]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = 
@@ -14648,13 +14694,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[808]
+    (const void *)&gInstructions[812]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[809]
+    (const void *)&gInstructions[813]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = 
@@ -14673,13 +14719,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[810]
+    (const void *)&gInstructions[814]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[811]
+    (const void *)&gInstructions[815]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = 
@@ -14711,73 +14757,73 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[978]
+    (const void *)&gInstructions[982]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[979]
+    (const void *)&gInstructions[983]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[980]
+    (const void *)&gInstructions[984]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[981]
+    (const void *)&gInstructions[985]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[982]
+    (const void *)&gInstructions[986]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[983]
+    (const void *)&gInstructions[987]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[984]
+    (const void *)&gInstructions[988]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[985]
+    (const void *)&gInstructions[989]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[986]
+    (const void *)&gInstructions[990]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[987]
+    (const void *)&gInstructions[991]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[988]
+    (const void *)&gInstructions[992]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[989]
+    (const void *)&gInstructions[993]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = 
@@ -14798,13 +14844,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[990]
+    (const void *)&gInstructions[994]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[991]
+    (const void *)&gInstructions[995]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_61_dsize = 
@@ -14823,19 +14869,19 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[993]
+    (const void *)&gInstructions[997]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[994]
+    (const void *)&gInstructions[998]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[995]
+    (const void *)&gInstructions[999]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9d_dsize = 
@@ -14854,97 +14900,97 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1094]
+    (const void *)&gInstructions[1098]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1095]
+    (const void *)&gInstructions[1099]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1096]
+    (const void *)&gInstructions[1100]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1097]
+    (const void *)&gInstructions[1101]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1098]
+    (const void *)&gInstructions[1102]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1099]
+    (const void *)&gInstructions[1103]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1100]
+    (const void *)&gInstructions[1104]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1101]
+    (const void *)&gInstructions[1105]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1102]
+    (const void *)&gInstructions[1106]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1103]
+    (const void *)&gInstructions[1107]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1104]
+    (const void *)&gInstructions[1108]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1105]
+    (const void *)&gInstructions[1109]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1106]
+    (const void *)&gInstructions[1110]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1107]
+    (const void *)&gInstructions[1111]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1109]
+    (const void *)&gInstructions[1113]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1110]
+    (const void *)&gInstructions[1114]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_60_dsize = 
@@ -14963,19 +15009,19 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1111]
+    (const void *)&gInstructions[1115]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1112]
+    (const void *)&gInstructions[1116]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1113]
+    (const void *)&gInstructions[1117]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9c_dsize = 
@@ -14994,49 +15040,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1117]
+    (const void *)&gInstructions[1121]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1125]
+    (const void *)&gInstructions[1129]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1153]
+    (const void *)&gInstructions[1157]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1159]
+    (const void *)&gInstructions[1163]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1178]
+    (const void *)&gInstructions[1182]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1185]
+    (const void *)&gInstructions[1189]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1242]
+    (const void *)&gInstructions[1246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1251]
+    (const void *)&gInstructions[1255]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = 
@@ -15057,49 +15103,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1118]
+    (const void *)&gInstructions[1122]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1126]
+    (const void *)&gInstructions[1130]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1154]
+    (const void *)&gInstructions[1158]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1160]
+    (const void *)&gInstructions[1164]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1179]
+    (const void *)&gInstructions[1183]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1186]
+    (const void *)&gInstructions[1190]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1243]
+    (const void *)&gInstructions[1247]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1252]
+    (const void *)&gInstructions[1256]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = 
@@ -15120,49 +15166,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1119]
+    (const void *)&gInstructions[1123]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1127]
+    (const void *)&gInstructions[1131]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1155]
+    (const void *)&gInstructions[1159]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1161]
+    (const void *)&gInstructions[1165]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1180]
+    (const void *)&gInstructions[1184]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1187]
+    (const void *)&gInstructions[1191]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1244]
+    (const void *)&gInstructions[1248]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1253]
+    (const void *)&gInstructions[1257]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = 
@@ -15183,49 +15229,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1120]
+    (const void *)&gInstructions[1124]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1128]
+    (const void *)&gInstructions[1132]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1156]
+    (const void *)&gInstructions[1160]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1162]
+    (const void *)&gInstructions[1166]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1181]
+    (const void *)&gInstructions[1185]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1188]
+    (const void *)&gInstructions[1192]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1245]
+    (const void *)&gInstructions[1249]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1254]
+    (const void *)&gInstructions[1258]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = 
@@ -15246,49 +15292,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1121]
+    (const void *)&gInstructions[1125]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1129]
+    (const void *)&gInstructions[1133]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1157]
+    (const void *)&gInstructions[1161]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1163]
+    (const void *)&gInstructions[1167]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1182]
+    (const void *)&gInstructions[1186]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1189]
+    (const void *)&gInstructions[1193]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1246]
+    (const void *)&gInstructions[1250]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1255]
+    (const void *)&gInstructions[1259]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = 
@@ -15309,49 +15355,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1122]
+    (const void *)&gInstructions[1126]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1130]
+    (const void *)&gInstructions[1134]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1158]
+    (const void *)&gInstructions[1162]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1164]
+    (const void *)&gInstructions[1168]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1183]
+    (const void *)&gInstructions[1187]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1190]
+    (const void *)&gInstructions[1194]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1247]
+    (const void *)&gInstructions[1251]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1256]
+    (const void *)&gInstructions[1260]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = 
@@ -15372,85 +15418,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1147]
+    (const void *)&gInstructions[1151]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1148]
+    (const void *)&gInstructions[1152]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1149]
+    (const void *)&gInstructions[1153]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1150]
+    (const void *)&gInstructions[1154]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1177]
+    (const void *)&gInstructions[1181]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1184]
+    (const void *)&gInstructions[1188]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1193]
+    (const void *)&gInstructions[1197]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1194]
+    (const void *)&gInstructions[1198]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1195]
+    (const void *)&gInstructions[1199]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1196]
+    (const void *)&gInstructions[1200]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1197]
+    (const void *)&gInstructions[1201]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1198]
+    (const void *)&gInstructions[1202]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1203]
+    (const void *)&gInstructions[1207]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1204]
+    (const void *)&gInstructions[1208]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = 
@@ -15469,13 +15515,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1205]
+    (const void *)&gInstructions[1209]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1206]
+    (const void *)&gInstructions[1210]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = 
@@ -15494,13 +15540,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1207]
+    (const void *)&gInstructions[1211]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1208]
+    (const void *)&gInstructions[1212]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = 
@@ -15519,13 +15565,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1209]
+    (const void *)&gInstructions[1213]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1210]
+    (const void *)&gInstructions[1214]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = 
@@ -15557,31 +15603,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1276]
+    (const void *)&gInstructions[1280]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1277]
+    (const void *)&gInstructions[1281]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1279]
+    (const void *)&gInstructions[1283]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1281]
+    (const void *)&gInstructions[1285]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1282]
+    (const void *)&gInstructions[1286]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = 
@@ -15600,13 +15646,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1283]
+    (const void *)&gInstructions[1287]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1284]
+    (const void *)&gInstructions[1288]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = 
@@ -15625,13 +15671,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1285]
+    (const void *)&gInstructions[1289]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1286]
+    (const void *)&gInstructions[1290]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = 
@@ -15650,13 +15696,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1287]
+    (const void *)&gInstructions[1291]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1288]
+    (const void *)&gInstructions[1292]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = 
@@ -15688,163 +15734,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1293]
+    (const void *)&gInstructions[1297]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1294]
+    (const void *)&gInstructions[1298]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1295]
+    (const void *)&gInstructions[1299]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1296]
+    (const void *)&gInstructions[1300]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1297]
+    (const void *)&gInstructions[1301]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1298]
+    (const void *)&gInstructions[1302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1322]
+    (const void *)&gInstructions[1326]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1323]
+    (const void *)&gInstructions[1327]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1324]
+    (const void *)&gInstructions[1328]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1325]
+    (const void *)&gInstructions[1329]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2519]
+    (const void *)&gInstructions[2523]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2535]
+    (const void *)&gInstructions[2539]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2536]
+    (const void *)&gInstructions[2540]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2538]
+    (const void *)&gInstructions[2542]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2539]
+    (const void *)&gInstructions[2543]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2540]
+    (const void *)&gInstructions[2544]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2541]
+    (const void *)&gInstructions[2545]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2542]
+    (const void *)&gInstructions[2546]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2543]
+    (const void *)&gInstructions[2547]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2544]
+    (const void *)&gInstructions[2548]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2552]
+    (const void *)&gInstructions[2556]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2553]
+    (const void *)&gInstructions[2557]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2554]
+    (const void *)&gInstructions[2558]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2555]
+    (const void *)&gInstructions[2559]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2556]
+    (const void *)&gInstructions[2560]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2557]
+    (const void *)&gInstructions[2561]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2558]
+    (const void *)&gInstructions[2562]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_opcode = 
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
index 5f570d5..b75bba9 100644
--- a/bddisasm/include/table_vex.h
+++ b/bddisasm/include/table_vex.h
@@ -49,7 +49,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1191]
+    (const void *)&gInstructions[1195]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = 
@@ -66,7 +66,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1250]
+    (const void *)&gInstructions[1254]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = 
@@ -83,7 +83,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1259]
+    (const void *)&gInstructions[1263]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = 
@@ -205,7 +205,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[875]
+    (const void *)&gInstructions[879]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = 
@@ -222,7 +222,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[876]
+    (const void *)&gInstructions[880]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[568]
+    (const void *)&gInstructions[570]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = 
@@ -291,7 +291,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1333]
+    (const void *)&gInstructions[1337]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = 
@@ -356,7 +356,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1291]
+    (const void *)&gInstructions[1295]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = 
@@ -406,7 +406,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1335]
+    (const void *)&gInstructions[1339]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = 
@@ -467,7 +467,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[728]
+    (const void *)&gInstructions[732]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = 
@@ -495,7 +495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1317]
+    (const void *)&gInstructions[1321]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = 
@@ -541,7 +541,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1318]
+    (const void *)&gInstructions[1322]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = 
@@ -576,7 +576,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1319]
+    (const void *)&gInstructions[1323]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = 
@@ -611,7 +611,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1320]
+    (const void *)&gInstructions[1324]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = 
@@ -646,7 +646,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1321]
+    (const void *)&gInstructions[1325]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = 
@@ -692,7 +692,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1331]
+    (const void *)&gInstructions[1335]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = 
@@ -727,7 +727,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1332]
+    (const void *)&gInstructions[1336]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = 
@@ -762,7 +762,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1334]
+    (const void *)&gInstructions[1338]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = 
@@ -808,7 +808,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1367]
+    (const void *)&gInstructions[1371]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = 
@@ -825,7 +825,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1369]
+    (const void *)&gInstructions[1373]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = 
@@ -842,7 +842,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1371]
+    (const void *)&gInstructions[1375]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = 
@@ -859,7 +859,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1373]
+    (const void *)&gInstructions[1377]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = 
@@ -876,7 +876,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1374]
+    (const void *)&gInstructions[1378]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = 
@@ -904,7 +904,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1392]
+    (const void *)&gInstructions[1396]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = 
@@ -950,7 +950,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1398]
+    (const void *)&gInstructions[1402]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = 
@@ -996,7 +996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1405]
+    (const void *)&gInstructions[1409]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = 
@@ -1022,7 +1022,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1407]
+    (const void *)&gInstructions[1411]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = 
@@ -1048,7 +1048,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1438]
+    (const void *)&gInstructions[1442]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = 
@@ -1063,7 +1063,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1439]
+    (const void *)&gInstructions[1443]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = 
@@ -1100,13 +1100,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1528]
+    (const void *)&gInstructions[1532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1530]
+    (const void *)&gInstructions[1534]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = 
@@ -1132,13 +1132,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1532]
+    (const void *)&gInstructions[1536]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1534]
+    (const void *)&gInstructions[1538]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = 
@@ -1164,13 +1164,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1536]
+    (const void *)&gInstructions[1540]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1538]
+    (const void *)&gInstructions[1542]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = 
@@ -1196,13 +1196,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1540]
+    (const void *)&gInstructions[1544]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1542]
+    (const void *)&gInstructions[1546]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = 
@@ -1228,13 +1228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1544]
+    (const void *)&gInstructions[1548]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1546]
+    (const void *)&gInstructions[1550]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = 
@@ -1260,13 +1260,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1548]
+    (const void *)&gInstructions[1552]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1550]
+    (const void *)&gInstructions[1554]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = 
@@ -1292,13 +1292,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1560]
+    (const void *)&gInstructions[1564]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1562]
+    (const void *)&gInstructions[1566]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = 
@@ -1324,13 +1324,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1564]
+    (const void *)&gInstructions[1568]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1566]
+    (const void *)&gInstructions[1570]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = 
@@ -1356,13 +1356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1568]
+    (const void *)&gInstructions[1572]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1570]
+    (const void *)&gInstructions[1574]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = 
@@ -1388,13 +1388,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1576]
+    (const void *)&gInstructions[1580]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1578]
+    (const void *)&gInstructions[1582]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = 
@@ -1420,13 +1420,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1580]
+    (const void *)&gInstructions[1584]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1582]
+    (const void *)&gInstructions[1586]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = 
@@ -1452,13 +1452,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1584]
+    (const void *)&gInstructions[1588]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1586]
+    (const void *)&gInstructions[1590]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = 
@@ -1484,13 +1484,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1588]
+    (const void *)&gInstructions[1592]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1590]
+    (const void *)&gInstructions[1594]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = 
@@ -1516,13 +1516,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1592]
+    (const void *)&gInstructions[1596]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1594]
+    (const void *)&gInstructions[1598]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = 
@@ -1548,13 +1548,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1596]
+    (const void *)&gInstructions[1600]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1598]
+    (const void *)&gInstructions[1602]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = 
@@ -1580,13 +1580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1600]
+    (const void *)&gInstructions[1604]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1602]
+    (const void *)&gInstructions[1606]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = 
@@ -1612,13 +1612,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1604]
+    (const void *)&gInstructions[1608]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1606]
+    (const void *)&gInstructions[1610]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = 
@@ -1644,13 +1644,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1608]
+    (const void *)&gInstructions[1612]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1610]
+    (const void *)&gInstructions[1614]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = 
@@ -1676,13 +1676,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1624]
+    (const void *)&gInstructions[1628]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1626]
+    (const void *)&gInstructions[1630]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = 
@@ -1708,13 +1708,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1628]
+    (const void *)&gInstructions[1632]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1630]
+    (const void *)&gInstructions[1634]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = 
@@ -1740,13 +1740,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1632]
+    (const void *)&gInstructions[1636]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1634]
+    (const void *)&gInstructions[1638]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = 
@@ -1772,13 +1772,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1636]
+    (const void *)&gInstructions[1640]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1638]
+    (const void *)&gInstructions[1642]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = 
@@ -1804,13 +1804,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1640]
+    (const void *)&gInstructions[1644]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1642]
+    (const void *)&gInstructions[1646]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = 
@@ -1836,13 +1836,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1644]
+    (const void *)&gInstructions[1648]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1646]
+    (const void *)&gInstructions[1650]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = 
@@ -1868,13 +1868,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1656]
+    (const void *)&gInstructions[1660]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1658]
+    (const void *)&gInstructions[1662]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = 
@@ -1900,13 +1900,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1660]
+    (const void *)&gInstructions[1664]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1662]
+    (const void *)&gInstructions[1666]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = 
@@ -1932,13 +1932,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1664]
+    (const void *)&gInstructions[1668]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1666]
+    (const void *)&gInstructions[1670]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = 
@@ -1964,13 +1964,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1668]
+    (const void *)&gInstructions[1672]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1670]
+    (const void *)&gInstructions[1674]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = 
@@ -1996,13 +1996,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1672]
+    (const void *)&gInstructions[1676]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1674]
+    (const void *)&gInstructions[1678]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = 
@@ -2028,13 +2028,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1676]
+    (const void *)&gInstructions[1680]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1678]
+    (const void *)&gInstructions[1682]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = 
@@ -2060,13 +2060,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1696]
+    (const void *)&gInstructions[1700]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1698]
+    (const void *)&gInstructions[1702]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = 
@@ -2101,13 +2101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1708]
+    (const void *)&gInstructions[1712]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1710]
+    (const void *)&gInstructions[1714]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = 
@@ -2142,7 +2142,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1724]
+    (const void *)&gInstructions[1728]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = 
@@ -2168,7 +2168,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1746]
+    (const void *)&gInstructions[1750]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = 
@@ -2203,7 +2203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1747]
+    (const void *)&gInstructions[1751]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = 
@@ -2238,7 +2238,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1748]
+    (const void *)&gInstructions[1752]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = 
@@ -2273,7 +2273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1749]
+    (const void *)&gInstructions[1753]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = 
@@ -2308,7 +2308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1833]
+    (const void *)&gInstructions[1837]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = 
@@ -2334,7 +2334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1901]
+    (const void *)&gInstructions[1905]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = 
@@ -2351,7 +2351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1903]
+    (const void *)&gInstructions[1907]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = 
@@ -2368,7 +2368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1906]
+    (const void *)&gInstructions[1910]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = 
@@ -2385,7 +2385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1912]
+    (const void *)&gInstructions[1916]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = 
@@ -2402,7 +2402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1952]
+    (const void *)&gInstructions[1956]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = 
@@ -2428,7 +2428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1955]
+    (const void *)&gInstructions[1959]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = 
@@ -2454,7 +2454,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1960]
+    (const void *)&gInstructions[1964]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = 
@@ -2480,7 +2480,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1963]
+    (const void *)&gInstructions[1967]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = 
@@ -2506,7 +2506,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1975]
+    (const void *)&gInstructions[1979]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = 
@@ -2523,7 +2523,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1985]
+    (const void *)&gInstructions[1989]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = 
@@ -2540,7 +2540,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2011]
+    (const void *)&gInstructions[2015]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = 
@@ -2566,7 +2566,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2013]
+    (const void *)&gInstructions[2017]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = 
@@ -2592,7 +2592,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2015]
+    (const void *)&gInstructions[2019]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = 
@@ -2618,7 +2618,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2017]
+    (const void *)&gInstructions[2021]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = 
@@ -2644,7 +2644,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_53_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2022]
+    (const void *)&gInstructions[2026]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = 
@@ -2681,7 +2681,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2035]
+    (const void *)&gInstructions[2039]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = 
@@ -2707,7 +2707,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2039]
+    (const void *)&gInstructions[2043]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = 
@@ -2733,7 +2733,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2047]
+    (const void *)&gInstructions[2051]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = 
@@ -2770,13 +2770,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2077]
+    (const void *)&gInstructions[2081]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2079]
+    (const void *)&gInstructions[2083]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = 
@@ -2811,13 +2811,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2081]
+    (const void *)&gInstructions[2085]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2083]
+    (const void *)&gInstructions[2087]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = 
@@ -2852,7 +2852,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2087]
+    (const void *)&gInstructions[2091]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = 
@@ -2869,7 +2869,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2089]
+    (const void *)&gInstructions[2093]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = 
@@ -2886,7 +2886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2096]
+    (const void *)&gInstructions[2100]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = 
@@ -2903,7 +2903,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2099]
+    (const void *)&gInstructions[2103]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = 
@@ -2931,7 +2931,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2101]
+    (const void *)&gInstructions[2105]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = 
@@ -2948,7 +2948,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2103]
+    (const void *)&gInstructions[2107]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = 
@@ -2965,7 +2965,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2104]
+    (const void *)&gInstructions[2108]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = 
@@ -2982,7 +2982,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2135]
+    (const void *)&gInstructions[2139]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = 
@@ -2999,13 +2999,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2138]
+    (const void *)&gInstructions[2142]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2140]
+    (const void *)&gInstructions[2144]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = 
@@ -3040,13 +3040,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2139]
+    (const void *)&gInstructions[2143]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2141]
+    (const void *)&gInstructions[2145]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = 
@@ -3081,7 +3081,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2143]
+    (const void *)&gInstructions[2147]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = 
@@ -3098,7 +3098,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2145]
+    (const void *)&gInstructions[2149]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = 
@@ -3115,7 +3115,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2152]
+    (const void *)&gInstructions[2156]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = 
@@ -3132,7 +3132,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2155]
+    (const void *)&gInstructions[2159]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = 
@@ -3149,7 +3149,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2157]
+    (const void *)&gInstructions[2161]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = 
@@ -3166,7 +3166,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2159]
+    (const void *)&gInstructions[2163]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = 
@@ -3183,7 +3183,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2166]
+    (const void *)&gInstructions[2170]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = 
@@ -3200,7 +3200,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2169]
+    (const void *)&gInstructions[2173]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = 
@@ -3217,13 +3217,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2190]
+    (const void *)&gInstructions[2194]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2191]
+    (const void *)&gInstructions[2195]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = 
@@ -3251,13 +3251,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2193]
+    (const void *)&gInstructions[2197]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2194]
+    (const void *)&gInstructions[2198]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = 
@@ -3285,13 +3285,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2196]
+    (const void *)&gInstructions[2200]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2197]
+    (const void *)&gInstructions[2201]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = 
@@ -3319,13 +3319,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2199]
+    (const void *)&gInstructions[2203]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2200]
+    (const void *)&gInstructions[2204]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = 
@@ -3353,13 +3353,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2202]
+    (const void *)&gInstructions[2206]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2203]
+    (const void *)&gInstructions[2207]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = 
@@ -3387,13 +3387,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2205]
+    (const void *)&gInstructions[2209]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2206]
+    (const void *)&gInstructions[2210]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = 
@@ -3421,13 +3421,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2216]
+    (const void *)&gInstructions[2220]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2217]
+    (const void *)&gInstructions[2221]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = 
@@ -3455,13 +3455,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2219]
+    (const void *)&gInstructions[2223]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2220]
+    (const void *)&gInstructions[2224]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = 
@@ -3489,13 +3489,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2222]
+    (const void *)&gInstructions[2226]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2223]
+    (const void *)&gInstructions[2227]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = 
@@ -3523,13 +3523,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2225]
+    (const void *)&gInstructions[2229]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2226]
+    (const void *)&gInstructions[2230]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = 
@@ -3557,13 +3557,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2228]
+    (const void *)&gInstructions[2232]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2229]
+    (const void *)&gInstructions[2233]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = 
@@ -3591,13 +3591,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2231]
+    (const void *)&gInstructions[2235]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2232]
+    (const void *)&gInstructions[2236]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = 
@@ -3625,7 +3625,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2234]
+    (const void *)&gInstructions[2238]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = 
@@ -3642,7 +3642,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2236]
+    (const void *)&gInstructions[2240]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = 
@@ -3659,7 +3659,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2242]
+    (const void *)&gInstructions[2246]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = 
@@ -3676,7 +3676,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2313]
+    (const void *)&gInstructions[2317]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = 
@@ -3693,7 +3693,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2321]
+    (const void *)&gInstructions[2325]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = 
@@ -3710,7 +3710,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2322]
+    (const void *)&gInstructions[2326]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = 
@@ -3727,7 +3727,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2323]
+    (const void *)&gInstructions[2327]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = 
@@ -3744,13 +3744,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2335]
+    (const void *)&gInstructions[2339]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2337]
+    (const void *)&gInstructions[2341]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = 
@@ -3776,7 +3776,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2350]
+    (const void *)&gInstructions[2354]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = 
@@ -3802,13 +3802,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2368]
+    (const void *)&gInstructions[2372]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2370]
+    (const void *)&gInstructions[2374]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = 
@@ -3834,7 +3834,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2394]
+    (const void *)&gInstructions[2398]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = 
@@ -3851,7 +3851,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2499]
+    (const void *)&gInstructions[2503]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = 
@@ -3877,7 +3877,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2500]
+    (const void *)&gInstructions[2504]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = 
@@ -4187,7 +4187,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1270]
+    (const void *)&gInstructions[1274]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = 
@@ -4268,13 +4268,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1744]
+    (const void *)&gInstructions[1748]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2490]
+    (const void *)&gInstructions[2494]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = 
@@ -4315,13 +4315,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[493]
+    (const void *)&gInstructions[495]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[494]
+    (const void *)&gInstructions[496]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = 
@@ -4356,13 +4356,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[495]
+    (const void *)&gInstructions[497]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[496]
+    (const void *)&gInstructions[498]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = 
@@ -4408,13 +4408,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[497]
+    (const void *)&gInstructions[499]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[498]
+    (const void *)&gInstructions[500]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = 
@@ -4449,13 +4449,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[503]
+    (const void *)&gInstructions[505]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[504]
+    (const void *)&gInstructions[506]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = 
@@ -4501,13 +4501,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[499]
+    (const void *)&gInstructions[501]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[500]
+    (const void *)&gInstructions[502]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = 
@@ -4542,13 +4542,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[501]
+    (const void *)&gInstructions[503]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[502]
+    (const void *)&gInstructions[504]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = 
@@ -4594,7 +4594,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[505]
+    (const void *)&gInstructions[507]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = 
@@ -4640,7 +4640,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[506]
+    (const void *)&gInstructions[508]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = 
@@ -4686,13 +4686,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[507]
+    (const void *)&gInstructions[509]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[512]
+    (const void *)&gInstructions[514]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = 
@@ -4718,13 +4718,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[508]
+    (const void *)&gInstructions[510]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[513]
+    (const void *)&gInstructions[515]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = 
@@ -4759,13 +4759,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[517]
+    (const void *)&gInstructions[519]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[522]
+    (const void *)&gInstructions[524]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = 
@@ -4791,13 +4791,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[518]
+    (const void *)&gInstructions[520]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[523]
+    (const void *)&gInstructions[525]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = 
@@ -4843,13 +4843,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[509]
+    (const void *)&gInstructions[511]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[514]
+    (const void *)&gInstructions[516]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = 
@@ -4884,13 +4884,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[519]
+    (const void *)&gInstructions[521]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[524]
+    (const void *)&gInstructions[526]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = 
@@ -4936,7 +4936,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[510]
+    (const void *)&gInstructions[512]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = 
@@ -4971,13 +4971,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[515]
+    (const void *)&gInstructions[517]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[520]
+    (const void *)&gInstructions[522]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = 
@@ -5012,7 +5012,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[525]
+    (const void *)&gInstructions[527]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = 
@@ -5058,7 +5058,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[511]
+    (const void *)&gInstructions[513]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = 
@@ -5093,13 +5093,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[516]
+    (const void *)&gInstructions[518]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[521]
+    (const void *)&gInstructions[523]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = 
@@ -5134,7 +5134,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[526]
+    (const void *)&gInstructions[528]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = 
@@ -5180,13 +5180,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[527]
+    (const void *)&gInstructions[529]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[528]
+    (const void *)&gInstructions[530]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = 
@@ -5221,13 +5221,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[529]
+    (const void *)&gInstructions[531]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[530]
+    (const void *)&gInstructions[532]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = 
@@ -5273,13 +5273,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[531]
+    (const void *)&gInstructions[533]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[532]
+    (const void *)&gInstructions[534]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = 
@@ -5314,13 +5314,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[533]
+    (const void *)&gInstructions[535]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[538]
+    (const void *)&gInstructions[540]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = 
@@ -5366,13 +5366,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[534]
+    (const void *)&gInstructions[536]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[535]
+    (const void *)&gInstructions[537]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = 
@@ -5407,13 +5407,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[536]
+    (const void *)&gInstructions[538]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[537]
+    (const void *)&gInstructions[539]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = 
@@ -5459,13 +5459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[547]
+    (const void *)&gInstructions[549]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[548]
+    (const void *)&gInstructions[550]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = 
@@ -5500,13 +5500,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[549]
+    (const void *)&gInstructions[551]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[550]
+    (const void *)&gInstructions[552]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = 
@@ -5552,7 +5552,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[551]
+    (const void *)&gInstructions[553]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = 
@@ -5587,13 +5587,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[552]
+    (const void *)&gInstructions[554]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[553]
+    (const void *)&gInstructions[555]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = 
@@ -5639,13 +5639,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[554]
+    (const void *)&gInstructions[556]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[555]
+    (const void *)&gInstructions[557]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = 
@@ -5680,13 +5680,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[556]
+    (const void *)&gInstructions[558]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[557]
+    (const void *)&gInstructions[559]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = 
@@ -5732,13 +5732,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[558]
+    (const void *)&gInstructions[560]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[559]
+    (const void *)&gInstructions[561]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = 
@@ -5773,13 +5773,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[560]
+    (const void *)&gInstructions[562]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[561]
+    (const void *)&gInstructions[563]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = 
@@ -5825,25 +5825,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1357]
+    (const void *)&gInstructions[1361]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1359]
+    (const void *)&gInstructions[1363]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1361]
+    (const void *)&gInstructions[1365]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1363]
+    (const void *)&gInstructions[1367]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = 
@@ -5860,13 +5860,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1364]
+    (const void *)&gInstructions[1368]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1365]
+    (const void *)&gInstructions[1369]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = 
@@ -5883,13 +5883,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1379]
+    (const void *)&gInstructions[1383]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1381]
+    (const void *)&gInstructions[1385]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = 
@@ -5906,13 +5906,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1383]
+    (const void *)&gInstructions[1387]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1385]
+    (const void *)&gInstructions[1389]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = 
@@ -5929,25 +5929,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1409]
+    (const void *)&gInstructions[1413]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1411]
+    (const void *)&gInstructions[1415]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1413]
+    (const void *)&gInstructions[1417]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1415]
+    (const void *)&gInstructions[1419]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = 
@@ -5964,13 +5964,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1417]
+    (const void *)&gInstructions[1421]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1419]
+    (const void *)&gInstructions[1423]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = 
@@ -5987,13 +5987,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1423]
+    (const void *)&gInstructions[1427]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1424]
+    (const void *)&gInstructions[1428]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = 
@@ -6010,13 +6010,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1430]
+    (const void *)&gInstructions[1434]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1469]
+    (const void *)&gInstructions[1473]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = 
@@ -6033,19 +6033,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1426]
+    (const void *)&gInstructions[1430]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1441]
+    (const void *)&gInstructions[1445]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1474]
+    (const void *)&gInstructions[1478]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = 
@@ -6062,13 +6062,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1432]
+    (const void *)&gInstructions[1436]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1433]
+    (const void *)&gInstructions[1437]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = 
@@ -6085,13 +6085,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1443]
+    (const void *)&gInstructions[1447]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1444]
+    (const void *)&gInstructions[1448]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = 
@@ -6108,13 +6108,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1456]
+    (const void *)&gInstructions[1460]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1464]
+    (const void *)&gInstructions[1468]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = 
@@ -6131,13 +6131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1454]
+    (const void *)&gInstructions[1458]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1466]
+    (const void *)&gInstructions[1470]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = 
@@ -6154,13 +6154,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1460]
+    (const void *)&gInstructions[1464]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1462]
+    (const void *)&gInstructions[1466]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = 
@@ -6177,13 +6177,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1479]
+    (const void *)&gInstructions[1483]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1482]
+    (const void *)&gInstructions[1486]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = 
@@ -6200,25 +6200,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1493]
+    (const void *)&gInstructions[1497]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1495]
+    (const void *)&gInstructions[1499]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1497]
+    (const void *)&gInstructions[1501]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1499]
+    (const void *)&gInstructions[1503]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = 
@@ -6235,13 +6235,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1725]
+    (const void *)&gInstructions[1729]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1726]
+    (const void *)&gInstructions[1730]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = 
@@ -6258,13 +6258,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1727]
+    (const void *)&gInstructions[1731]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1728]
+    (const void *)&gInstructions[1732]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = 
@@ -6281,7 +6281,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1743]
+    (const void *)&gInstructions[1747]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = 
@@ -6307,7 +6307,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1745]
+    (const void *)&gInstructions[1749]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = 
@@ -6344,25 +6344,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1751]
+    (const void *)&gInstructions[1755]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1753]
+    (const void *)&gInstructions[1757]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1755]
+    (const void *)&gInstructions[1759]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1757]
+    (const void *)&gInstructions[1761]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = 
@@ -6379,25 +6379,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1764]
+    (const void *)&gInstructions[1768]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1766]
+    (const void *)&gInstructions[1770]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1768]
+    (const void *)&gInstructions[1772]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1770]
+    (const void *)&gInstructions[1774]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = 
@@ -6414,13 +6414,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1777]
+    (const void *)&gInstructions[1781]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1781]
+    (const void *)&gInstructions[1785]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = 
@@ -6437,13 +6437,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1778]
+    (const void *)&gInstructions[1782]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1782]
+    (const void *)&gInstructions[1786]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = 
@@ -6460,13 +6460,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1785]
+    (const void *)&gInstructions[1789]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1842]
+    (const void *)&gInstructions[1846]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_w = 
@@ -6503,13 +6503,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1786]
+    (const void *)&gInstructions[1790]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1843]
+    (const void *)&gInstructions[1847]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_w = 
@@ -6535,7 +6535,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1844]
+    (const void *)&gInstructions[1848]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = 
@@ -6563,13 +6563,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1790]
+    (const void *)&gInstructions[1794]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1791]
+    (const void *)&gInstructions[1795]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = 
@@ -6586,7 +6586,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1809]
+    (const void *)&gInstructions[1813]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = 
@@ -6603,7 +6603,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1826]
+    (const void *)&gInstructions[1830]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = 
@@ -6629,7 +6629,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1822]
+    (const void *)&gInstructions[1826]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = 
@@ -6655,7 +6655,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1857]
+    (const void *)&gInstructions[1861]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = 
@@ -6672,13 +6672,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1792]
+    (const void *)&gInstructions[1796]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1798]
+    (const void *)&gInstructions[1802]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = 
@@ -6695,13 +6695,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1793]
+    (const void *)&gInstructions[1797]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1799]
+    (const void *)&gInstructions[1803]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = 
@@ -6718,7 +6718,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1812]
+    (const void *)&gInstructions[1816]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = 
@@ -6744,7 +6744,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1816]
+    (const void *)&gInstructions[1820]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = 
@@ -6761,7 +6761,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1819]
+    (const void *)&gInstructions[1823]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = 
@@ -6787,7 +6787,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1855]
+    (const void *)&gInstructions[1859]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = 
@@ -6804,7 +6804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1813]
+    (const void *)&gInstructions[1817]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = 
@@ -6830,7 +6830,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1817]
+    (const void *)&gInstructions[1821]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = 
@@ -6867,7 +6867,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1823]
+    (const void *)&gInstructions[1827]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = 
@@ -6893,7 +6893,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1827]
+    (const void *)&gInstructions[1831]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = 
@@ -6930,7 +6930,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1828]
+    (const void *)&gInstructions[1832]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = 
@@ -6945,7 +6945,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1829]
+    (const void *)&gInstructions[1833]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = 
@@ -6971,7 +6971,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1831]
+    (const void *)&gInstructions[1835]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = 
@@ -6997,7 +6997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1835]
+    (const void *)&gInstructions[1839]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = 
@@ -7012,7 +7012,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1837]
+    (const void *)&gInstructions[1841]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = 
@@ -7038,7 +7038,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1845]
+    (const void *)&gInstructions[1849]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = 
@@ -7066,13 +7066,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1850]
+    (const void *)&gInstructions[1854]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1851]
+    (const void *)&gInstructions[1855]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = 
@@ -7087,13 +7087,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1862]
+    (const void *)&gInstructions[1866]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1863]
+    (const void *)&gInstructions[1867]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = 
@@ -7108,13 +7108,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1868]
+    (const void *)&gInstructions[1872]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1872]
+    (const void *)&gInstructions[1876]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = 
@@ -7131,13 +7131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1852]
+    (const void *)&gInstructions[1856]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1853]
+    (const void *)&gInstructions[1857]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = 
@@ -7152,13 +7152,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1864]
+    (const void *)&gInstructions[1868]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1865]
+    (const void *)&gInstructions[1869]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = 
@@ -7173,13 +7173,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1869]
+    (const void *)&gInstructions[1873]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1873]
+    (const void *)&gInstructions[1877]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = 
@@ -7196,25 +7196,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1882]
+    (const void *)&gInstructions[1886]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1884]
+    (const void *)&gInstructions[1888]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1886]
+    (const void *)&gInstructions[1890]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1888]
+    (const void *)&gInstructions[1892]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = 
@@ -7231,13 +7231,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1893]
+    (const void *)&gInstructions[1897]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1895]
+    (const void *)&gInstructions[1899]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = 
@@ -7254,7 +7254,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1908]
+    (const void *)&gInstructions[1912]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = 
@@ -7271,7 +7271,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1910]
+    (const void *)&gInstructions[1914]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = 
@@ -7288,7 +7288,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1914]
+    (const void *)&gInstructions[1918]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = 
@@ -7305,7 +7305,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1916]
+    (const void *)&gInstructions[1920]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = 
@@ -7322,7 +7322,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1918]
+    (const void *)&gInstructions[1922]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = 
@@ -7339,7 +7339,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1920]
+    (const void *)&gInstructions[1924]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = 
@@ -7356,7 +7356,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1922]
+    (const void *)&gInstructions[1926]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = 
@@ -7373,7 +7373,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1924]
+    (const void *)&gInstructions[1928]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = 
@@ -7390,7 +7390,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1926]
+    (const void *)&gInstructions[1930]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = 
@@ -7407,7 +7407,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1928]
+    (const void *)&gInstructions[1932]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = 
@@ -7424,7 +7424,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1930]
+    (const void *)&gInstructions[1934]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = 
@@ -7441,7 +7441,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1933]
+    (const void *)&gInstructions[1937]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = 
@@ -7458,7 +7458,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1935]
+    (const void *)&gInstructions[1939]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = 
@@ -7475,7 +7475,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1940]
+    (const void *)&gInstructions[1944]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = 
@@ -7492,7 +7492,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1942]
+    (const void *)&gInstructions[1946]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = 
@@ -7509,7 +7509,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1971]
+    (const void *)&gInstructions[1975]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = 
@@ -7526,7 +7526,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1973]
+    (const void *)&gInstructions[1977]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = 
@@ -7543,7 +7543,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1977]
+    (const void *)&gInstructions[1981]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = 
@@ -7560,7 +7560,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1981]
+    (const void *)&gInstructions[1985]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = 
@@ -7577,7 +7577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1983]
+    (const void *)&gInstructions[1987]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = 
@@ -7594,7 +7594,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1987]
+    (const void *)&gInstructions[1991]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = 
@@ -7611,7 +7611,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2073]
+    (const void *)&gInstructions[2077]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = 
@@ -7648,7 +7648,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2116]
+    (const void *)&gInstructions[2120]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = 
@@ -7665,7 +7665,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2117]
+    (const void *)&gInstructions[2121]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = 
@@ -7702,7 +7702,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2137]
+    (const void *)&gInstructions[2141]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = 
@@ -7719,7 +7719,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2148]
+    (const void *)&gInstructions[2152]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = 
@@ -7736,7 +7736,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2150]
+    (const void *)&gInstructions[2154]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = 
@@ -7753,7 +7753,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2162]
+    (const void *)&gInstructions[2166]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = 
@@ -7770,7 +7770,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2164]
+    (const void *)&gInstructions[2168]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = 
@@ -7787,7 +7787,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2178]
+    (const void *)&gInstructions[2182]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = 
@@ -7813,7 +7813,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2238]
+    (const void *)&gInstructions[2242]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = 
@@ -7830,7 +7830,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2240]
+    (const void *)&gInstructions[2244]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = 
@@ -7847,7 +7847,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2245]
+    (const void *)&gInstructions[2249]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = 
@@ -7864,7 +7864,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2248]
+    (const void *)&gInstructions[2252]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = 
@@ -7881,7 +7881,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2253]
+    (const void *)&gInstructions[2257]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = 
@@ -7898,7 +7898,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2279]
+    (const void *)&gInstructions[2283]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = 
@@ -7915,19 +7915,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2316]
+    (const void *)&gInstructions[2320]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2318]
+    (const void *)&gInstructions[2322]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2320]
+    (const void *)&gInstructions[2324]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = 
@@ -7944,19 +7944,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2326]
+    (const void *)&gInstructions[2330]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2345]
+    (const void *)&gInstructions[2349]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2359]
+    (const void *)&gInstructions[2363]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = 
@@ -7997,7 +7997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2327]
+    (const void *)&gInstructions[2331]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = 
@@ -8014,25 +8014,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2329]
+    (const void *)&gInstructions[2333]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2332]
+    (const void *)&gInstructions[2336]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2362]
+    (const void *)&gInstructions[2366]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2365]
+    (const void *)&gInstructions[2369]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = 
@@ -8073,7 +8073,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2333]
+    (const void *)&gInstructions[2337]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = 
@@ -8090,19 +8090,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2341]
+    (const void *)&gInstructions[2345]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2355]
+    (const void *)&gInstructions[2359]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2374]
+    (const void *)&gInstructions[2378]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = 
@@ -8143,7 +8143,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2342]
+    (const void *)&gInstructions[2346]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = 
@@ -8160,7 +8160,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2346]
+    (const void *)&gInstructions[2350]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = 
@@ -8177,7 +8177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2356]
+    (const void *)&gInstructions[2360]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = 
@@ -8194,7 +8194,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2360]
+    (const void *)&gInstructions[2364]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = 
@@ -8211,7 +8211,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2366]
+    (const void *)&gInstructions[2370]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = 
@@ -8228,7 +8228,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2375]
+    (const void *)&gInstructions[2379]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = 
@@ -8245,7 +8245,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2377]
+    (const void *)&gInstructions[2381]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = 
@@ -8262,7 +8262,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2379]
+    (const void *)&gInstructions[2383]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = 
@@ -8279,7 +8279,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2381]
+    (const void *)&gInstructions[2385]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = 
@@ -8296,7 +8296,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2383]
+    (const void *)&gInstructions[2387]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = 
@@ -8313,7 +8313,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2385]
+    (const void *)&gInstructions[2389]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = 
@@ -8330,7 +8330,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2387]
+    (const void *)&gInstructions[2391]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = 
@@ -8347,7 +8347,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2389]
+    (const void *)&gInstructions[2393]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = 
@@ -8364,7 +8364,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2391]
+    (const void *)&gInstructions[2395]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = 
@@ -8381,7 +8381,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2404]
+    (const void *)&gInstructions[2408]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = 
@@ -8398,7 +8398,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2406]
+    (const void *)&gInstructions[2410]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = 
@@ -8415,7 +8415,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2408]
+    (const void *)&gInstructions[2412]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = 
@@ -8432,7 +8432,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2410]
+    (const void *)&gInstructions[2414]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = 
@@ -8449,7 +8449,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2412]
+    (const void *)&gInstructions[2416]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = 
@@ -8466,7 +8466,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2414]
+    (const void *)&gInstructions[2418]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = 
@@ -8483,7 +8483,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2416]
+    (const void *)&gInstructions[2420]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = 
@@ -8500,7 +8500,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2418]
+    (const void *)&gInstructions[2422]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = 
@@ -8517,7 +8517,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2419]
+    (const void *)&gInstructions[2423]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = 
@@ -8534,13 +8534,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2434]
+    (const void *)&gInstructions[2438]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2435]
+    (const void *)&gInstructions[2439]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = 
@@ -8557,13 +8557,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2456]
+    (const void *)&gInstructions[2460]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2457]
+    (const void *)&gInstructions[2461]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = 
@@ -8580,13 +8580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2479]
+    (const void *)&gInstructions[2483]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2481]
+    (const void *)&gInstructions[2485]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = 
@@ -8603,25 +8603,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2483]
+    (const void *)&gInstructions[2487]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2485]
+    (const void *)&gInstructions[2489]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2487]
+    (const void *)&gInstructions[2491]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2489]
+    (const void *)&gInstructions[2493]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = 
@@ -8638,25 +8638,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2492]
+    (const void *)&gInstructions[2496]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2494]
+    (const void *)&gInstructions[2498]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2496]
+    (const void *)&gInstructions[2500]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2498]
+    (const void *)&gInstructions[2502]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = 
@@ -8673,13 +8673,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2502]
+    (const void *)&gInstructions[2506]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2504]
+    (const void *)&gInstructions[2508]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = 
@@ -8696,13 +8696,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2506]
+    (const void *)&gInstructions[2510]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2508]
+    (const void *)&gInstructions[2512]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = 
@@ -8719,13 +8719,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2510]
+    (const void *)&gInstructions[2514]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2512]
+    (const void *)&gInstructions[2516]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = 
@@ -8742,13 +8742,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2514]
+    (const void *)&gInstructions[2518]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2516]
+    (const void *)&gInstructions[2520]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = 
@@ -8765,13 +8765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2517]
+    (const void *)&gInstructions[2521]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2518]
+    (const void *)&gInstructions[2522]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = 
@@ -9062,13 +9062,13 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[539]
+    (const void *)&gInstructions[541]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[542]
+    (const void *)&gInstructions[544]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = 
@@ -9114,13 +9114,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[540]
+    (const void *)&gInstructions[542]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[541]
+    (const void *)&gInstructions[543]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = 
@@ -9166,13 +9166,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[543]
+    (const void *)&gInstructions[545]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[546]
+    (const void *)&gInstructions[548]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = 
@@ -9218,13 +9218,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[544]
+    (const void *)&gInstructions[546]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[545]
+    (const void *)&gInstructions[547]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = 
@@ -9270,7 +9270,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1165]
+    (const void *)&gInstructions[1169]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = 
@@ -9298,7 +9298,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1375]
+    (const void *)&gInstructions[1379]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = 
@@ -9326,7 +9326,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1388]
+    (const void *)&gInstructions[1392]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = 
@@ -9343,7 +9343,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1389]
+    (const void *)&gInstructions[1393]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = 
@@ -9360,7 +9360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1390]
+    (const void *)&gInstructions[1394]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = 
@@ -9386,7 +9386,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1391]
+    (const void *)&gInstructions[1395]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = 
@@ -9412,7 +9412,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1446]
+    (const void *)&gInstructions[1450]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = 
@@ -9427,7 +9427,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1447]
+    (const void *)&gInstructions[1451]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = 
@@ -9464,7 +9464,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1501]
+    (const void *)&gInstructions[1505]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = 
@@ -9492,7 +9492,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1502]
+    (const void *)&gInstructions[1506]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = 
@@ -9509,7 +9509,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1509]
+    (const void *)&gInstructions[1513]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = 
@@ -9546,7 +9546,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1514]
+    (const void *)&gInstructions[1518]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = 
@@ -9583,7 +9583,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1521]
+    (const void *)&gInstructions[1525]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = 
@@ -9600,7 +9600,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1522]
+    (const void *)&gInstructions[1526]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = 
@@ -9637,13 +9637,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1551]
+    (const void *)&gInstructions[1555]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1552]
+    (const void *)&gInstructions[1556]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = 
@@ -9669,13 +9669,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1553]
+    (const void *)&gInstructions[1557]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1554]
+    (const void *)&gInstructions[1558]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = 
@@ -9701,13 +9701,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1555]
+    (const void *)&gInstructions[1559]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1556]
+    (const void *)&gInstructions[1560]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = 
@@ -9733,13 +9733,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1557]
+    (const void *)&gInstructions[1561]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1558]
+    (const void *)&gInstructions[1562]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = 
@@ -9765,13 +9765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1571]
+    (const void *)&gInstructions[1575]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1572]
+    (const void *)&gInstructions[1576]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = 
@@ -9797,13 +9797,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1573]
+    (const void *)&gInstructions[1577]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1574]
+    (const void *)&gInstructions[1578]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = 
@@ -9829,13 +9829,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1611]
+    (const void *)&gInstructions[1615]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1612]
+    (const void *)&gInstructions[1616]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = 
@@ -9861,13 +9861,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1613]
+    (const void *)&gInstructions[1617]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1614]
+    (const void *)&gInstructions[1618]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = 
@@ -9893,13 +9893,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1615]
+    (const void *)&gInstructions[1619]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1616]
+    (const void *)&gInstructions[1620]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = 
@@ -9925,13 +9925,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1617]
+    (const void *)&gInstructions[1621]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1618]
+    (const void *)&gInstructions[1622]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = 
@@ -9957,13 +9957,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1619]
+    (const void *)&gInstructions[1623]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1620]
+    (const void *)&gInstructions[1624]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = 
@@ -9989,13 +9989,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1621]
+    (const void *)&gInstructions[1625]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1622]
+    (const void *)&gInstructions[1626]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = 
@@ -10021,13 +10021,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1647]
+    (const void *)&gInstructions[1651]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1648]
+    (const void *)&gInstructions[1652]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = 
@@ -10053,13 +10053,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1649]
+    (const void *)&gInstructions[1653]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1650]
+    (const void *)&gInstructions[1654]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = 
@@ -10085,13 +10085,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1651]
+    (const void *)&gInstructions[1655]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1652]
+    (const void *)&gInstructions[1656]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = 
@@ -10117,13 +10117,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1653]
+    (const void *)&gInstructions[1657]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1654]
+    (const void *)&gInstructions[1658]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = 
@@ -10149,13 +10149,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1679]
+    (const void *)&gInstructions[1683]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1680]
+    (const void *)&gInstructions[1684]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = 
@@ -10181,13 +10181,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1681]
+    (const void *)&gInstructions[1685]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1682]
+    (const void *)&gInstructions[1686]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = 
@@ -10213,13 +10213,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1683]
+    (const void *)&gInstructions[1687]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1684]
+    (const void *)&gInstructions[1688]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = 
@@ -10245,13 +10245,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1685]
+    (const void *)&gInstructions[1689]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1686]
+    (const void *)&gInstructions[1690]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = 
@@ -10277,7 +10277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1720]
+    (const void *)&gInstructions[1724]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = 
@@ -10303,7 +10303,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1722]
+    (const void *)&gInstructions[1726]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = 
@@ -10329,7 +10329,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1729]
+    (const void *)&gInstructions[1733]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = 
@@ -10366,7 +10366,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1734]
+    (const void *)&gInstructions[1738]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = 
@@ -10403,7 +10403,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1741]
+    (const void *)&gInstructions[1745]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = 
@@ -10420,7 +10420,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1742]
+    (const void *)&gInstructions[1746]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = 
@@ -10457,7 +10457,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1874]
+    (const void *)&gInstructions[1878]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = 
@@ -10474,7 +10474,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1932]
+    (const void *)&gInstructions[1936]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = 
@@ -10491,7 +10491,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1943]
+    (const void *)&gInstructions[1947]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = 
@@ -10517,7 +10517,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1948]
+    (const void *)&gInstructions[1952]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = 
@@ -10543,7 +10543,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1949]
+    (const void *)&gInstructions[1953]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = 
@@ -10560,7 +10560,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1965]
+    (const void *)&gInstructions[1969]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = 
@@ -10577,7 +10577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1978]
+    (const void *)&gInstructions[1982]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = 
@@ -10605,7 +10605,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1979]
+    (const void *)&gInstructions[1983]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = 
@@ -10633,7 +10633,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1988]
+    (const void *)&gInstructions[1992]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = 
@@ -10661,7 +10661,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1989]
+    (const void *)&gInstructions[1993]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = 
@@ -10689,7 +10689,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2018]
+    (const void *)&gInstructions[2022]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = 
@@ -10726,7 +10726,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2019]
+    (const void *)&gInstructions[2023]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = 
@@ -10763,13 +10763,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2029]
+    (const void *)&gInstructions[2033]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2030]
+    (const void *)&gInstructions[2034]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = 
@@ -10795,13 +10795,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2031]
+    (const void *)&gInstructions[2035]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2032]
+    (const void *)&gInstructions[2036]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = 
@@ -10827,7 +10827,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2036]
+    (const void *)&gInstructions[2040]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = 
@@ -10853,7 +10853,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2040]
+    (const void *)&gInstructions[2044]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = 
@@ -10879,7 +10879,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2044]
+    (const void *)&gInstructions[2048]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = 
@@ -10916,7 +10916,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2050]
+    (const void *)&gInstructions[2054]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = 
@@ -10953,7 +10953,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2064]
+    (const void *)&gInstructions[2068]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = 
@@ -10970,7 +10970,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2065]
+    (const void *)&gInstructions[2069]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = 
@@ -11007,13 +11007,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2067]
+    (const void *)&gInstructions[2071]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2069]
+    (const void *)&gInstructions[2073]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_w = 
@@ -11050,7 +11050,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2074]
+    (const void *)&gInstructions[2078]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = 
@@ -11067,7 +11067,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2075]
+    (const void *)&gInstructions[2079]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = 
@@ -11104,7 +11104,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2108]
+    (const void *)&gInstructions[2112]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = 
@@ -11121,7 +11121,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2109]
+    (const void *)&gInstructions[2113]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = 
@@ -11158,13 +11158,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2111]
+    (const void *)&gInstructions[2115]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2113]
+    (const void *)&gInstructions[2117]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_w = 
@@ -11201,7 +11201,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2444]
+    (const void *)&gInstructions[2448]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = 
@@ -11218,7 +11218,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2445]
+    (const void *)&gInstructions[2449]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = 
@@ -11235,7 +11235,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2446]
+    (const void *)&gInstructions[2450]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = 
@@ -11252,7 +11252,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2447]
+    (const void *)&gInstructions[2451]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = 
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
index abe041a..a777cd4 100644
--- a/bddisasm/include/table_xop.h
+++ b/bddisasm/include/table_xop.h
@@ -10,13 +10,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf =
 const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[596]
+    (const void *)&gInstructions[600]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[597]
+    (const void *)&gInstructions[601]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = 
@@ -330,13 +330,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1315]
+    (const void *)&gInstructions[1319]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1339]
+    (const void *)&gInstructions[1343]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = 
@@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[578]
+    (const void *)&gInstructions[582]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1266]
+    (const void *)&gInstructions[1270]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = 
@@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1691]
+    (const void *)&gInstructions[1695]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1692]
+    (const void *)&gInstructions[1696]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1693]
+    (const void *)&gInstructions[1697]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1694]
+    (const void *)&gInstructions[1698]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2084]
+    (const void *)&gInstructions[2088]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2085]
+    (const void *)&gInstructions[2089]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2086]
+    (const void *)&gInstructions[2090]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2088]
+    (const void *)&gInstructions[2092]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2090]
+    (const void *)&gInstructions[2094]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2091]
+    (const void *)&gInstructions[2095]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2092]
+    (const void *)&gInstructions[2096]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2093]
+    (const void *)&gInstructions[2097]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2094]
+    (const void *)&gInstructions[2098]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2095]
+    (const void *)&gInstructions[2099]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2097]
+    (const void *)&gInstructions[2101]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2098]
+    (const void *)&gInstructions[2102]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2100]
+    (const void *)&gInstructions[2104]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2102]
+    (const void *)&gInstructions[2106]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2105]
+    (const void *)&gInstructions[2109]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2267]
+    (const void *)&gInstructions[2271]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2268]
+    (const void *)&gInstructions[2272]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_90_w = 
@@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2270]
+    (const void *)&gInstructions[2274]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2271]
+    (const void *)&gInstructions[2275]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_92_w = 
@@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2273]
+    (const void *)&gInstructions[2277]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2274]
+    (const void *)&gInstructions[2278]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_93_w = 
@@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2276]
+    (const void *)&gInstructions[2280]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2277]
+    (const void *)&gInstructions[2281]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_91_w = 
@@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2284]
+    (const void *)&gInstructions[2288]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2285]
+    (const void *)&gInstructions[2289]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_98_w = 
@@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2286]
+    (const void *)&gInstructions[2290]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2287]
+    (const void *)&gInstructions[2291]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9a_w = 
@@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2288]
+    (const void *)&gInstructions[2292]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2289]
+    (const void *)&gInstructions[2293]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9b_w = 
@@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2290]
+    (const void *)&gInstructions[2294]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2291]
+    (const void *)&gInstructions[2295]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_99_w = 
@@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2292]
+    (const void *)&gInstructions[2296]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2293]
+    (const void *)&gInstructions[2297]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_94_w = 
@@ -723,13 +723,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2294]
+    (const void *)&gInstructions[2298]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2305]
+    (const void *)&gInstructions[2309]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_95_w = 
@@ -744,13 +744,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2295]
+    (const void *)&gInstructions[2299]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2296]
+    (const void *)&gInstructions[2300]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_96_w = 
@@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2303]
+    (const void *)&gInstructions[2307]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2304]
+    (const void *)&gInstructions[2308]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_97_w = 
@@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1966]
+    (const void *)&gInstructions[1970]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1967]
+    (const void *)&gInstructions[1971]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a2_w = 
@@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1996]
+    (const void *)&gInstructions[2000]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1997]
+    (const void *)&gInstructions[2001]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2002]
+    (const void *)&gInstructions[2006]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2003]
+    (const void *)&gInstructions[2007]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2004]
+    (const void *)&gInstructions[2008]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2005]
+    (const void *)&gInstructions[2009]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2006]
+    (const void *)&gInstructions[2010]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2007]
+    (const void *)&gInstructions[2011]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2120]
+    (const void *)&gInstructions[2124]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2121]
+    (const void *)&gInstructions[2125]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2122]
+    (const void *)&gInstructions[2126]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2123]
+    (const void *)&gInstructions[2127]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2124]
+    (const void *)&gInstructions[2128]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2125]
+    (const void *)&gInstructions[2129]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2126]
+    (const void *)&gInstructions[2130]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2127]
+    (const void *)&gInstructions[2131]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2128]
+    (const void *)&gInstructions[2132]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2129]
+    (const void *)&gInstructions[2133]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2130]
+    (const void *)&gInstructions[2134]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2131]
+    (const void *)&gInstructions[2135]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2256]
+    (const void *)&gInstructions[2260]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2257]
+    (const void *)&gInstructions[2261]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a3_w = 
@@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2266]
+    (const void *)&gInstructions[2270]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2269]
+    (const void *)&gInstructions[2273]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2272]
+    (const void *)&gInstructions[2276]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2275]
+    (const void *)&gInstructions[2279]
 };
 
 const ND_TABLE_OPCODE gXopTable_root_08_opcode = 
diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h
index df18324..35ba4bc 100644
--- a/bddisasm/include/tabledefs.h
+++ b/bddisasm/include/tabledefs.h
@@ -319,6 +319,7 @@ typedef enum _ND_OPERAND_SIZE_SPEC
     ND_OPS_v2,
     ND_OPS_v3,
     ND_OPS_v4,
+    ND_OPS_v5,
     ND_OPS_v8,
     // 4 + 8 bytes accessed on the shadow stack by the SAVPREVSSP instruction.
     ND_OPS_12,
diff --git a/bddisasm_test/fred/fred_64 b/bddisasm_test/fred/fred_64
new file mode 100644
index 0000000..52774a8
Binary files /dev/null and b/bddisasm_test/fred/fred_64 differ
diff --git a/bddisasm_test/fred/fred_64.asm b/bddisasm_test/fred/fred_64.asm
new file mode 100644
index 0000000..a088468
--- /dev/null
+++ b/bddisasm_test/fred/fred_64.asm
@@ -0,0 +1,10 @@
+    bits 64
+    
+    db 0xF3, 0x0F, 0x01, 0xCA           ; ERETU
+    db 0xF2, 0x0F, 0x01, 0xCA           ; ERETS
+    db 0xF2, 0x0F, 0x00, 0x30           ; LKGS word ptr [rax]
+    db 0xF2, 0x48, 0x0F, 0x00, 0x30     ; LKGS word ptr [rax]
+    db 0xF2, 0x66, 0x0F, 0x00, 0x30     ; LKGS word ptr [rax]
+    db 0xF2, 0x0F, 0x00, 0xF1           ; LKGS ecx
+    db 0xF2, 0x48, 0x0F, 0x00, 0xF1     ; LKGS rcx
+    db 0xF2, 0x66, 0x0F, 0x00, 0xF1     ; LKGS cx
\ No newline at end of file
diff --git a/bddisasm_test/fred/fred_64.result b/bddisasm_test/fred/fred_64.result
new file mode 100644
index 0000000..9b1b763
--- /dev/null
+++ b/bddisasm_test/fred/fred_64.result
@@ -0,0 +1,147 @@
+0000000000000000 f30f01ca                        ERETU
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: FRED, Ins cat: FRED, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 17
+        FLAGS access
+                Entire register
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 4, RegCount: 1
+        Operand: 3, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:          Segment, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:          Segment, RegSize:  8, RegId: 2, RegCount: 1
+        Operand: 5, Acc:  R-,  Type:     Memory, Size: 40, RawSize: 40, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+        Operand: 6, Acc:  CRCW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:              SSP, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 7, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000101, RegCount: 1
+        Operand: 8, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+0000000000000004 f20f01ca                        ERETS
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: FRED, Ins cat: FRED, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 17
+        FLAGS access
+                Entire register
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 4, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:     Memory, Size: 40, RawSize: 40, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+        Operand: 4, Acc:  CRCW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:              SSP, RegSize:  8, RegId: 0, RegCount: 1
+
+0000000000000008 f20f0030                        LKGS      word ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size:  2, RawSize:  2, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+000000000000000C f2480f0030                      LKGS      word ptr [rax]
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size:  2, RawSize:  2, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+0000000000000011 f2660f0030                      LKGS      word ptr [rax]
+        DSIZE: 16, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size:  2, RawSize:  2, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+0000000000000016 f20f00f1                        LKGS      ecx
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: M, RegType:  General Purpose, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+000000000000001A f2480f00f1                      LKGS      rcx
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: M, RegType:  General Purpose, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
+000000000000001F f2660f00f1                      LKGS      cx
+        DSIZE: 16, ASIZE: 64, VLEN: -
+        ISA Set: LKGS, Ins cat: LKGS, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 18
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  2, RawSize:  2, Encoding: M, RegType:  General Purpose, RegSize:  2, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: 0xc0000102, RegCount: 1
+
diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c
index ebd469a..b31513c 100644
--- a/disasmtool/disasmtool.c
+++ b/disasmtool/disasmtool.c
@@ -133,6 +133,7 @@ const char* set_to_string(
     case ND_SET_F16C:                  return "F16C";
     case ND_SET_FMA:                   return "FMA";
     case ND_SET_FMA4:                  return "FMA4";
+    case ND_SET_FRED:                  return "FRED";
     case ND_SET_FXSAVE:                return "FXSAVE";
     case ND_SET_GFNI:                  return "GFNI";
     case ND_SET_HRESET:                return "HRESET";
@@ -147,6 +148,7 @@ const char* set_to_string(
     case ND_SET_INVPCID:               return "INVPCID";
     case ND_SET_INVLPGB:               return "INVLPGB";
     case ND_SET_KL:                    return "KL";
+    case ND_SET_LKGS:                  return "LKGS";
     case ND_SET_LONGMODE:              return "LONGMODE";
     case ND_SET_LWP:                   return "LWP";
     case ND_SET_LZCNT:                 return "LZCNT";
@@ -250,6 +252,7 @@ const char* category_to_string(
     case ND_CAT_EXPAND:               return "EXPAND";
     case ND_CAT_FLAGOP:               return "FLAGOP";
     case ND_CAT_FMA4:                 return "FMA4";
+    case ND_CAT_FRED:                 return "FRED";
     case ND_CAT_GATHER:               return "GATHER";
     case ND_CAT_GFNI:                 return "GFNI";
     case ND_CAT_HRESET:               return "HRESET";
@@ -261,6 +264,7 @@ const char* category_to_string(
     case ND_CAT_KL:                   return "KL";
     case ND_CAT_KMASK:                return "KMASK";
     case ND_CAT_KNL:                  return "KNL";
+    case ND_CAT_LKGS:                 return "LKGS";
     case ND_CAT_LOGIC:                return "LOGIC";
     case ND_CAT_LOGICAL:              return "LOGICAL";
     case ND_CAT_LOGICAL_FP:           return "LOGICAL_FP";
diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp
index 47aafb2..9224b7e 100644
--- a/disasmtool_lix/dumpers.cpp
+++ b/disasmtool_lix/dumpers.cpp
@@ -220,6 +220,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_ENQCMD: return "enqcmd";
     case ND_INS_ENQCMDS: return "enqcmds";
     case ND_INS_ENTER: return "enter";
+    case ND_INS_ERETS: return "erets";
+    case ND_INS_ERETU: return "eretu";
     case ND_INS_EXTRACTPS: return "extractps";
     case ND_INS_EXTRQ: return "extrq";
     case ND_INS_F2XM1: return "f2xm1";
@@ -386,6 +388,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_LGDT: return "lgdt";
     case ND_INS_LGS: return "lgs";
     case ND_INS_LIDT: return "lidt";
+    case ND_INS_LKGS: return "lkgs";
     case ND_INS_LLDT: return "lldt";
     case ND_INS_LLWPCB: return "llwpcb";
     case ND_INS_LMSW: return "lmsw";
@@ -1588,6 +1591,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_EXPAND: return "expand";
     case ND_CAT_FLAGOP: return "flagop";
     case ND_CAT_FMA4: return "fma4";
+    case ND_CAT_FRED: return "fred";
     case ND_CAT_GATHER: return "gather";
     case ND_CAT_GFNI: return "gfni";
     case ND_CAT_HRESET: return "hreset";
@@ -1599,6 +1603,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_KL: return "kl";
     case ND_CAT_KMASK: return "kmask";
     case ND_CAT_KNL: return "knl";
+    case ND_CAT_LKGS: return "lkgs";
     case ND_CAT_LOGIC: return "logic";
     case ND_CAT_LOGICAL: return "logical";
     case ND_CAT_LOGICAL_FP: return "logical_fp";
@@ -1710,6 +1715,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_F16C: return "f16c";
     case ND_SET_FMA: return "fma";
     case ND_SET_FMA4: return "fma4";
+    case ND_SET_FRED: return "fred";
     case ND_SET_FXSAVE: return "fxsave";
     case ND_SET_GFNI: return "gfni";
     case ND_SET_HRESET: return "hreset";
@@ -1724,6 +1730,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_I86: return "i86";
     case ND_SET_INVPCID: return "invpcid";
     case ND_SET_KL: return "kl";
+    case ND_SET_LKGS: return "lkgs";
     case ND_SET_LONGMODE: return "longmode";
     case ND_SET_LWP: return "lwp";
     case ND_SET_LZCNT: return "lzcnt";
diff --git a/inc/constants.h b/inc/constants.h
index f397edc..6c94e81 100644
--- a/inc/constants.h
+++ b/inc/constants.h
@@ -162,6 +162,8 @@ typedef enum _ND_INS_CLASS
     ND_INS_ENQCMD,
     ND_INS_ENQCMDS,
     ND_INS_ENTER,
+    ND_INS_ERETS,
+    ND_INS_ERETU,
     ND_INS_EXTRACTPS,
     ND_INS_EXTRQ,
     ND_INS_F2XM1,
@@ -329,6 +331,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_LGDT,
     ND_INS_LGS,
     ND_INS_LIDT,
+    ND_INS_LKGS,
     ND_INS_LLDT,
     ND_INS_LLWPCB,
     ND_INS_LMSW,
@@ -1535,6 +1538,7 @@ typedef enum _ND_INS_SET
     ND_SET_F16C,
     ND_SET_FMA,
     ND_SET_FMA4,
+    ND_SET_FRED,
     ND_SET_FXSAVE,
     ND_SET_GFNI,
     ND_SET_HRESET,
@@ -1549,6 +1553,7 @@ typedef enum _ND_INS_SET
     ND_SET_INVLPGB,
     ND_SET_INVPCID,
     ND_SET_KL,
+    ND_SET_LKGS,
     ND_SET_LONGMODE,
     ND_SET_LWP,
     ND_SET_LZCNT,
@@ -1645,6 +1650,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_EXPAND,
     ND_CAT_FLAGOP,
     ND_CAT_FMA4,
+    ND_CAT_FRED,
     ND_CAT_GATHER,
     ND_CAT_GFNI,
     ND_CAT_HRESET,
@@ -1656,6 +1662,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_KL,
     ND_CAT_KMASK,
     ND_CAT_KNL,
+    ND_CAT_LKGS,
     ND_CAT_LOGIC,
     ND_CAT_LOGICAL,
     ND_CAT_LOGICAL_FP,
diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h
index 60d3da0..5950072 100644
--- a/inc/cpuidflags.h
+++ b/inc/cpuidflags.h
@@ -87,6 +87,8 @@
 #define ND_CFF_AMXINT8                  ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
 #define ND_CFF_AVXVNNI                  ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
 #define ND_CFF_AVX512BF16               ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
+#define ND_CFF_FRED                     ND_CFF(0x00000007, 0x00000001, NDR_EAX, 17)
+#define ND_CFF_LKGS                     ND_CFF(0x00000007, 0x00000001, NDR_EAX, 18)
 #define ND_CFF_HRESET                   ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
 #define ND_CFF_XSAVEOPT                 ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
 #define ND_CFF_XSAVEC                   ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
diff --git a/inc/disasmtypes.h b/inc/disasmtypes.h
index 45f7175..0e45072 100644
--- a/inc/disasmtypes.h
+++ b/inc/disasmtypes.h
@@ -8,6 +8,21 @@
 #if defined(KERNEL_MODE) && defined(_MSC_VER)
 # include <ntddk.h>
 # include <Ntstrsafe.h>
+# include <basetsd.h>
+
+typedef UINT8 uint8_t;
+typedef UINT16 uint16_t;
+typedef UINT32 uint32_t;
+typedef UINT64 uint64_t;
+
+typedef INT8 int8_t;
+typedef INT16 int16_t;
+typedef INT32 int32_t;
+typedef INT64 int64_t;
+
+typedef _Bool bool;
+#define false 0
+#define true 1
 
 #elif defined(__KERNEL__) && defined(__GNUC__)
 
diff --git a/inc/version.h b/inc/version.h
index b17b6d1..7442b23 100644
--- a/inc/version.h
+++ b/inc/version.h
@@ -6,7 +6,7 @@
 #define DISASM_VER_H
 
 #define DISASM_VERSION_MAJOR        1
-#define DISASM_VERSION_MINOR        31
-#define DISASM_VERSION_REVISION     8
+#define DISASM_VERSION_MINOR        32
+#define DISASM_VERSION_REVISION     0
 
 #endif // DISASM_VER_H
diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py
index 8dcd736..eddb7aa 100644
--- a/isagenerator/disasmlib.py
+++ b/isagenerator/disasmlib.py
@@ -167,6 +167,7 @@ valid_opsize = [
     'v2',           # Two stack words.
     'v3',           # Three stack words.
     'v4',           # Four stack words.
+    'v5',           # Five stack words.
     'v8',           # Eight stack words.
 
     # These are aliased over 'dq.*' encodings.
diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py
index ac5ce5f..4c4e618 100644
--- a/isagenerator/generate_tables.py
+++ b/isagenerator/generate_tables.py
@@ -209,6 +209,7 @@ opsize = {
     'v2'       : 'ND_OPS_v2',
     'v3'       : 'ND_OPS_v3',
     'v4'       : 'ND_OPS_v4',
+    'v5'       : 'ND_OPS_v5',
     'v8'       : 'ND_OPS_v8',
     'oq'       : 'ND_OPS_oq',
     'p'        : 'ND_OPS_p',
diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat
index 30090cb..b15ade6 100644
--- a/isagenerator/instructions/cpuid.dat
+++ b/isagenerator/instructions/cpuid.dat
@@ -90,6 +90,8 @@ AMXINT8                 : 0x00000007, 0x00000000, EDX, 25
 
 AVXVNNI                 : 0x00000007, 0x00000001, EAX, 4
 AVX512BF16              : 0x00000007, 0x00000001, EAX, 5
+FRED                    : 0x00000007, 0x00000001, EAX, 17
+LKGS                    : 0x00000007, 0x00000001, EAX, 18
 HRESET                  : 0x00000007, 0x00000001, EAX, 22
 
 XSAVEOPT                : 0x0000000D, 0x00000001, EAX, 0
diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat
index 8e75894..b18ae8e 100644
--- a/isagenerator/instructions/table_0F.dat
+++ b/isagenerator/instructions/table_0F.dat
@@ -9,7 +9,9 @@ LLDT           Ew            LDTR                      [            0x0F 0x00 /2
 LTR            Ew            TR                        [            0x0F 0x00 /3]              s:I286PROT, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL|NOREAL
 VERR           Ew            Fv                        [            0x0F 0x00 /4]              s:I286PROT, t:SYSTEM, w:R|W, f:ZF=m, m:NOREAL
 VERW           Ew            Fv                        [            0x0F 0x00 /5]              s:I286PROT, t:SYSTEM, w:R|W, f:ZF=m, m:NOREAL
-JMPE           Ev            rIP                       [            0x0F 0x00 /6]              s:I64, t:SYSTEM, w:R|W, m:NO64 
+JMPE           Ev            rIP                       [         NP 0x0F 0x00 /6]              s:I64, t:SYSTEM, w:R|W, m:NO64 
+LKGS           Mw            KGSBASE                   [       0xF2 0x0F 0x00 /6:mem]          s:LKGS, t:LKGS, w:R|W, m:KERNEL|O64|NOSGX
+LKGS           Rv            KGSBASE                   [       0xF2 0x0F 0x00 /6:reg]          s:LKGS, t:LKGS, w:R|W, m:KERNEL|O64|NOSGX
 SGDT           Ms            GDTR                      [            0x0F 0x01 /0:mem]          s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX
 SIDT           Ms            IDTR                      [            0x0F 0x01 /1:mem]          s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX
 LGDT           Ms            GDTR                      [            0x0F 0x01 /2:mem]          s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL
@@ -28,6 +30,8 @@ PCONFIG        nil           EAX,RBX,RCX,RDX           [         NP 0x0F 0x01 /0
 MONITOR        nil           EAX,ECX,EDX               [         NP 0x0F 0x01 /0xC8]           s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86
 MWAIT          nil           EAX,ECX                   [         NP 0x0F 0x01 /0xC9]           s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86
 CLAC           nil           Fv                        [         NP 0x0F 0x01 /0xCA]           s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86
+ERETU          nil           rIP,Fv,rSP,CS,SS,Kv5,SSP,GSBASE,KGSBASE [0xF3 0x0F 0x01 /0xCA]    s:FRED, t:FRED, w:W|W|W|W|W|R|CRCW|RW|RW, m:KERNEL|O64|NOTSX, a:F64
+ERETS          nil           rIP,Fv,rSP,Kv5,SSP        [       0xF2 0x0F 0x01 /0xCA]           s:FRED, t:FRED, w:W|W|W|R|CRCW, m:KERNEL|O64|NOTSX, a:F64
 STAC           nil           Fv                        [         NP 0x0F 0x01 /0xCB]           s:SMAP, t:SMAP, w:W, f:AC=1, m:KERNEL|NOV86
 TDCALL         nil           nil                       [       0x66 0x0F 0x01 /0xCC]           s:TDX, t:TDX, m:KERNEL|VMXNROOT
 SEAMRET        nil           nil                       [       0x66 0x0F 0x01 /0xCD]           s:TDX, t:TDX, f:VMX, m:SEAMR
diff --git a/pybddisasm/setup.py b/pybddisasm/setup.py
index aa9613d..5a794fd 100644
--- a/pybddisasm/setup.py
+++ b/pybddisasm/setup.py
@@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
 from codecs import open
 
 VERSION = (0, 1, 3)
-LIBRARY_VERSION = (1, 31, 8)
+LIBRARY_VERSION = (1, 32, 0)
 LIBRARY_INSTRUX_SIZE = 864
 
 packages = ['pybddisasm']