From d61a6fa5dd844ded3e577397706852db6a22ae26 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Wed, 19 Aug 2020 19:14:22 +0300 Subject: [PATCH] * INC/DEC do not modify the CF. * Fixed FXSAVE64, PUSHAD and POPAD emulation - when explicit mnemonics were added for them, emulation support was not added, thus causing emulation to stop when encountering one of these. --- bddisasm/include/instructions.h | 40 ++++++++-------- bdshemu/bdshemu.c | 12 ++++- bdshemu_test/basic/test_64_incdec | 1 + bdshemu_test/basic/test_64_incdec.asm | 13 +++++ bdshemu_test/basic/test_64_incdec.result | 61 ++++++++++++++++++++++++ isagenerator/instructions/flags.dat | 10 +++- isagenerator/instructions/table_base.dat | 40 ++++++++-------- 7 files changed, 133 insertions(+), 44 deletions(-) create mode 100644 bdshemu_test/basic/test_64_incdec create mode 100644 bdshemu_test/basic/test_64_incdec.asm create mode 100644 bdshemu_test/basic/test_64_incdec.result diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index 2c2dc58..60830b5 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -3135,7 +3135,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3150,7 +3150,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3165,7 +3165,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3180,7 +3180,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3195,7 +3195,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3210,7 +3210,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3225,7 +3225,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3240,7 +3240,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3255,7 +3255,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3270,7 +3270,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6307,7 +6307,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6322,7 +6322,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6337,7 +6337,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6352,7 +6352,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6367,7 +6367,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6382,7 +6382,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6397,7 +6397,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6412,7 +6412,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6427,7 +6427,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6442,7 +6442,7 @@ const ND_INSTRUCTION gInstructions[2561] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { diff --git a/bdshemu/bdshemu.c b/bdshemu/bdshemu.c index 1d89d73..b1d8591 100644 --- a/bdshemu/bdshemu.c +++ b/bdshemu/bdshemu.c @@ -1363,7 +1363,8 @@ ShemuSetOperandValue( // OK: op->Size will be the FPU state size. ShemuSetBits(STACKBMP(Context), (gla + 0xC) - Context->StackBase, Context->Instruction.WordLength, 1); } - else if (Context->Instruction.Instruction == ND_INS_FXSAVE) + else if (Context->Instruction.Instruction == ND_INS_FXSAVE || + Context->Instruction.Instruction == ND_INS_FXSAVE64) { // OK: op->Size will be the FXSAVE size. ShemuSetBits(STACKBMP(Context), (gla + 0x8) - Context->StackBase, Context->Instruction.WordLength, 1); @@ -1545,7 +1546,7 @@ ShemuEmulate( { NDSTATUS ndstatus; SHEMU_VALUE res = { 0 }, dst = { 0 }, src = { 0 }, rcx = { 0 }, aux = { 0 }; - bool stop = false; + bool stop = false, cf; uint64_t rip = 0; if (NULL == Context) @@ -1660,6 +1661,7 @@ ShemuEmulate( break; case ND_INS_FXSAVE: + case ND_INS_FXSAVE64: src.Size = MIN(Context->Instruction.Operands[0].Size, sizeof(src.Value.XsaveArea)); src.Value.XsaveArea.FpuRip = Context->Registers.FpuRip; SET_OP(Context, 0, &src); @@ -1794,7 +1796,9 @@ ShemuEmulate( src.Value.Qwords[0] = 1; res.Size = src.Size; res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + cf = GET_FLAG(Context, NDR_RFLAG_CF); SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_FLAG(Context, NDR_RFLAG_CF, cf); SET_OP(Context, 0, &res); break; @@ -1804,7 +1808,9 @@ ShemuEmulate( src.Value.Qwords[0] = 1; res.Size = src.Size; res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + cf = GET_FLAG(Context, NDR_RFLAG_CF); SET_FLAGS(Context, res, dst, src, FM_SUB); + SET_FLAG(Context, NDR_RFLAG_CF, cf); SET_OP(Context, 0, &res); break; @@ -1821,6 +1827,7 @@ ShemuEmulate( break; case ND_INS_PUSHA: + case ND_INS_PUSHAD: src.Size = 32; src.Value.Dwords[7] = (uint32_t)Context->Registers.RegRax; src.Value.Dwords[6] = (uint32_t)Context->Registers.RegRcx; @@ -1834,6 +1841,7 @@ ShemuEmulate( break; case ND_INS_POPA: + case ND_INS_POPAD: GET_OP(Context, 1, &src); Context->Registers.RegRax = src.Value.Dwords[7]; Context->Registers.RegRcx = src.Value.Dwords[6]; diff --git a/bdshemu_test/basic/test_64_incdec b/bdshemu_test/basic/test_64_incdec new file mode 100644 index 0000000..5fe060d --- /dev/null +++ b/bdshemu_test/basic/test_64_incdec @@ -0,0 +1 @@ +1ÀøÿÈÿÈùÿÀÿÀÿÀÿÀÃ \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_incdec.asm b/bdshemu_test/basic/test_64_incdec.asm new file mode 100644 index 0000000..4c950dc --- /dev/null +++ b/bdshemu_test/basic/test_64_incdec.asm @@ -0,0 +1,13 @@ + + bits 64 + + xor eax, eax + clc + dec eax + dec eax + stc + inc eax + inc eax + inc eax + inc eax + retn \ No newline at end of file diff --git a/bdshemu_test/basic/test_64_incdec.result b/bdshemu_test/basic/test_64_incdec.result new file mode 100644 index 0000000..33d2c1d --- /dev/null +++ b/bdshemu_test/basic/test_64_incdec.result @@ -0,0 +1,61 @@ + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202 +Emulating: 0x0000000000200000 XOR eax, eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200002 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200002 CLC + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200003 RFLAGS = 0x0000000000000246 +Emulating: 0x0000000000200003 DEC eax + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200005 RFLAGS = 0x0000000000000286 +Emulating: 0x0000000000200005 DEC eax + RAX = 0x00000000fffffffe RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200007 RFLAGS = 0x0000000000000282 +Emulating: 0x0000000000200007 STC + RAX = 0x00000000fffffffe RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200008 RFLAGS = 0x0000000000000283 +Emulating: 0x0000000000200008 INC eax + RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000a RFLAGS = 0x0000000000000a87 +Emulating: 0x000000000020000a INC eax + RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000c RFLAGS = 0x0000000000000247 +Emulating: 0x000000000020000c INC eax + RAX = 0x0000000000000001 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x000000000020000e RFLAGS = 0x0000000000000203 +Emulating: 0x000000000020000e INC eax + RAX = 0x0000000000000002 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000 + RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000 + R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000 + R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000 + RIP = 0x0000000000200010 RFLAGS = 0x0000000000000203 +Emulating: 0x0000000000200010 RETN +Emulation terminated with status 0x00000002, flags: 0x0, 0 NOPs diff --git a/isagenerator/instructions/flags.dat b/isagenerator/instructions/flags.dat index 97f206d..ec45fa3 100644 --- a/isagenerator/instructions/flags.dat +++ b/isagenerator/instructions/flags.dat @@ -3,12 +3,15 @@ # Accepted flags: CF, PF, AF, ZF, TF, IF, OF, DF, AC, IOPL, RF, NT, VIF, VIP, VM # Accepted modifiers: t (tested), m (modified according to the result), 0 (cleared), 1 (set), u (undefined) -# All airthmetic instructions: ADD, SUB, CMP, XADD +# All arithmetic instructions: ADD, SUB, CMP, XADD ARITH : CF=m|PF=m|AF=m|ZF=m|SF=m|OF=m -# Airthmetic with carry instructions: ADC, SBB +# Arithmetic with carry instructions: ADC, SBB ARITHC : CF=t|CF=m|PF=m|AF=m|ZF=m|SF=m|OF=m +# INC/DEC do not alter CF. +INCDEC : PF=m|AF=m|ZF=m|SF=m|OF=m + # Logic instructions: OR, AND, XOR, TEST LOGIC : CF=0|PF=m|AF=u|ZF=m|SF=m|OF=0 @@ -55,6 +58,9 @@ REPCMPS : CF=m|PF=m|AF=m|ZF=t|ZF=m|SF=m|OF=m|DF=t # Used by PCMPESTRM, PCMPESTRI, PCMPISTRM, PCMPISTRI PCMPSTR : CF=m|PF=0|AF=0|ZF=m|SF=m|OF=m +# MOV to/from control/debug registers, all flags are undefined. +MOVCRDR : CF=u|PF=u|AF=u|ZF=u|SF=u|OF=u + # Used by VMX instructions. VMX : CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0 diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_base.dat index eb5842a..433d519 100644 --- a/isagenerator/instructions/table_base.dat +++ b/isagenerator/instructions/table_base.dat @@ -74,22 +74,22 @@ BHT nil nil [ 0x3E] s:UNK AAS nil AH,AL,Fv [ 0x3F] s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 # 0x40 - 0x4F -INC Zv Fv [ 0x40] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x41] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x42] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x43] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x44] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x45] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x46] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -INC Zv Fv [ 0x47] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x48] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x49] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4A] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4B] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4C] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4D] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4E] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 -DEC Zv Fv [ 0x4F] s:I86, t:ARITH, w:RW|W, f:ARITH, m:NO64 +INC Zv Fv [ 0x40] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x41] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x42] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x43] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x44] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x45] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x46] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC Zv Fv [ 0x47] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x48] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x49] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4A] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4B] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4C] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4D] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4E] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +DEC Zv Fv [ 0x4F] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 # 0x50 - 0x5F PUSH Zv Kv [ 0x50] s:I86, t:PUSH, w:R|W, a:D64 @@ -436,10 +436,10 @@ CLI nil Fv [ 0xFA] s:I86 STI nil Fv [ 0xFB] s:I86, t:FLAGOP, w:RW, f:IF=1 CLD nil Fv [ 0xFC] s:I86, t:FLAGOP, w:W, f:DF=0 STD nil Fv [ 0xFD] s:I86, t:FLAGOP, w:W, f:DF=1 -INC Eb Fv [ 0xFE /0] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK -DEC Eb Fv [ 0xFE /1] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK -INC Ev Fv [ 0xFF /0] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK -DEC Ev Fv [ 0xFF /1] s:I86, t:ARITH, w:RW|W, f:ARITH, p:HLE|LOCK +INC Eb Fv [ 0xFE /0] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK +DEC Eb Fv [ 0xFE /1] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK +INC Ev Fv [ 0xFF /0] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK +DEC Ev Fv [ 0xFF /1] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK CALL Ev rIP,Kv,SHS1 [ 0xFF /2] s:I86, t:CALL, c:CALLNI, w:R|W|W|W, a:F64|CETT, p:BND|DNT CALLF Mp CS,rIP,Kv2,SHS2 [ 0xFF /3:mem] s:I86, t:CALL, c:CALLFI, w:R|W|W|W|W, a:CETT, m:NOSGX JMP Ev rIP [ 0xFF /4] s:I86, t:UNCOND_BR, c:JMPNI, w:R|W, a:F64|CETT, p:BND|DNT